char/xillybus/xillybus.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * linux/drivers/misc/xillybus.h
0004  *
0005  * Copyright 2011 Xillybus Ltd, http://xillybus.com
0006  *
0007  * Header file for the Xillybus FPGA/host framework.
0008  */
0009
0010 #ifndef __XILLYBUS_H
0011 #define __XILLYBUS_H
0012
0013 #include <linux/list.h>
0014 #include <linux/device.h>
0015 #include <linux/dma-mapping.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/sched.h>
0018 #include <linux/cdev.h>
0019 #include <linux/spinlock.h>
0020 #include <linux/mutex.h>
0021 #include <linux/workqueue.h>
0022
0023 struct xilly_endpoint_hardware;
0024
0025 struct xilly_buffer {
0026     void *addr;
0027     dma_addr_t dma_addr;
0028     int end_offset; /* Counting elements, not bytes */
0029 };
0030
0031 struct xilly_idt_handle {
0032     unsigned char *chandesc;
0033     unsigned char *names;
0034     int names_len;
0035     int entries;
0036 };
0037
0038 /*
0039  * Read-write confusion: wr_* and rd_* notation sticks to FPGA view, so
0040  * wr_* buffers are those consumed by read(), since the FPGA writes to them
0041  * and vice versa.
0042  */
0043
0044 struct xilly_channel {
0045     struct xilly_endpoint *endpoint;
0046     int chan_num;
0047     int log2_element_size;
0048     int seekable;
0049
0050     struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */
0051     int num_wr_buffers;
0052     unsigned int wr_buf_size; /* In bytes */
0053     int wr_fpga_buf_idx;
0054     int wr_host_buf_idx;
0055     int wr_host_buf_pos;
0056     int wr_empty;
0057     int wr_ready; /* Significant only when wr_empty == 1 */
0058     int wr_sleepy;
0059     int wr_eof;
0060     int wr_hangup;
0061     spinlock_t wr_spinlock;
0062     struct mutex wr_mutex;
0063     wait_queue_head_t wr_wait;
0064     wait_queue_head_t wr_ready_wait;
0065     int wr_ref_count;
0066     int wr_synchronous;
0067     int wr_allow_partial;
0068     int wr_exclusive_open;
0069     int wr_supports_nonempty;
0070
0071     struct xilly_buffer **rd_buffers; /* FPGA reads, driver writes! */
0072     int num_rd_buffers;
0073     unsigned int rd_buf_size; /* In bytes */
0074     int rd_fpga_buf_idx;
0075     int rd_host_buf_pos;
0076     int rd_host_buf_idx;
0077     int rd_full;
0078     spinlock_t rd_spinlock;
0079     struct mutex rd_mutex;
0080     wait_queue_head_t rd_wait;
0081     int rd_ref_count;
0082     int rd_allow_partial;
0083     int rd_synchronous;
0084     int rd_exclusive_open;
0085     struct delayed_work rd_workitem;
0086     unsigned char rd_leftovers[4];
0087 };
0088
0089 struct xilly_endpoint {
0090     struct device *dev;
0091     struct module *owner;
0092
0093     int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */
0094     __iomem void *registers;
0095     int fatal_error;
0096
0097     struct mutex register_mutex;
0098     wait_queue_head_t ep_wait;
0099
0100     int num_channels; /* EXCLUDING message buffer */
0101     struct xilly_channel **channels;
0102     int msg_counter;
0103     int failed_messages;
0104     int idtlen;
0105
0106     u32 *msgbuf_addr;
0107     dma_addr_t msgbuf_dma_addr;
0108     unsigned int msg_buf_size;
0109 };
0110
0111 struct xilly_mapping {
0112     struct device *device;
0113     dma_addr_t dma_addr;
0114     size_t size;
0115     int direction;
0116 };
0117
0118 irqreturn_t xillybus_isr(int irq, void *data);
0119
0120 struct xilly_endpoint *xillybus_init_endpoint(struct device *dev);
0121
0122 int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint);
0123
0124 void xillybus_endpoint_remove(struct xilly_endpoint *endpoint);
0125
0126 #endif /* __XILLYBUS_H */