char/xilinx_hwicap/xilinx_hwicap.h

0001 /*****************************************************************************
0002  *
0003  *     Author: Xilinx, Inc.
0004  *
0005  *     This program is free software; you can redistribute it and/or modify it
0006  *     under the terms of the GNU General Public License as published by the
0007  *     Free Software Foundation; either version 2 of the License, or (at your
0008  *     option) any later version.
0009  *
0010  *     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
0011  *     AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
0012  *     SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
0013  *     OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
0014  *     APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
0015  *     THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
0016  *     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
0017  *     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
0018  *     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
0019  *     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
0020  *     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
0021  *     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
0022  *     FOR A PARTICULAR PURPOSE.
0023  *
0024  *     (c) Copyright 2003-2007 Xilinx Inc.
0025  *     All rights reserved.
0026  *
0027  *     You should have received a copy of the GNU General Public License along
0028  *     with this program; if not, write to the Free Software Foundation, Inc.,
0029  *     675 Mass Ave, Cambridge, MA 02139, USA.
0030  *
0031  *****************************************************************************/
0032
0033 #ifndef XILINX_HWICAP_H_    /* prevent circular inclusions */
0034 #define XILINX_HWICAP_H_    /* by using protection macros */
0035
0036 #include <linux/types.h>
0037 #include <linux/cdev.h>
0038 #include <linux/platform_device.h>
0039
0040 #include <linux/io.h>
0041
0042 struct hwicap_drvdata {
0043     u32 write_buffer_in_use;  /* Always in [0,3] */
0044     u8 write_buffer[4];
0045     u32 read_buffer_in_use;   /* Always in [0,3] */
0046     u8 read_buffer[4];
0047     resource_size_t mem_start;/* phys. address of the control registers */
0048     resource_size_t mem_end;  /* phys. address of the control registers */
0049     resource_size_t mem_size;
0050     void __iomem *base_address;/* virt. address of the control registers */
0051
0052     struct device *dev;
0053     struct cdev cdev;   /* Char device structure */
0054     dev_t devt;
0055
0056     const struct hwicap_driver_config *config;
0057     const struct config_registers *config_regs;
0058     void *private_data;
0059     bool is_open;
0060     struct mutex sem;
0061 };
0062
0063 struct hwicap_driver_config {
0064     /* Read configuration data given by size into the data buffer.
0065      * Return 0 if successful.
0066      */
0067     int (*get_configuration)(struct hwicap_drvdata *drvdata, u32 *data,
0068             u32 size);
0069     /* Write configuration data given by size from the data buffer.
0070      * Return 0 if successful.
0071      */
0072     int (*set_configuration)(struct hwicap_drvdata *drvdata, u32 *data,
0073             u32 size);
0074     /* Get the status register, bit pattern given by:
0075      * D8 - 0 = configuration error
0076      * D7 - 1 = alignment found
0077      * D6 - 1 = readback in progress
0078      * D5 - 0 = abort in progress
0079      * D4 - Always 1
0080      * D3 - Always 1
0081      * D2 - Always 1
0082      * D1 - Always 1
0083      * D0 - 1 = operation completed
0084      */
0085     u32 (*get_status)(struct hwicap_drvdata *drvdata);
0086     /* Reset the hw */
0087     void (*reset)(struct hwicap_drvdata *drvdata);
0088 };
0089
0090 /* Number of times to poll the done register. This has to be large
0091  * enough to allow an entire configuration to complete. If an entire
0092  * page (4kb) is configured at once, that could take up to 4k cycles
0093  * with a byte-wide icap interface. In most cases, this driver is
0094  * used with a much smaller fifo, but this should be sufficient in the
0095  * worst case.
0096  */
0097 #define XHI_MAX_RETRIES     5000
0098
0099 /************ Constant Definitions *************/
0100
0101 #define XHI_PAD_FRAMES              0x1
0102
0103 /* Mask for calculating configuration packet headers */
0104 #define XHI_WORD_COUNT_MASK_TYPE_1  0x7FFUL
0105 #define XHI_WORD_COUNT_MASK_TYPE_2  0x1FFFFFUL
0106 #define XHI_TYPE_MASK               0x7
0107 #define XHI_REGISTER_MASK           0xF
0108 #define XHI_OP_MASK                 0x3
0109
0110 #define XHI_TYPE_SHIFT              29
0111 #define XHI_REGISTER_SHIFT          13
0112 #define XHI_OP_SHIFT                27
0113
0114 #define XHI_TYPE_1                  1
0115 #define XHI_TYPE_2                  2
0116 #define XHI_OP_WRITE                2
0117 #define XHI_OP_READ                 1
0118
0119 /* Address Block Types */
0120 #define XHI_FAR_CLB_BLOCK           0
0121 #define XHI_FAR_BRAM_BLOCK          1
0122 #define XHI_FAR_BRAM_INT_BLOCK      2
0123
0124 struct config_registers {
0125     u32 CRC;
0126     u32 FAR;
0127     u32 FDRI;
0128     u32 FDRO;
0129     u32 CMD;
0130     u32 CTL;
0131     u32 MASK;
0132     u32 STAT;
0133     u32 LOUT;
0134     u32 COR;
0135     u32 MFWR;
0136     u32 FLR;
0137     u32 KEY;
0138     u32 CBC;
0139     u32 IDCODE;
0140     u32 AXSS;
0141     u32 C0R_1;
0142     u32 CSOB;
0143     u32 WBSTAR;
0144     u32 TIMER;
0145     u32 BOOTSTS;
0146     u32 CTL_1;
0147 };
0148
0149 /* Configuration Commands */
0150 #define XHI_CMD_NULL                0
0151 #define XHI_CMD_WCFG                1
0152 #define XHI_CMD_MFW                 2
0153 #define XHI_CMD_DGHIGH              3
0154 #define XHI_CMD_RCFG                4
0155 #define XHI_CMD_START               5
0156 #define XHI_CMD_RCAP                6
0157 #define XHI_CMD_RCRC                7
0158 #define XHI_CMD_AGHIGH              8
0159 #define XHI_CMD_SWITCH              9
0160 #define XHI_CMD_GRESTORE            10
0161 #define XHI_CMD_SHUTDOWN            11
0162 #define XHI_CMD_GCAPTURE            12
0163 #define XHI_CMD_DESYNCH             13
0164 #define XHI_CMD_IPROG               15 /* Only in Virtex5 */
0165 #define XHI_CMD_CRCC                16 /* Only in Virtex5 */
0166 #define XHI_CMD_LTIMER              17 /* Only in Virtex5 */
0167
0168 /* Packet constants */
0169 #define XHI_SYNC_PACKET             0xAA995566UL
0170 #define XHI_DUMMY_PACKET            0xFFFFFFFFUL
0171 #define XHI_NOOP_PACKET             (XHI_TYPE_1 << XHI_TYPE_SHIFT)
0172 #define XHI_TYPE_2_READ ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
0173             (XHI_OP_READ << XHI_OP_SHIFT))
0174
0175 #define XHI_TYPE_2_WRITE ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
0176             (XHI_OP_WRITE << XHI_OP_SHIFT))
0177
0178 #define XHI_TYPE2_CNT_MASK          0x07FFFFFF
0179
0180 #define XHI_TYPE_1_PACKET_MAX_WORDS 2047UL
0181 #define XHI_TYPE_1_HEADER_BYTES     4
0182 #define XHI_TYPE_2_HEADER_BYTES     8
0183
0184 /* Constant to use for CRC check when CRC has been disabled */
0185 #define XHI_DISABLED_AUTO_CRC       0x0000DEFCUL
0186
0187 /* Meanings of the bits returned by get_status */
0188 #define XHI_SR_CFGERR_N_MASK 0x00000100 /* Config Error Mask */
0189 #define XHI_SR_DALIGN_MASK 0x00000080 /* Data Alignment Mask */
0190 #define XHI_SR_RIP_MASK 0x00000040 /* Read back Mask */
0191 #define XHI_SR_IN_ABORT_N_MASK 0x00000020 /* Select Map Abort Mask */
0192 #define XHI_SR_DONE_MASK 0x00000001 /* Done bit Mask  */
0193
0194 /**
0195  * hwicap_type_1_read - Generates a Type 1 read packet header.
0196  * @reg: is the address of the register to be read back.
0197  *
0198  * Return:
0199  * Generates a Type 1 read packet header, which is used to indirectly
0200  * read registers in the configuration logic.  This packet must then
0201  * be sent through the icap device, and a return packet received with
0202  * the information.
0203  */
0204 static inline u32 hwicap_type_1_read(u32 reg)
0205 {
0206     return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
0207         (reg << XHI_REGISTER_SHIFT) |
0208         (XHI_OP_READ << XHI_OP_SHIFT);
0209 }
0210
0211 /**
0212  * hwicap_type_1_write - Generates a Type 1 write packet header
0213  * @reg: is the address of the register to be read back.
0214  *
0215  * Return: Type 1 write packet header
0216  */
0217 static inline u32 hwicap_type_1_write(u32 reg)
0218 {
0219     return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
0220         (reg << XHI_REGISTER_SHIFT) |
0221         (XHI_OP_WRITE << XHI_OP_SHIFT);
0222 }
0223
0224 #endif