char/tpm/tpm_tis_spi_cr50.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2016 Google, Inc
0004  *
0005  * This device driver implements a TCG PTP FIFO interface over SPI for chips
0006  * with Cr50 firmware.
0007  * It is based on tpm_tis_spi driver by Peter Huewe and Christophe Ricard.
0008  */
0009
0010 #include <linux/completion.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/pm.h>
0015 #include <linux/spi/spi.h>
0016 #include <linux/wait.h>
0017
0018 #include "tpm_tis_core.h"
0019 #include "tpm_tis_spi.h"
0020
0021 /*
0022  * Cr50 timing constants:
0023  * - can go to sleep not earlier than after CR50_SLEEP_DELAY_MSEC.
0024  * - needs up to CR50_WAKE_START_DELAY_USEC to wake after sleep.
0025  * - requires waiting for "ready" IRQ, if supported; or waiting for at least
0026  *   CR50_NOIRQ_ACCESS_DELAY_MSEC between transactions, if IRQ is not supported.
0027  * - waits for up to CR50_FLOW_CONTROL for flow control 'ready' indication.
0028  */
0029 #define CR50_SLEEP_DELAY_MSEC           1000
0030 #define CR50_WAKE_START_DELAY_USEC      1000
0031 #define CR50_NOIRQ_ACCESS_DELAY         msecs_to_jiffies(2)
0032 #define CR50_READY_IRQ_TIMEOUT          msecs_to_jiffies(TPM2_TIMEOUT_A)
0033 #define CR50_FLOW_CONTROL           msecs_to_jiffies(TPM2_TIMEOUT_A)
0034 #define MAX_IRQ_CONFIRMATION_ATTEMPTS       3
0035
0036 #define TPM_CR50_FW_VER(l)          (0x0f90 | ((l) << 12))
0037 #define TPM_CR50_MAX_FW_VER_LEN         64
0038
0039 /* Default quality for hwrng. */
0040 #define TPM_CR50_DEFAULT_RNG_QUALITY        700
0041
0042 struct cr50_spi_phy {
0043     struct tpm_tis_spi_phy spi_phy;
0044
0045     struct mutex time_track_mutex;
0046     unsigned long last_access;
0047
0048     unsigned long access_delay;
0049
0050     unsigned int irq_confirmation_attempt;
0051     bool irq_needs_confirmation;
0052     bool irq_confirmed;
0053 };
0054
0055 static inline struct cr50_spi_phy *to_cr50_spi_phy(struct tpm_tis_spi_phy *phy)
0056 {
0057     return container_of(phy, struct cr50_spi_phy, spi_phy);
0058 }
0059
0060 /*
0061  * The cr50 interrupt handler just signals waiting threads that the
0062  * interrupt was asserted.  It does not do any processing triggered
0063  * by interrupts but is instead used to avoid fixed delays.
0064  */
0065 static irqreturn_t cr50_spi_irq_handler(int dummy, void *dev_id)
0066 {
0067     struct cr50_spi_phy *cr50_phy = dev_id;
0068
0069     cr50_phy->irq_confirmed = true;
0070     complete(&cr50_phy->spi_phy.ready);
0071
0072     return IRQ_HANDLED;
0073 }
0074
0075 /*
0076  * Cr50 needs to have at least some delay between consecutive
0077  * transactions. Make sure we wait.
0078  */
0079 static void cr50_ensure_access_delay(struct cr50_spi_phy *phy)
0080 {
0081     unsigned long allowed_access = phy->last_access + phy->access_delay;
0082     unsigned long time_now = jiffies;
0083     struct device *dev = &phy->spi_phy.spi_device->dev;
0084
0085     /*
0086      * Note: There is a small chance, if Cr50 is not accessed in a few days,
0087      * that time_in_range will not provide the correct result after the wrap
0088      * around for jiffies. In this case, we'll have an unneeded short delay,
0089      * which is fine.
0090      */
0091     if (time_in_range_open(time_now, phy->last_access, allowed_access)) {
0092         unsigned long remaining, timeout = allowed_access - time_now;
0093
0094         remaining = wait_for_completion_timeout(&phy->spi_phy.ready,
0095                             timeout);
0096         if (!remaining && phy->irq_confirmed)
0097             dev_warn(dev, "Timeout waiting for TPM ready IRQ\n");
0098     }
0099
0100     if (phy->irq_needs_confirmation) {
0101         unsigned int attempt = ++phy->irq_confirmation_attempt;
0102
0103         if (phy->irq_confirmed) {
0104             phy->irq_needs_confirmation = false;
0105             phy->access_delay = CR50_READY_IRQ_TIMEOUT;
0106             dev_info(dev, "TPM ready IRQ confirmed on attempt %u\n",
0107                  attempt);
0108         } else if (attempt > MAX_IRQ_CONFIRMATION_ATTEMPTS) {
0109             phy->irq_needs_confirmation = false;
0110             dev_warn(dev, "IRQ not confirmed - will use delays\n");
0111         }
0112     }
0113 }
0114
0115 /*
0116  * Cr50 might go to sleep if there is no SPI activity for some time and
0117  * miss the first few bits/bytes on the bus. In such case, wake it up
0118  * by asserting CS and give it time to start up.
0119  */
0120 static bool cr50_needs_waking(struct cr50_spi_phy *phy)
0121 {
0122     /*
0123      * Note: There is a small chance, if Cr50 is not accessed in a few days,
0124      * that time_in_range will not provide the correct result after the wrap
0125      * around for jiffies. In this case, we'll probably timeout or read
0126      * incorrect value from TPM_STS and just retry the operation.
0127      */
0128     return !time_in_range_open(jiffies, phy->last_access,
0129                    phy->spi_phy.wake_after);
0130 }
0131
0132 static void cr50_wake_if_needed(struct cr50_spi_phy *cr50_phy)
0133 {
0134     struct tpm_tis_spi_phy *phy = &cr50_phy->spi_phy;
0135
0136     if (cr50_needs_waking(cr50_phy)) {
0137         /* Assert CS, wait 1 msec, deassert CS */
0138         struct spi_transfer spi_cs_wake = {
0139             .delay = {
0140                 .value = 1000,
0141                 .unit = SPI_DELAY_UNIT_USECS
0142             }
0143         };
0144
0145         spi_sync_transfer(phy->spi_device, &spi_cs_wake, 1);
0146         /* Wait for it to fully wake */
0147         usleep_range(CR50_WAKE_START_DELAY_USEC,
0148                  CR50_WAKE_START_DELAY_USEC * 2);
0149     }
0150
0151     /* Reset the time when we need to wake Cr50 again */
0152     phy->wake_after = jiffies + msecs_to_jiffies(CR50_SLEEP_DELAY_MSEC);
0153 }
0154
0155 /*
0156  * Flow control: clock the bus and wait for cr50 to set LSB before
0157  * sending/receiving data. TCG PTP spec allows it to happen during
0158  * the last byte of header, but cr50 never does that in practice,
0159  * and earlier versions had a bug when it was set too early, so don't
0160  * check for it during header transfer.
0161  */
0162 static int cr50_spi_flow_control(struct tpm_tis_spi_phy *phy,
0163                  struct spi_transfer *spi_xfer)
0164 {
0165     struct device *dev = &phy->spi_device->dev;
0166     unsigned long timeout = jiffies + CR50_FLOW_CONTROL;
0167     struct spi_message m;
0168     int ret;
0169
0170     spi_xfer->len = 1;
0171
0172     do {
0173         spi_message_init(&m);
0174         spi_message_add_tail(spi_xfer, &m);
0175         ret = spi_sync_locked(phy->spi_device, &m);
0176         if (ret < 0)
0177             return ret;
0178
0179         if (time_after(jiffies, timeout)) {
0180             dev_warn(dev, "Timeout during flow control\n");
0181             return -EBUSY;
0182         }
0183     } while (!(phy->iobuf[0] & 0x01));
0184
0185     return 0;
0186 }
0187
0188 static bool tpm_cr50_spi_is_firmware_power_managed(struct device *dev)
0189 {
0190     u8 val;
0191     int ret;
0192
0193     /* This flag should default true when the device property is not present */
0194     ret = device_property_read_u8(dev, "firmware-power-managed", &val);
0195     if (ret)
0196         return true;
0197
0198     return val;
0199 }
0200
0201 static int tpm_tis_spi_cr50_transfer(struct tpm_tis_data *data, u32 addr, u16 len,
0202                      u8 *in, const u8 *out)
0203 {
0204     struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
0205     struct cr50_spi_phy *cr50_phy = to_cr50_spi_phy(phy);
0206     int ret;
0207
0208     mutex_lock(&cr50_phy->time_track_mutex);
0209     /*
0210      * Do this outside of spi_bus_lock in case cr50 is not the
0211      * only device on that spi bus.
0212      */
0213     cr50_ensure_access_delay(cr50_phy);
0214     cr50_wake_if_needed(cr50_phy);
0215
0216     ret = tpm_tis_spi_transfer(data, addr, len, in, out);
0217
0218     cr50_phy->last_access = jiffies;
0219     mutex_unlock(&cr50_phy->time_track_mutex);
0220
0221     return ret;
0222 }
0223
0224 static int tpm_tis_spi_cr50_read_bytes(struct tpm_tis_data *data, u32 addr,
0225                        u16 len, u8 *result, enum tpm_tis_io_mode io_mode)
0226 {
0227     return tpm_tis_spi_cr50_transfer(data, addr, len, result, NULL);
0228 }
0229
0230 static int tpm_tis_spi_cr50_write_bytes(struct tpm_tis_data *data, u32 addr,
0231                     u16 len, const u8 *value, enum tpm_tis_io_mode io_mode)
0232 {
0233     return tpm_tis_spi_cr50_transfer(data, addr, len, NULL, value);
0234 }
0235
0236 static const struct tpm_tis_phy_ops tpm_spi_cr50_phy_ops = {
0237     .read_bytes = tpm_tis_spi_cr50_read_bytes,
0238     .write_bytes = tpm_tis_spi_cr50_write_bytes,
0239 };
0240
0241 static void cr50_print_fw_version(struct tpm_tis_data *data)
0242 {
0243     struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
0244     int i, len = 0;
0245     char fw_ver[TPM_CR50_MAX_FW_VER_LEN + 1];
0246     char fw_ver_block[4];
0247
0248     /*
0249      * Write anything to TPM_CR50_FW_VER to start from the beginning
0250      * of the version string
0251      */
0252     tpm_tis_write8(data, TPM_CR50_FW_VER(data->locality), 0);
0253
0254     /* Read the string, 4 bytes at a time, until we get '\0' */
0255     do {
0256         tpm_tis_read_bytes(data, TPM_CR50_FW_VER(data->locality), 4,
0257                    fw_ver_block);
0258         for (i = 0; i < 4 && fw_ver_block[i]; ++len, ++i)
0259             fw_ver[len] = fw_ver_block[i];
0260     } while (i == 4 && len < TPM_CR50_MAX_FW_VER_LEN);
0261     fw_ver[len] = '\0';
0262
0263     dev_info(&phy->spi_device->dev, "Cr50 firmware version: %s\n", fw_ver);
0264 }
0265
0266 int cr50_spi_probe(struct spi_device *spi)
0267 {
0268     struct tpm_tis_spi_phy *phy;
0269     struct cr50_spi_phy *cr50_phy;
0270     int ret;
0271     struct tpm_chip *chip;
0272
0273     cr50_phy = devm_kzalloc(&spi->dev, sizeof(*cr50_phy), GFP_KERNEL);
0274     if (!cr50_phy)
0275         return -ENOMEM;
0276
0277     phy = &cr50_phy->spi_phy;
0278     phy->flow_control = cr50_spi_flow_control;
0279     phy->wake_after = jiffies;
0280     phy->priv.rng_quality = TPM_CR50_DEFAULT_RNG_QUALITY;
0281     init_completion(&phy->ready);
0282
0283     cr50_phy->access_delay = CR50_NOIRQ_ACCESS_DELAY;
0284     cr50_phy->last_access = jiffies;
0285     mutex_init(&cr50_phy->time_track_mutex);
0286
0287     if (spi->irq > 0) {
0288         ret = devm_request_irq(&spi->dev, spi->irq,
0289                        cr50_spi_irq_handler,
0290                        IRQF_TRIGGER_RISING | IRQF_ONESHOT,
0291                        "cr50_spi", cr50_phy);
0292         if (ret < 0) {
0293             if (ret == -EPROBE_DEFER)
0294                 return ret;
0295             dev_warn(&spi->dev, "Requesting IRQ %d failed: %d\n",
0296                  spi->irq, ret);
0297             /*
0298              * This is not fatal, the driver will fall back to
0299              * delays automatically, since ready will never
0300              * be completed without a registered irq handler.
0301              * So, just fall through.
0302              */
0303         } else {
0304             /*
0305              * IRQ requested, let's verify that it is actually
0306              * triggered, before relying on it.
0307              */
0308             cr50_phy->irq_needs_confirmation = true;
0309         }
0310     } else {
0311         dev_warn(&spi->dev,
0312              "No IRQ - will use delays between transactions.\n");
0313     }
0314
0315     ret = tpm_tis_spi_init(spi, phy, -1, &tpm_spi_cr50_phy_ops);
0316     if (ret)
0317         return ret;
0318
0319     cr50_print_fw_version(&phy->priv);
0320
0321     chip = dev_get_drvdata(&spi->dev);
0322     if (tpm_cr50_spi_is_firmware_power_managed(&spi->dev))
0323         chip->flags |= TPM_CHIP_FLAG_FIRMWARE_POWER_MANAGED;
0324
0325     return 0;
0326 }
0327
0328 #ifdef CONFIG_PM_SLEEP
0329 int tpm_tis_spi_resume(struct device *dev)
0330 {
0331     struct tpm_chip *chip = dev_get_drvdata(dev);
0332     struct tpm_tis_data *data = dev_get_drvdata(&chip->dev);
0333     struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
0334     /*
0335      * Jiffies not increased during suspend, so we need to reset
0336      * the time to wake Cr50 after resume.
0337      */
0338     phy->wake_after = jiffies;
0339
0340     return tpm_tis_resume(dev);
0341 }
0342 #endif