char/tpm/tpm_tis_i2c.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2014-2021 Nuvoton Technology corporation
0004  * Copyright (C) 2019-2022 Infineon Technologies AG
0005  *
0006  * This device driver implements the TPM interface as defined in the TCG PC
0007  * Client Platform TPM Profile (PTP) Specification for TPM 2.0 v1.04
0008  * Revision 14.
0009  *
0010  * It is based on the tpm_tis_spi device driver.
0011  */
0012
0013 #include <linux/i2c.h>
0014 #include <linux/crc-ccitt.h>
0015 #include "tpm_tis_core.h"
0016
0017 /* TPM registers */
0018 #define TPM_I2C_LOC_SEL 0x00
0019 #define TPM_I2C_ACCESS 0x04
0020 #define TPM_I2C_INTERFACE_CAPABILITY 0x30
0021 #define TPM_I2C_DEVICE_ADDRESS 0x38
0022 #define TPM_I2C_DATA_CSUM_ENABLE 0x40
0023 #define TPM_DATA_CSUM 0x44
0024 #define TPM_I2C_DID_VID 0x48
0025 #define TPM_I2C_RID 0x4C
0026
0027 /* TIS-compatible register address to avoid clash with TPM_ACCESS (0x00) */
0028 #define TPM_LOC_SEL 0x0FFF
0029
0030 /* Mask to extract the I2C register from TIS register addresses */
0031 #define TPM_TIS_REGISTER_MASK 0x0FFF
0032
0033 /* Default Guard Time of 250µs until interface capability register is read */
0034 #define GUARD_TIME_DEFAULT_MIN 250
0035 #define GUARD_TIME_DEFAULT_MAX 300
0036
0037 /* Guard Time of 250µs after I2C slave NACK */
0038 #define GUARD_TIME_ERR_MIN 250
0039 #define GUARD_TIME_ERR_MAX 300
0040
0041 /* Guard Time bit masks; SR is repeated start, RW is read then write, etc. */
0042 #define TPM_GUARD_TIME_SR_MASK 0x40000000
0043 #define TPM_GUARD_TIME_RR_MASK 0x00100000
0044 #define TPM_GUARD_TIME_RW_MASK 0x00080000
0045 #define TPM_GUARD_TIME_WR_MASK 0x00040000
0046 #define TPM_GUARD_TIME_WW_MASK 0x00020000
0047 #define TPM_GUARD_TIME_MIN_MASK 0x0001FE00
0048 #define TPM_GUARD_TIME_MIN_SHIFT 9
0049
0050 /* Masks with bits that must be read zero */
0051 #define TPM_ACCESS_READ_ZERO 0x48
0052 #define TPM_INT_ENABLE_ZERO 0x7FFFFF6
0053 #define TPM_STS_READ_ZERO 0x23
0054 #define TPM_INTF_CAPABILITY_ZERO 0x0FFFF000
0055 #define TPM_I2C_INTERFACE_CAPABILITY_ZERO 0x80000000
0056
0057 struct tpm_tis_i2c_phy {
0058     struct tpm_tis_data priv;
0059     struct i2c_client *i2c_client;
0060     bool guard_time_read;
0061     bool guard_time_write;
0062     u16 guard_time_min;
0063     u16 guard_time_max;
0064     u8 *io_buf;
0065 };
0066
0067 static inline struct tpm_tis_i2c_phy *
0068 to_tpm_tis_i2c_phy(struct tpm_tis_data *data)
0069 {
0070     return container_of(data, struct tpm_tis_i2c_phy, priv);
0071 }
0072
0073 /*
0074  * tpm_tis_core uses the register addresses as defined in Table 19 "Allocation
0075  * of Register Space for FIFO TPM Access" of the TCG PC Client PTP
0076  * Specification. In order for this code to work together with tpm_tis_core,
0077  * those addresses need to mapped to the registers defined for I2C TPMs in
0078  * Table 51 "I2C-TPM Register Overview".
0079  *
0080  * For most addresses this can be done by simply stripping off the locality
0081  * information from the address. A few addresses need to be mapped explicitly,
0082  * since the corresponding I2C registers have been moved around. TPM_LOC_SEL is
0083  * only defined for I2C TPMs and is also mapped explicitly here to distinguish
0084  * it from TPM_ACCESS(0).
0085  *
0086  * Locality information is ignored, since this driver assumes exclusive access
0087  * to the TPM and always uses locality 0.
0088  */
0089 static u8 tpm_tis_i2c_address_to_register(u32 addr)
0090 {
0091     addr &= TPM_TIS_REGISTER_MASK;
0092
0093     switch (addr) {
0094     case TPM_ACCESS(0):
0095         return TPM_I2C_ACCESS;
0096     case TPM_LOC_SEL:
0097         return TPM_I2C_LOC_SEL;
0098     case TPM_DID_VID(0):
0099         return TPM_I2C_DID_VID;
0100     case TPM_RID(0):
0101         return TPM_I2C_RID;
0102     default:
0103         return addr;
0104     }
0105 }
0106
0107 static int tpm_tis_i2c_retry_transfer_until_ack(struct tpm_tis_data *data,
0108                         struct i2c_msg *msg)
0109 {
0110     struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
0111     bool guard_time;
0112     int i = 0;
0113     int ret;
0114
0115     if (msg->flags & I2C_M_RD)
0116         guard_time = phy->guard_time_read;
0117     else
0118         guard_time = phy->guard_time_write;
0119
0120     do {
0121         ret = i2c_transfer(phy->i2c_client->adapter, msg, 1);
0122         if (ret < 0)
0123             usleep_range(GUARD_TIME_ERR_MIN, GUARD_TIME_ERR_MAX);
0124         else if (guard_time)
0125             usleep_range(phy->guard_time_min, phy->guard_time_max);
0126         /* retry on TPM NACK */
0127     } while (ret < 0 && i++ < TPM_RETRY);
0128
0129     return ret;
0130 }
0131
0132 /* Check that bits which must be read zero are not set */
0133 static int tpm_tis_i2c_sanity_check_read(u8 reg, u16 len, u8 *buf)
0134 {
0135     u32 zero_mask;
0136     u32 value;
0137
0138     switch (len) {
0139     case sizeof(u8):
0140         value = buf[0];
0141         break;
0142     case sizeof(u16):
0143         value = le16_to_cpup((__le16 *)buf);
0144         break;
0145     case sizeof(u32):
0146         value = le32_to_cpup((__le32 *)buf);
0147         break;
0148     default:
0149         /* unknown length, skip check */
0150         return 0;
0151     }
0152
0153     switch (reg) {
0154     case TPM_I2C_ACCESS:
0155         zero_mask = TPM_ACCESS_READ_ZERO;
0156         break;
0157     case TPM_INT_ENABLE(0) & TPM_TIS_REGISTER_MASK:
0158         zero_mask = TPM_INT_ENABLE_ZERO;
0159         break;
0160     case TPM_STS(0) & TPM_TIS_REGISTER_MASK:
0161         zero_mask = TPM_STS_READ_ZERO;
0162         break;
0163     case TPM_INTF_CAPS(0) & TPM_TIS_REGISTER_MASK:
0164         zero_mask = TPM_INTF_CAPABILITY_ZERO;
0165         break;
0166     case TPM_I2C_INTERFACE_CAPABILITY:
0167         zero_mask = TPM_I2C_INTERFACE_CAPABILITY_ZERO;
0168         break;
0169     default:
0170         /* unknown register, skip check */
0171         return 0;
0172     }
0173
0174     if (unlikely((value & zero_mask) != 0x00)) {
0175         pr_debug("TPM I2C read of register 0x%02x failed sanity check: 0x%x\n", reg, value);
0176         return -EIO;
0177     }
0178
0179     return 0;
0180 }
0181
0182 static int tpm_tis_i2c_read_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
0183                   u8 *result, enum tpm_tis_io_mode io_mode)
0184 {
0185     struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
0186     struct i2c_msg msg = { .addr = phy->i2c_client->addr };
0187     u8 reg = tpm_tis_i2c_address_to_register(addr);
0188     int i;
0189     int ret;
0190
0191     for (i = 0; i < TPM_RETRY; i++) {
0192         /* write register */
0193         msg.len = sizeof(reg);
0194         msg.buf = &reg;
0195         msg.flags = 0;
0196         ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
0197         if (ret < 0)
0198             return ret;
0199
0200         /* read data */
0201         msg.buf = result;
0202         msg.len = len;
0203         msg.flags = I2C_M_RD;
0204         ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
0205         if (ret < 0)
0206             return ret;
0207
0208         ret = tpm_tis_i2c_sanity_check_read(reg, len, result);
0209         if (ret == 0)
0210             return 0;
0211
0212         usleep_range(GUARD_TIME_ERR_MIN, GUARD_TIME_ERR_MAX);
0213     }
0214
0215     return ret;
0216 }
0217
0218 static int tpm_tis_i2c_write_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
0219                    const u8 *value,
0220                    enum tpm_tis_io_mode io_mode)
0221 {
0222     struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
0223     struct i2c_msg msg = { .addr = phy->i2c_client->addr };
0224     u8 reg = tpm_tis_i2c_address_to_register(addr);
0225     int ret;
0226
0227     if (len > TPM_BUFSIZE - 1)
0228         return -EIO;
0229
0230     /* write register and data in one go */
0231     phy->io_buf[0] = reg;
0232     memcpy(phy->io_buf + sizeof(reg), value, len);
0233
0234     msg.len = sizeof(reg) + len;
0235     msg.buf = phy->io_buf;
0236     ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
0237     if (ret < 0)
0238         return ret;
0239
0240     return 0;
0241 }
0242
0243 static int tpm_tis_i2c_verify_crc(struct tpm_tis_data *data, size_t len,
0244                   const u8 *value)
0245 {
0246     u16 crc_tpm, crc_host;
0247     int rc;
0248
0249     rc = tpm_tis_read16(data, TPM_DATA_CSUM, &crc_tpm);
0250     if (rc < 0)
0251         return rc;
0252
0253     /* reflect crc result, regardless of host endianness */
0254     crc_host = swab16(crc_ccitt(0, value, len));
0255     if (crc_tpm != crc_host)
0256         return -EIO;
0257
0258     return 0;
0259 }
0260
0261 /*
0262  * Guard Time:
0263  * After each I2C operation, the TPM might require the master to wait.
0264  * The time period is vendor-specific and must be read from the
0265  * TPM_I2C_INTERFACE_CAPABILITY register.
0266  *
0267  * Before the Guard Time is read (or after the TPM failed to send an I2C NACK),
0268  * a Guard Time of 250µs applies.
0269  *
0270  * Various flags in the same register indicate if a guard time is needed:
0271  *  - SR: <I2C read with repeated start> <guard time> <I2C read>
0272  *  - RR: <I2C read> <guard time> <I2C read>
0273  *  - RW: <I2C read> <guard time> <I2C write>
0274  *  - WR: <I2C write> <guard time> <I2C read>
0275  *  - WW: <I2C write> <guard time> <I2C write>
0276  *
0277  * See TCG PC Client PTP Specification v1.04, 8.1.10 GUARD_TIME
0278  */
0279 static int tpm_tis_i2c_init_guard_time(struct tpm_tis_i2c_phy *phy)
0280 {
0281     u32 i2c_caps;
0282     int ret;
0283
0284     phy->guard_time_read = true;
0285     phy->guard_time_write = true;
0286     phy->guard_time_min = GUARD_TIME_DEFAULT_MIN;
0287     phy->guard_time_max = GUARD_TIME_DEFAULT_MAX;
0288
0289     ret = tpm_tis_i2c_read_bytes(&phy->priv, TPM_I2C_INTERFACE_CAPABILITY,
0290                      sizeof(i2c_caps), (u8 *)&i2c_caps,
0291                      TPM_TIS_PHYS_32);
0292     if (ret)
0293         return ret;
0294
0295     phy->guard_time_read = (i2c_caps & TPM_GUARD_TIME_RR_MASK) ||
0296                    (i2c_caps & TPM_GUARD_TIME_RW_MASK);
0297     phy->guard_time_write = (i2c_caps & TPM_GUARD_TIME_WR_MASK) ||
0298                 (i2c_caps & TPM_GUARD_TIME_WW_MASK);
0299     phy->guard_time_min = (i2c_caps & TPM_GUARD_TIME_MIN_MASK) >>
0300                   TPM_GUARD_TIME_MIN_SHIFT;
0301     /* guard_time_max = guard_time_min * 1.2 */
0302     phy->guard_time_max = phy->guard_time_min + phy->guard_time_min / 5;
0303
0304     return 0;
0305 }
0306
0307 static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume);
0308
0309 static const struct tpm_tis_phy_ops tpm_i2c_phy_ops = {
0310     .read_bytes = tpm_tis_i2c_read_bytes,
0311     .write_bytes = tpm_tis_i2c_write_bytes,
0312     .verify_crc = tpm_tis_i2c_verify_crc,
0313 };
0314
0315 static int tpm_tis_i2c_probe(struct i2c_client *dev,
0316                  const struct i2c_device_id *id)
0317 {
0318     struct tpm_tis_i2c_phy *phy;
0319     const u8 crc_enable = 1;
0320     const u8 locality = 0;
0321     int ret;
0322
0323     phy = devm_kzalloc(&dev->dev, sizeof(struct tpm_tis_i2c_phy),
0324                GFP_KERNEL);
0325     if (!phy)
0326         return -ENOMEM;
0327
0328     phy->io_buf = devm_kzalloc(&dev->dev, TPM_BUFSIZE, GFP_KERNEL);
0329     if (!phy->io_buf)
0330         return -ENOMEM;
0331
0332     phy->i2c_client = dev;
0333
0334     /* must precede all communication with the tpm */
0335     ret = tpm_tis_i2c_init_guard_time(phy);
0336     if (ret)
0337         return ret;
0338
0339     ret = tpm_tis_i2c_write_bytes(&phy->priv, TPM_LOC_SEL, sizeof(locality),
0340                       &locality, TPM_TIS_PHYS_8);
0341     if (ret)
0342         return ret;
0343
0344     ret = tpm_tis_i2c_write_bytes(&phy->priv, TPM_I2C_DATA_CSUM_ENABLE,
0345                       sizeof(crc_enable), &crc_enable,
0346                       TPM_TIS_PHYS_8);
0347     if (ret)
0348         return ret;
0349
0350     return tpm_tis_core_init(&dev->dev, &phy->priv, -1, &tpm_i2c_phy_ops,
0351                  NULL);
0352 }
0353
0354 static int tpm_tis_i2c_remove(struct i2c_client *client)
0355 {
0356     struct tpm_chip *chip = i2c_get_clientdata(client);
0357
0358     tpm_chip_unregister(chip);
0359     tpm_tis_remove(chip);
0360     return 0;
0361 }
0362
0363 static const struct i2c_device_id tpm_tis_i2c_id[] = {
0364     { "tpm_tis_i2c", 0 },
0365     {}
0366 };
0367 MODULE_DEVICE_TABLE(i2c, tpm_tis_i2c_id);
0368
0369 #ifdef CONFIG_OF
0370 static const struct of_device_id of_tis_i2c_match[] = {
0371     { .compatible = "infineon,slb9673", },
0372     {}
0373 };
0374 MODULE_DEVICE_TABLE(of, of_tis_i2c_match);
0375 #endif
0376
0377 static struct i2c_driver tpm_tis_i2c_driver = {
0378     .driver = {
0379         .name = "tpm_tis_i2c",
0380         .pm = &tpm_tis_pm,
0381         .of_match_table = of_match_ptr(of_tis_i2c_match),
0382     },
0383     .probe = tpm_tis_i2c_probe,
0384     .remove = tpm_tis_i2c_remove,
0385     .id_table = tpm_tis_i2c_id,
0386 };
0387 module_i2c_driver(tpm_tis_i2c_driver);
0388
0389 MODULE_DESCRIPTION("TPM Driver for native I2C access");
0390 MODULE_LICENSE("GPL");