char/mwave/3780i.h

0001 /*
0002 *
0003 * 3780i.h -- declarations for 3780i.c
0004 *
0005 *
0006 * Written By: Mike Sullivan IBM Corporation
0007 *
0008 * Copyright (C) 1999 IBM Corporation
0009 *
0010 * This program is free software; you can redistribute it and/or modify
0011 * it under the terms of the GNU General Public License as published by
0012 * the Free Software Foundation; either version 2 of the License, or
0013 * (at your option) any later version.
0014 *
0015 * This program is distributed in the hope that it will be useful,
0016 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0017 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0018 * GNU General Public License for more details.
0019 *
0020 * NO WARRANTY
0021 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
0022 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
0023 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
0024 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
0025 * solely responsible for determining the appropriateness of using and
0026 * distributing the Program and assumes all risks associated with its
0027 * exercise of rights under this Agreement, including but not limited to
0028 * the risks and costs of program errors, damage to or loss of data,
0029 * programs or equipment, and unavailability or interruption of operations.
0030 *
0031 * DISCLAIMER OF LIABILITY
0032 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
0033 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0034 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
0035 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
0036 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
0037 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
0038 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
0039 *
0040 * You should have received a copy of the GNU General Public License
0041 * along with this program; if not, write to the Free Software
0042 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
0043 *
0044 *
0045 * 10/23/2000 - Alpha Release
0046 *   First release to the public
0047 */
0048
0049 #ifndef _LINUX_3780I_H
0050 #define _LINUX_3780I_H
0051
0052 #include <asm/io.h>
0053
0054 /* DSP I/O port offsets and definitions */
0055 #define DSP_IsaSlaveControl        0x0000   /* ISA slave control register */
0056 #define DSP_IsaSlaveStatus         0x0001   /* ISA slave status register */
0057 #define DSP_ConfigAddress          0x0002   /* General config address register */
0058 #define DSP_ConfigData             0x0003   /* General config data register */
0059 #define DSP_HBridgeControl         0x0002   /* HBridge control register */
0060 #define DSP_MsaAddrLow             0x0004   /* MSP System Address, low word */
0061 #define DSP_MsaAddrHigh            0x0006   /* MSP System Address, high word */
0062 #define DSP_MsaDataDSISHigh        0x0008   /* MSA data register: d-store word or high byte of i-store */
0063 #define DSP_MsaDataISLow           0x000A   /* MSA data register: low word of i-store */
0064 #define DSP_ReadAndClear           0x000C   /* MSA read and clear data register */
0065 #define DSP_Interrupt              0x000E   /* Interrupt register (IPC source) */
0066
0067 typedef struct {
0068     unsigned char ClockControl:1;   /* RW: Clock control: 0=normal, 1=stop 3780i clocks */
0069     unsigned char SoftReset:1;  /* RW: Soft reset 0=normal, 1=soft reset active */
0070     unsigned char ConfigMode:1; /* RW: Configuration mode, 0=normal, 1=config mode */
0071     unsigned short Reserved:13; /* 0: Reserved */
0072 } DSP_ISA_SLAVE_CONTROL;
0073
0074
0075 typedef struct {
0076     unsigned short EnableDspInt:1;  /* RW: Enable DSP to X86 ISA interrupt 0=mask it, 1=enable it */
0077     unsigned short MemAutoInc:1;    /* RW: Memory address auto increment, 0=disable, 1=enable */
0078     unsigned short IoAutoInc:1; /* RW: I/O address auto increment, 0=disable, 1=enable */
0079     unsigned short DiagnosticMode:1;    /* RW: Disgnostic mode 0=nromal, 1=diagnostic mode */
0080     unsigned short IsaPacingTimer:12;   /* R: ISA access pacing timer: count of core cycles stolen */
0081 } DSP_HBRIDGE_CONTROL;
0082
0083
0084 /* DSP register indexes used with the configuration register address (index) register */
0085 #define DSP_UartCfg1Index          0x0003   /* UART config register 1 */
0086 #define DSP_UartCfg2Index          0x0004   /* UART config register 2 */
0087 #define DSP_HBridgeCfg1Index       0x0007   /* HBridge config register 1 */
0088 #define DSP_HBridgeCfg2Index       0x0008   /* HBridge config register 2 */
0089 #define DSP_BusMasterCfg1Index     0x0009   /* ISA bus master config register 1 */
0090 #define DSP_BusMasterCfg2Index     0x000A   /* ISA bus master config register 2 */
0091 #define DSP_IsaProtCfgIndex        0x000F   /* ISA protocol control register */
0092 #define DSP_PowerMgCfgIndex        0x0010   /* Low poser suspend/resume enable */
0093 #define DSP_HBusTimerCfgIndex      0x0011   /* HBUS timer load value */
0094
0095 typedef struct {
0096     unsigned char IrqActiveLow:1;   /* RW: IRQ active high or low: 0=high, 1=low */
0097     unsigned char IrqPulse:1;   /* RW: IRQ pulse or level: 0=level, 1=pulse  */
0098     unsigned char Irq:3;    /* RW: IRQ selection */
0099     unsigned char BaseIO:2; /* RW: Base I/O selection */
0100     unsigned char Reserved:1;   /* 0: Reserved */
0101 } DSP_UART_CFG_1;
0102
0103 typedef struct {
0104     unsigned char Enable:1; /* RW: Enable I/O and IRQ: 0=false, 1=true */
0105     unsigned char Reserved:7;   /* 0: Reserved */
0106 } DSP_UART_CFG_2;
0107
0108 typedef struct {
0109     unsigned char IrqActiveLow:1;   /* RW: IRQ active high=0 or low=1 */
0110     unsigned char IrqPulse:1;   /* RW: IRQ pulse=1 or level=0 */
0111     unsigned char Irq:3;    /* RW: IRQ selection */
0112     unsigned char AccessMode:1; /* RW: 16-bit register access method 0=byte, 1=word */
0113     unsigned char Reserved:2;   /* 0: Reserved */
0114 } DSP_HBRIDGE_CFG_1;
0115
0116 typedef struct {
0117     unsigned char Enable:1; /* RW: enable I/O and IRQ: 0=false, 1=true */
0118     unsigned char Reserved:7;   /* 0: Reserved */
0119 } DSP_HBRIDGE_CFG_2;
0120
0121
0122 typedef struct {
0123     unsigned char Dma:3;    /* RW: DMA channel selection */
0124     unsigned char NumTransfers:2;   /* RW: Maximum # of transfers once being granted the ISA bus */
0125     unsigned char ReRequest:2;  /* RW: Minimum delay between releasing the ISA bus and requesting it again */
0126     unsigned char MEMCS16:1;    /* RW: ISA signal MEMCS16: 0=disabled, 1=enabled */
0127 } DSP_BUSMASTER_CFG_1;
0128
0129 typedef struct {
0130     unsigned char IsaMemCmdWidth:2; /* RW: ISA memory command width */
0131     unsigned char Reserved:6;   /* 0: Reserved */
0132 } DSP_BUSMASTER_CFG_2;
0133
0134
0135 typedef struct {
0136     unsigned char GateIOCHRDY:1;    /* RW: Enable IOCHRDY gating: 0=false, 1=true */
0137     unsigned char Reserved:7;   /* 0: Reserved */
0138 } DSP_ISA_PROT_CFG;
0139
0140 typedef struct {
0141     unsigned char Enable:1; /* RW: Enable low power suspend/resume 0=false, 1=true */
0142     unsigned char Reserved:7;   /* 0: Reserved */
0143 } DSP_POWER_MGMT_CFG;
0144
0145 typedef struct {
0146     unsigned char LoadValue:8;  /* RW: HBUS timer load value */
0147 } DSP_HBUS_TIMER_CFG;
0148
0149
0150
0151 /* DSP registers that exist in MSA I/O space */
0152 #define DSP_ChipID                 0x80000000
0153 #define DSP_MspBootDomain          0x80000580
0154 #define DSP_LBusTimeoutDisable     0x80000580
0155 #define DSP_ClockControl_1         0x8000058A
0156 #define DSP_ClockControl_2         0x8000058C
0157 #define DSP_ChipReset              0x80000588
0158 #define DSP_GpioModeControl_15_8   0x80000082
0159 #define DSP_GpioDriverEnable_15_8  0x80000076
0160 #define DSP_GpioOutputData_15_8    0x80000072
0161
0162 typedef struct {
0163     unsigned short NMI:1;   /* RW: non maskable interrupt */
0164     unsigned short Halt:1;  /* RW: Halt MSP clock */
0165     unsigned short ResetCore:1; /* RW: Reset MSP core interface */
0166     unsigned short Reserved:13; /* 0: Reserved */
0167 } DSP_BOOT_DOMAIN;
0168
0169 typedef struct {
0170     unsigned short DisableTimeout:1;    /* RW: Disable LBus timeout */
0171     unsigned short Reserved:15; /* 0: Reserved */
0172 } DSP_LBUS_TIMEOUT_DISABLE;
0173
0174 typedef struct {
0175     unsigned short Memory:1;    /* RW: Reset memory interface */
0176     unsigned short SerialPort1:1;   /* RW: Reset serial port 1 interface */
0177     unsigned short SerialPort2:1;   /* RW: Reset serial port 2 interface */
0178     unsigned short SerialPort3:1;   /* RW: Reset serial port 3 interface */
0179     unsigned short Gpio:1;  /* RW: Reset GPIO interface */
0180     unsigned short Dma:1;   /* RW: Reset DMA interface */
0181     unsigned short SoundBlaster:1;  /* RW: Reset soundblaster interface */
0182     unsigned short Uart:1;  /* RW: Reset UART interface */
0183     unsigned short Midi:1;  /* RW: Reset MIDI interface */
0184     unsigned short IsaMaster:1; /* RW: Reset ISA master interface */
0185     unsigned short Reserved:6;  /* 0: Reserved */
0186 } DSP_CHIP_RESET;
0187
0188 typedef struct {
0189     unsigned short N_Divisor:6; /* RW: (N) PLL output clock divisor */
0190     unsigned short Reserved1:2; /* 0: reserved */
0191     unsigned short M_Multiplier:6;  /* RW: (M) PLL feedback clock multiplier */
0192     unsigned short Reserved2:2; /* 0: reserved */
0193 } DSP_CLOCK_CONTROL_1;
0194
0195 typedef struct {
0196     unsigned short PllBypass:1; /* RW: PLL Bypass */
0197     unsigned short Reserved:15; /* 0: Reserved */
0198 } DSP_CLOCK_CONTROL_2;
0199
0200 typedef struct {
0201     unsigned short Latch8:1;
0202     unsigned short Latch9:1;
0203     unsigned short Latch10:1;
0204     unsigned short Latch11:1;
0205     unsigned short Latch12:1;
0206     unsigned short Latch13:1;
0207     unsigned short Latch14:1;
0208     unsigned short Latch15:1;
0209     unsigned short Mask8:1;
0210     unsigned short Mask9:1;
0211     unsigned short Mask10:1;
0212     unsigned short Mask11:1;
0213     unsigned short Mask12:1;
0214     unsigned short Mask13:1;
0215     unsigned short Mask14:1;
0216     unsigned short Mask15:1;
0217 } DSP_GPIO_OUTPUT_DATA_15_8;
0218
0219 typedef struct {
0220     unsigned short Enable8:1;
0221     unsigned short Enable9:1;
0222     unsigned short Enable10:1;
0223     unsigned short Enable11:1;
0224     unsigned short Enable12:1;
0225     unsigned short Enable13:1;
0226     unsigned short Enable14:1;
0227     unsigned short Enable15:1;
0228     unsigned short Mask8:1;
0229     unsigned short Mask9:1;
0230     unsigned short Mask10:1;
0231     unsigned short Mask11:1;
0232     unsigned short Mask12:1;
0233     unsigned short Mask13:1;
0234     unsigned short Mask14:1;
0235     unsigned short Mask15:1;
0236 } DSP_GPIO_DRIVER_ENABLE_15_8;
0237
0238 typedef struct {
0239     unsigned short GpioMode8:2;
0240     unsigned short GpioMode9:2;
0241     unsigned short GpioMode10:2;
0242     unsigned short GpioMode11:2;
0243     unsigned short GpioMode12:2;
0244     unsigned short GpioMode13:2;
0245     unsigned short GpioMode14:2;
0246     unsigned short GpioMode15:2;
0247 } DSP_GPIO_MODE_15_8;
0248
0249 /* Component masks that are defined in dspmgr.h */
0250 #define MW_ADC_MASK    0x0001
0251 #define MW_AIC2_MASK   0x0006
0252 #define MW_MIDI_MASK   0x0008
0253 #define MW_CDDAC_MASK  0x8001
0254 #define MW_AIC1_MASK   0xE006
0255 #define MW_UART_MASK   0xE00A
0256 #define MW_ACI_MASK    0xE00B
0257
0258 /*
0259 * Definition of 3780i configuration structure.  Unless otherwise stated,
0260 * these values are provided as input to the 3780i support layer.  At present,
0261 * the only values maintained by the 3780i support layer are the saved UART
0262 * registers.
0263 */
0264 typedef struct _DSP_3780I_CONFIG_SETTINGS {
0265
0266     /* Location of base configuration register */
0267     unsigned short usBaseConfigIO;
0268
0269     /* Enables for various DSP components */
0270     int bDSPEnabled;
0271     int bModemEnabled;
0272     int bInterruptClaimed;
0273
0274     /* IRQ, DMA, and Base I/O addresses for various DSP components */
0275     unsigned short usDspIrq;
0276     unsigned short usDspDma;
0277     unsigned short usDspBaseIO;
0278     unsigned short usUartIrq;
0279     unsigned short usUartBaseIO;
0280
0281     /* IRQ modes for various DSP components */
0282     int bDspIrqActiveLow;
0283     int bUartIrqActiveLow;
0284     int bDspIrqPulse;
0285     int bUartIrqPulse;
0286
0287     /* Card abilities */
0288     unsigned uIps;
0289     unsigned uDStoreSize;
0290     unsigned uIStoreSize;
0291     unsigned uDmaBandwidth;
0292
0293     /* Adapter specific 3780i settings */
0294     unsigned short usNumTransfers;
0295     unsigned short usReRequest;
0296     int bEnableMEMCS16;
0297     unsigned short usIsaMemCmdWidth;
0298     int bGateIOCHRDY;
0299     int bEnablePwrMgmt;
0300     unsigned short usHBusTimerLoadValue;
0301     int bDisableLBusTimeout;
0302     unsigned short usN_Divisor;
0303     unsigned short usM_Multiplier;
0304     int bPllBypass;
0305     unsigned short usChipletEnable; /* Used with the chip reset register to enable specific chiplets */
0306
0307     /* Saved UART registers. These are maintained by the 3780i support layer. */
0308     int bUartSaved;     /* True after a successful save of the UART registers */
0309     unsigned char ucIER;    /* Interrupt enable register */
0310     unsigned char ucFCR;    /* FIFO control register */
0311     unsigned char ucLCR;    /* Line control register */
0312     unsigned char ucMCR;    /* Modem control register */
0313     unsigned char ucSCR;    /* Scratch register */
0314     unsigned char ucDLL;    /* Divisor latch, low byte */
0315     unsigned char ucDLM;    /* Divisor latch, high byte */
0316 } DSP_3780I_CONFIG_SETTINGS;
0317
0318
0319 /* 3780i support functions */
0320 int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings,
0321                        unsigned short *pIrqMap,
0322                        unsigned short *pDmaMap);
0323 int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings);
0324 int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings);
0325 int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings);
0326 int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
0327                         unsigned uCount, unsigned long ulDSPAddr);
0328 int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO,
0329                                 void __user *pvBuffer, unsigned uCount,
0330                                 unsigned long ulDSPAddr);
0331 int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
0332                          unsigned uCount, unsigned long ulDSPAddr);
0333 int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
0334                         unsigned uCount, unsigned long ulDSPAddr);
0335 int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
0336                          unsigned uCount, unsigned long ulDSPAddr);
0337 unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO,
0338                                    unsigned long ulMsaAddr);
0339 void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO,
0340                           unsigned long ulMsaAddr, unsigned short usValue);
0341 int dsp3780I_GetIPCSource(unsigned short usDspBaseIO,
0342                           unsigned short *pusIPCSource);
0343
0344 /* I/O port access macros */
0345 #define MKWORD(var) (*((unsigned short *)(&var)))
0346 #define MKBYTE(var) (*((unsigned char *)(&var)))
0347
0348 #define WriteMsaCfg(addr,value) dsp3780I_WriteMsaCfg(usDspBaseIO,addr,value)
0349 #define ReadMsaCfg(addr) dsp3780I_ReadMsaCfg(usDspBaseIO,addr)
0350 #define WriteGenCfg(index,value) dsp3780I_WriteGenCfg(usDspBaseIO,index,value)
0351 #define ReadGenCfg(index) dsp3780I_ReadGenCfg(usDspBaseIO,index)
0352
0353 #define InWordDsp(index)          inw(usDspBaseIO+index)
0354 #define InByteDsp(index)          inb(usDspBaseIO+index)
0355 #define OutWordDsp(index,value)   outw(value,usDspBaseIO+index)
0356 #define OutByteDsp(index,value)   outb(value,usDspBaseIO+index)
0357
0358 #endif