char/mwave/3780i.c

0001 /*
0002 *
0003 * 3780i.c -- helper routines for the 3780i DSP
0004 *
0005 *
0006 * Written By: Mike Sullivan IBM Corporation
0007 *
0008 * Copyright (C) 1999 IBM Corporation
0009 *
0010 * This program is free software; you can redistribute it and/or modify
0011 * it under the terms of the GNU General Public License as published by
0012 * the Free Software Foundation; either version 2 of the License, or
0013 * (at your option) any later version.
0014 *
0015 * This program is distributed in the hope that it will be useful,
0016 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0017 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0018 * GNU General Public License for more details.
0019 *
0020 * NO WARRANTY
0021 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
0022 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
0023 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
0024 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
0025 * solely responsible for determining the appropriateness of using and
0026 * distributing the Program and assumes all risks associated with its
0027 * exercise of rights under this Agreement, including but not limited to
0028 * the risks and costs of program errors, damage to or loss of data,
0029 * programs or equipment, and unavailability or interruption of operations.
0030 *
0031 * DISCLAIMER OF LIABILITY
0032 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
0033 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0034 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
0035 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
0036 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
0037 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
0038 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
0039 *
0040 * You should have received a copy of the GNU General Public License
0041 * along with this program; if not, write to the Free Software
0042 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
0043 *
0044 *
0045 * 10/23/2000 - Alpha Release
0046 *   First release to the public
0047 */
0048
0049 #include <linux/kernel.h>
0050 #include <linux/unistd.h>
0051 #include <linux/delay.h>
0052 #include <linux/ioport.h>
0053 #include <linux/bitops.h>
0054 #include <linux/sched.h>    /* cond_resched() */
0055
0056 #include <asm/io.h>
0057 #include <linux/uaccess.h>
0058 #include <asm/irq.h>
0059 #include "smapi.h"
0060 #include "mwavedd.h"
0061 #include "3780i.h"
0062
0063 static DEFINE_SPINLOCK(dsp_lock);
0064
0065 static void PaceMsaAccess(unsigned short usDspBaseIO)
0066 {
0067     cond_resched();
0068     udelay(100);
0069     cond_resched();
0070 }
0071
0072 unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO,
0073                                    unsigned long ulMsaAddr)
0074 {
0075     unsigned long flags;
0076     unsigned short val;
0077
0078     PRINTK_3(TRACE_3780I,
0079         "3780i::dsp3780I_ReadMsaCfg entry usDspBaseIO %x ulMsaAddr %lx\n",
0080         usDspBaseIO, ulMsaAddr);
0081
0082     spin_lock_irqsave(&dsp_lock, flags);
0083     OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);
0084     OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));
0085     val = InWordDsp(DSP_MsaDataDSISHigh);
0086     spin_unlock_irqrestore(&dsp_lock, flags);
0087
0088     PRINTK_2(TRACE_3780I, "3780i::dsp3780I_ReadMsaCfg exit val %x\n", val);
0089
0090     return val;
0091 }
0092
0093 void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO,
0094                           unsigned long ulMsaAddr, unsigned short usValue)
0095 {
0096     unsigned long flags;
0097
0098     PRINTK_4(TRACE_3780I,
0099         "3780i::dsp3780i_WriteMsaCfg entry usDspBaseIO %x ulMsaAddr %lx usValue %x\n",
0100         usDspBaseIO, ulMsaAddr, usValue);
0101
0102     spin_lock_irqsave(&dsp_lock, flags);
0103     OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);
0104     OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));
0105     OutWordDsp(DSP_MsaDataDSISHigh, usValue);
0106     spin_unlock_irqrestore(&dsp_lock, flags);
0107 }
0108
0109 static void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex,
0110                  unsigned char ucValue)
0111 {
0112     DSP_ISA_SLAVE_CONTROL rSlaveControl;
0113     DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;
0114
0115
0116     PRINTK_4(TRACE_3780I,
0117         "3780i::dsp3780i_WriteGenCfg entry usDspBaseIO %x uIndex %x ucValue %x\n",
0118         usDspBaseIO, uIndex, ucValue);
0119
0120     MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);
0121
0122     PRINTK_2(TRACE_3780I,
0123         "3780i::dsp3780i_WriteGenCfg rSlaveControl %x\n",
0124         MKBYTE(rSlaveControl));
0125
0126     rSlaveControl_Save = rSlaveControl;
0127     rSlaveControl.ConfigMode = true;
0128
0129     PRINTK_2(TRACE_3780I,
0130         "3780i::dsp3780i_WriteGenCfg entry rSlaveControl+ConfigMode %x\n",
0131         MKBYTE(rSlaveControl));
0132
0133     OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));
0134     OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);
0135     OutByteDsp(DSP_ConfigData, ucValue);
0136     OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));
0137
0138     PRINTK_1(TRACE_3780I, "3780i::dsp3780i_WriteGenCfg exit\n");
0139
0140
0141 }
0142
0143 #if 0
0144 unsigned char dsp3780I_ReadGenCfg(unsigned short usDspBaseIO,
0145                                   unsigned uIndex)
0146 {
0147     DSP_ISA_SLAVE_CONTROL rSlaveControl;
0148     DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;
0149     unsigned char ucValue;
0150
0151
0152     PRINTK_3(TRACE_3780I,
0153         "3780i::dsp3780i_ReadGenCfg entry usDspBaseIO %x uIndex %x\n",
0154         usDspBaseIO, uIndex);
0155
0156     MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);
0157     rSlaveControl_Save = rSlaveControl;
0158     rSlaveControl.ConfigMode = true;
0159     OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));
0160     OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);
0161     ucValue = InByteDsp(DSP_ConfigData);
0162     OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));
0163
0164     PRINTK_2(TRACE_3780I,
0165         "3780i::dsp3780i_ReadGenCfg exit ucValue %x\n", ucValue);
0166
0167
0168     return ucValue;
0169 }
0170 #endif  /*  0  */
0171
0172 int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings,
0173                        unsigned short *pIrqMap,
0174                        unsigned short *pDmaMap)
0175 {
0176     unsigned long flags;
0177     unsigned short usDspBaseIO = pSettings->usDspBaseIO;
0178     int i;
0179     DSP_UART_CFG_1 rUartCfg1;
0180     DSP_UART_CFG_2 rUartCfg2;
0181     DSP_HBRIDGE_CFG_1 rHBridgeCfg1;
0182     DSP_HBRIDGE_CFG_2 rHBridgeCfg2;
0183     DSP_BUSMASTER_CFG_1 rBusmasterCfg1;
0184     DSP_BUSMASTER_CFG_2 rBusmasterCfg2;
0185     DSP_ISA_PROT_CFG rIsaProtCfg;
0186     DSP_POWER_MGMT_CFG rPowerMgmtCfg;
0187     DSP_HBUS_TIMER_CFG rHBusTimerCfg;
0188     DSP_LBUS_TIMEOUT_DISABLE rLBusTimeoutDisable;
0189     DSP_CHIP_RESET rChipReset;
0190     DSP_CLOCK_CONTROL_1 rClockControl1;
0191     DSP_CLOCK_CONTROL_2 rClockControl2;
0192     DSP_ISA_SLAVE_CONTROL rSlaveControl;
0193     DSP_HBRIDGE_CONTROL rHBridgeControl;
0194     unsigned short ChipID = 0;
0195     unsigned short tval;
0196
0197
0198     PRINTK_2(TRACE_3780I,
0199         "3780i::dsp3780I_EnableDSP entry pSettings->bDSPEnabled %x\n",
0200         pSettings->bDSPEnabled);
0201
0202
0203     if (!pSettings->bDSPEnabled) {
0204         PRINTK_ERROR( KERN_ERR "3780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting.\n" );
0205         return -EIO;
0206     }
0207
0208
0209     PRINTK_2(TRACE_3780I,
0210         "3780i::dsp3780i_EnableDSP entry pSettings->bModemEnabled %x\n",
0211         pSettings->bModemEnabled);
0212
0213     if (pSettings->bModemEnabled) {
0214         rUartCfg1.Reserved = rUartCfg2.Reserved = 0;
0215         rUartCfg1.IrqActiveLow = pSettings->bUartIrqActiveLow;
0216         rUartCfg1.IrqPulse = pSettings->bUartIrqPulse;
0217         rUartCfg1.Irq =
0218             (unsigned char) pIrqMap[pSettings->usUartIrq];
0219         switch (pSettings->usUartBaseIO) {
0220         case 0x03F8:
0221             rUartCfg1.BaseIO = 0;
0222             break;
0223         case 0x02F8:
0224             rUartCfg1.BaseIO = 1;
0225             break;
0226         case 0x03E8:
0227             rUartCfg1.BaseIO = 2;
0228             break;
0229         case 0x02E8:
0230             rUartCfg1.BaseIO = 3;
0231             break;
0232         }
0233         rUartCfg2.Enable = true;
0234     }
0235
0236     rHBridgeCfg1.Reserved = rHBridgeCfg2.Reserved = 0;
0237     rHBridgeCfg1.IrqActiveLow = pSettings->bDspIrqActiveLow;
0238     rHBridgeCfg1.IrqPulse = pSettings->bDspIrqPulse;
0239     rHBridgeCfg1.Irq = (unsigned char) pIrqMap[pSettings->usDspIrq];
0240     rHBridgeCfg1.AccessMode = 1;
0241     rHBridgeCfg2.Enable = true;
0242
0243
0244     rBusmasterCfg2.Reserved = 0;
0245     rBusmasterCfg1.Dma = (unsigned char) pDmaMap[pSettings->usDspDma];
0246     rBusmasterCfg1.NumTransfers =
0247         (unsigned char) pSettings->usNumTransfers;
0248     rBusmasterCfg1.ReRequest = (unsigned char) pSettings->usReRequest;
0249     rBusmasterCfg1.MEMCS16 = pSettings->bEnableMEMCS16;
0250     rBusmasterCfg2.IsaMemCmdWidth =
0251         (unsigned char) pSettings->usIsaMemCmdWidth;
0252
0253
0254     rIsaProtCfg.Reserved = 0;
0255     rIsaProtCfg.GateIOCHRDY = pSettings->bGateIOCHRDY;
0256
0257     rPowerMgmtCfg.Reserved = 0;
0258     rPowerMgmtCfg.Enable = pSettings->bEnablePwrMgmt;
0259
0260     rHBusTimerCfg.LoadValue =
0261         (unsigned char) pSettings->usHBusTimerLoadValue;
0262
0263     rLBusTimeoutDisable.Reserved = 0;
0264     rLBusTimeoutDisable.DisableTimeout =
0265         pSettings->bDisableLBusTimeout;
0266
0267     MKWORD(rChipReset) = ~pSettings->usChipletEnable;
0268
0269     rClockControl1.Reserved1 = rClockControl1.Reserved2 = 0;
0270     rClockControl1.N_Divisor = pSettings->usN_Divisor;
0271     rClockControl1.M_Multiplier = pSettings->usM_Multiplier;
0272
0273     rClockControl2.Reserved = 0;
0274     rClockControl2.PllBypass = pSettings->bPllBypass;
0275
0276     /* Issue a soft reset to the chip */
0277     /* Note: Since we may be coming in with 3780i clocks suspended, we must keep
0278     * soft-reset active for 10ms.
0279     */
0280     rSlaveControl.ClockControl = 0;
0281     rSlaveControl.SoftReset = true;
0282     rSlaveControl.ConfigMode = false;
0283     rSlaveControl.Reserved = 0;
0284
0285     PRINTK_4(TRACE_3780I,
0286         "3780i::dsp3780i_EnableDSP usDspBaseIO %x index %x taddr %x\n",
0287         usDspBaseIO, DSP_IsaSlaveControl,
0288         usDspBaseIO + DSP_IsaSlaveControl);
0289
0290     PRINTK_2(TRACE_3780I,
0291         "3780i::dsp3780i_EnableDSP rSlaveContrl %x\n",
0292         MKWORD(rSlaveControl));
0293
0294     spin_lock_irqsave(&dsp_lock, flags);
0295     OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
0296     MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);
0297
0298     PRINTK_2(TRACE_3780I,
0299         "3780i::dsp3780i_EnableDSP rSlaveControl 2 %x\n", tval);
0300
0301
0302     for (i = 0; i < 11; i++)
0303         udelay(2000);
0304
0305     rSlaveControl.SoftReset = false;
0306     OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
0307
0308     MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);
0309
0310     PRINTK_2(TRACE_3780I,
0311         "3780i::dsp3780i_EnableDSP rSlaveControl 3 %x\n", tval);
0312
0313
0314     /* Program our general configuration registers */
0315     WriteGenCfg(DSP_HBridgeCfg1Index, MKBYTE(rHBridgeCfg1));
0316     WriteGenCfg(DSP_HBridgeCfg2Index, MKBYTE(rHBridgeCfg2));
0317     WriteGenCfg(DSP_BusMasterCfg1Index, MKBYTE(rBusmasterCfg1));
0318     WriteGenCfg(DSP_BusMasterCfg2Index, MKBYTE(rBusmasterCfg2));
0319     WriteGenCfg(DSP_IsaProtCfgIndex, MKBYTE(rIsaProtCfg));
0320     WriteGenCfg(DSP_PowerMgCfgIndex, MKBYTE(rPowerMgmtCfg));
0321     WriteGenCfg(DSP_HBusTimerCfgIndex, MKBYTE(rHBusTimerCfg));
0322
0323     if (pSettings->bModemEnabled) {
0324         WriteGenCfg(DSP_UartCfg1Index, MKBYTE(rUartCfg1));
0325         WriteGenCfg(DSP_UartCfg2Index, MKBYTE(rUartCfg2));
0326     }
0327
0328
0329     rHBridgeControl.EnableDspInt = false;
0330     rHBridgeControl.MemAutoInc = true;
0331     rHBridgeControl.IoAutoInc = false;
0332     rHBridgeControl.DiagnosticMode = false;
0333
0334     PRINTK_3(TRACE_3780I,
0335         "3780i::dsp3780i_EnableDSP DSP_HBridgeControl %x rHBridgeControl %x\n",
0336         DSP_HBridgeControl, MKWORD(rHBridgeControl));
0337
0338     OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
0339     spin_unlock_irqrestore(&dsp_lock, flags);
0340     WriteMsaCfg(DSP_LBusTimeoutDisable, MKWORD(rLBusTimeoutDisable));
0341     WriteMsaCfg(DSP_ClockControl_1, MKWORD(rClockControl1));
0342     WriteMsaCfg(DSP_ClockControl_2, MKWORD(rClockControl2));
0343     WriteMsaCfg(DSP_ChipReset, MKWORD(rChipReset));
0344
0345     ChipID = ReadMsaCfg(DSP_ChipID);
0346
0347     PRINTK_2(TRACE_3780I,
0348         "3780i::dsp3780I_EnableDSP exiting bRC=true, ChipID %x\n",
0349         ChipID);
0350
0351     return 0;
0352 }
0353
0354 int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings)
0355 {
0356     unsigned long flags;
0357     unsigned short usDspBaseIO = pSettings->usDspBaseIO;
0358     DSP_ISA_SLAVE_CONTROL rSlaveControl;
0359
0360
0361     PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP entry\n");
0362
0363     rSlaveControl.ClockControl = 0;
0364     rSlaveControl.SoftReset = true;
0365     rSlaveControl.ConfigMode = false;
0366     rSlaveControl.Reserved = 0;
0367     spin_lock_irqsave(&dsp_lock, flags);
0368     OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
0369
0370     udelay(5);
0371
0372     rSlaveControl.ClockControl = 1;
0373     OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
0374     spin_unlock_irqrestore(&dsp_lock, flags);
0375
0376     udelay(5);
0377
0378
0379     PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP exit\n");
0380
0381     return 0;
0382 }
0383
0384 int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings)
0385 {
0386     unsigned long flags;
0387     unsigned short usDspBaseIO = pSettings->usDspBaseIO;
0388     DSP_BOOT_DOMAIN rBootDomain;
0389     DSP_HBRIDGE_CONTROL rHBridgeControl;
0390
0391
0392     PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset entry\n");
0393
0394     spin_lock_irqsave(&dsp_lock, flags);
0395     /* Mask DSP to PC interrupt */
0396     MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
0397
0398     PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rHBridgeControl %x\n",
0399         MKWORD(rHBridgeControl));
0400
0401     rHBridgeControl.EnableDspInt = false;
0402     OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
0403     spin_unlock_irqrestore(&dsp_lock, flags);
0404
0405     /* Reset the core via the boot domain register */
0406     rBootDomain.ResetCore = true;
0407     rBootDomain.Halt = true;
0408     rBootDomain.NMI = true;
0409     rBootDomain.Reserved = 0;
0410
0411     PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rBootDomain %x\n",
0412         MKWORD(rBootDomain));
0413
0414     WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
0415
0416     /* Reset all the chiplets and then reactivate them */
0417     WriteMsaCfg(DSP_ChipReset, 0xFFFF);
0418     udelay(5);
0419     WriteMsaCfg(DSP_ChipReset,
0420             (unsigned short) (~pSettings->usChipletEnable));
0421
0422
0423     PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset exit bRC=0\n");
0424
0425     return 0;
0426 }
0427
0428
0429 int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings)
0430 {
0431     unsigned long flags;
0432     unsigned short usDspBaseIO = pSettings->usDspBaseIO;
0433     DSP_BOOT_DOMAIN rBootDomain;
0434     DSP_HBRIDGE_CONTROL rHBridgeControl;
0435
0436
0437     PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run entry\n");
0438
0439
0440     /* Transition the core to a running state */
0441     rBootDomain.ResetCore = true;
0442     rBootDomain.Halt = false;
0443     rBootDomain.NMI = true;
0444     rBootDomain.Reserved = 0;
0445     WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
0446
0447     udelay(5);
0448
0449     rBootDomain.ResetCore = false;
0450     WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
0451     udelay(5);
0452
0453     rBootDomain.NMI = false;
0454     WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
0455     udelay(5);
0456
0457     /* Enable DSP to PC interrupt */
0458     spin_lock_irqsave(&dsp_lock, flags);
0459     MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
0460     rHBridgeControl.EnableDspInt = true;
0461
0462     PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Run rHBridgeControl %x\n",
0463         MKWORD(rHBridgeControl));
0464
0465     OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
0466     spin_unlock_irqrestore(&dsp_lock, flags);
0467
0468
0469     PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run exit bRC=true\n");
0470
0471     return 0;
0472 }
0473
0474
0475 int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
0476                         unsigned uCount, unsigned long ulDSPAddr)
0477 {
0478     unsigned long flags;
0479     unsigned short __user *pusBuffer = pvBuffer;
0480     unsigned short val;
0481
0482
0483     PRINTK_5(TRACE_3780I,
0484         "3780i::dsp3780I_ReadDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
0485         usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
0486
0487
0488     /* Set the initial MSA address. No adjustments need to be made to data store addresses */
0489     spin_lock_irqsave(&dsp_lock, flags);
0490     OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
0491     OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
0492     spin_unlock_irqrestore(&dsp_lock, flags);
0493
0494     /* Transfer the memory block */
0495     while (uCount-- != 0) {
0496         spin_lock_irqsave(&dsp_lock, flags);
0497         val = InWordDsp(DSP_MsaDataDSISHigh);
0498         spin_unlock_irqrestore(&dsp_lock, flags);
0499         if(put_user(val, pusBuffer++))
0500             return -EFAULT;
0501
0502         PRINTK_3(TRACE_3780I,
0503             "3780I::dsp3780I_ReadDStore uCount %x val %x\n",
0504             uCount, val);
0505
0506         PaceMsaAccess(usDspBaseIO);
0507     }
0508
0509
0510     PRINTK_1(TRACE_3780I,
0511         "3780I::dsp3780I_ReadDStore exit bRC=true\n");
0512
0513     return 0;
0514 }
0515
0516 int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO,
0517                                 void __user *pvBuffer, unsigned uCount,
0518                                 unsigned long ulDSPAddr)
0519 {
0520     unsigned long flags;
0521     unsigned short __user *pusBuffer = pvBuffer;
0522     unsigned short val;
0523
0524
0525     PRINTK_5(TRACE_3780I,
0526         "3780i::dsp3780I_ReadAndDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
0527         usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
0528
0529
0530     /* Set the initial MSA address. No adjustments need to be made to data store addresses */
0531     spin_lock_irqsave(&dsp_lock, flags);
0532     OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
0533     OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
0534     spin_unlock_irqrestore(&dsp_lock, flags);
0535
0536     /* Transfer the memory block */
0537     while (uCount-- != 0) {
0538         spin_lock_irqsave(&dsp_lock, flags);
0539         val = InWordDsp(DSP_ReadAndClear);
0540         spin_unlock_irqrestore(&dsp_lock, flags);
0541         if(put_user(val, pusBuffer++))
0542             return -EFAULT;
0543
0544         PRINTK_3(TRACE_3780I,
0545             "3780I::dsp3780I_ReadAndCleanDStore uCount %x val %x\n",
0546             uCount, val);
0547
0548         PaceMsaAccess(usDspBaseIO);
0549     }
0550
0551
0552     PRINTK_1(TRACE_3780I,
0553         "3780I::dsp3780I_ReadAndClearDStore exit bRC=true\n");
0554
0555     return 0;
0556 }
0557
0558
0559 int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
0560                          unsigned uCount, unsigned long ulDSPAddr)
0561 {
0562     unsigned long flags;
0563     unsigned short __user *pusBuffer = pvBuffer;
0564
0565
0566     PRINTK_5(TRACE_3780I,
0567         "3780i::dsp3780D_WriteDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
0568         usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
0569
0570
0571     /* Set the initial MSA address. No adjustments need to be made to data store addresses */
0572     spin_lock_irqsave(&dsp_lock, flags);
0573     OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
0574     OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
0575     spin_unlock_irqrestore(&dsp_lock, flags);
0576
0577     /* Transfer the memory block */
0578     while (uCount-- != 0) {
0579         unsigned short val;
0580         if(get_user(val, pusBuffer++))
0581             return -EFAULT;
0582         spin_lock_irqsave(&dsp_lock, flags);
0583         OutWordDsp(DSP_MsaDataDSISHigh, val);
0584         spin_unlock_irqrestore(&dsp_lock, flags);
0585
0586         PRINTK_3(TRACE_3780I,
0587             "3780I::dsp3780I_WriteDStore uCount %x val %x\n",
0588             uCount, val);
0589
0590         PaceMsaAccess(usDspBaseIO);
0591     }
0592
0593
0594     PRINTK_1(TRACE_3780I,
0595         "3780I::dsp3780D_WriteDStore exit bRC=true\n");
0596
0597     return 0;
0598 }
0599
0600
0601 int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
0602                         unsigned uCount, unsigned long ulDSPAddr)
0603 {
0604     unsigned long flags;
0605     unsigned short __user *pusBuffer = pvBuffer;
0606
0607     PRINTK_5(TRACE_3780I,
0608         "3780i::dsp3780I_ReadIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
0609         usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
0610
0611     /*
0612     * Set the initial MSA address. To convert from an instruction store
0613     * address to an MSA address
0614     * shift the address two bits to the left and set bit 22
0615     */
0616     ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);
0617     spin_lock_irqsave(&dsp_lock, flags);
0618     OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
0619     OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
0620     spin_unlock_irqrestore(&dsp_lock, flags);
0621
0622     /* Transfer the memory block */
0623     while (uCount-- != 0) {
0624         unsigned short val_lo, val_hi;
0625         spin_lock_irqsave(&dsp_lock, flags);
0626         val_lo = InWordDsp(DSP_MsaDataISLow);
0627         val_hi = InWordDsp(DSP_MsaDataDSISHigh);
0628         spin_unlock_irqrestore(&dsp_lock, flags);
0629         if(put_user(val_lo, pusBuffer++))
0630             return -EFAULT;
0631         if(put_user(val_hi, pusBuffer++))
0632             return -EFAULT;
0633
0634         PRINTK_4(TRACE_3780I,
0635             "3780I::dsp3780I_ReadIStore uCount %x val_lo %x val_hi %x\n",
0636             uCount, val_lo, val_hi);
0637
0638         PaceMsaAccess(usDspBaseIO);
0639
0640     }
0641
0642     PRINTK_1(TRACE_3780I,
0643         "3780I::dsp3780I_ReadIStore exit bRC=true\n");
0644
0645     return 0;
0646 }
0647
0648
0649 int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
0650                          unsigned uCount, unsigned long ulDSPAddr)
0651 {
0652     unsigned long flags;
0653     unsigned short __user *pusBuffer = pvBuffer;
0654
0655     PRINTK_5(TRACE_3780I,
0656         "3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
0657         usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
0658
0659
0660     /*
0661     * Set the initial MSA address. To convert from an instruction store
0662     * address to an MSA address
0663     * shift the address two bits to the left and set bit 22
0664     */
0665     ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);
0666     spin_lock_irqsave(&dsp_lock, flags);
0667     OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
0668     OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
0669     spin_unlock_irqrestore(&dsp_lock, flags);
0670
0671     /* Transfer the memory block */
0672     while (uCount-- != 0) {
0673         unsigned short val_lo, val_hi;
0674         if(get_user(val_lo, pusBuffer++))
0675             return -EFAULT;
0676         if(get_user(val_hi, pusBuffer++))
0677             return -EFAULT;
0678         spin_lock_irqsave(&dsp_lock, flags);
0679         OutWordDsp(DSP_MsaDataISLow, val_lo);
0680         OutWordDsp(DSP_MsaDataDSISHigh, val_hi);
0681         spin_unlock_irqrestore(&dsp_lock, flags);
0682
0683         PRINTK_4(TRACE_3780I,
0684             "3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x\n",
0685             uCount, val_lo, val_hi);
0686
0687         PaceMsaAccess(usDspBaseIO);
0688
0689     }
0690
0691     PRINTK_1(TRACE_3780I,
0692         "3780I::dsp3780I_WriteIStore exit bRC=true\n");
0693
0694     return 0;
0695 }
0696
0697
0698 int dsp3780I_GetIPCSource(unsigned short usDspBaseIO,
0699                           unsigned short *pusIPCSource)
0700 {
0701     unsigned long flags;
0702     DSP_HBRIDGE_CONTROL rHBridgeControl;
0703     unsigned short temp;
0704
0705
0706     PRINTK_3(TRACE_3780I,
0707         "3780i::dsp3780I_GetIPCSource entry usDspBaseIO %x pusIPCSource %p\n",
0708         usDspBaseIO, pusIPCSource);
0709
0710     /*
0711     * Disable DSP to PC interrupts, read the interrupt register,
0712     * clear the pending IPC bits, and reenable DSP to PC interrupts
0713     */
0714     spin_lock_irqsave(&dsp_lock, flags);
0715     MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
0716     rHBridgeControl.EnableDspInt = false;
0717     OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
0718
0719     *pusIPCSource = InWordDsp(DSP_Interrupt);
0720     temp = (unsigned short) ~(*pusIPCSource);
0721
0722     PRINTK_3(TRACE_3780I,
0723         "3780i::dsp3780I_GetIPCSource, usIPCSource %x ~ %x\n",
0724         *pusIPCSource, temp);
0725
0726     OutWordDsp(DSP_Interrupt, (unsigned short) ~(*pusIPCSource));
0727
0728     rHBridgeControl.EnableDspInt = true;
0729     OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
0730     spin_unlock_irqrestore(&dsp_lock, flags);
0731
0732
0733     PRINTK_2(TRACE_3780I,
0734         "3780i::dsp3780I_GetIPCSource exit usIPCSource %x\n",
0735         *pusIPCSource);
0736
0737     return 0;
0738 }