char/hw_random/xgene-rng.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * APM X-Gene SoC RNG Driver
0004  *
0005  * Copyright (c) 2014, Applied Micro Circuits Corporation
0006  * Author: Rameshwar Prasad Sahu <rsahu@apm.com>
0007  *     Shamal Winchurkar <swinchurkar@apm.com>
0008  *     Feng Kan <fkan@apm.com>
0009  */
0010
0011 #include <linux/acpi.h>
0012 #include <linux/clk.h>
0013 #include <linux/delay.h>
0014 #include <linux/hw_random.h>
0015 #include <linux/init.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/module.h>
0018 #include <linux/of_platform.h>
0019 #include <linux/of_irq.h>
0020 #include <linux/of_address.h>
0021 #include <linux/timer.h>
0022
0023 #define RNG_MAX_DATUM           4
0024 #define MAX_TRY             100
0025 #define XGENE_RNG_RETRY_COUNT       20
0026 #define XGENE_RNG_RETRY_INTERVAL    10
0027
0028 /* RNG  Registers */
0029 #define RNG_INOUT_0         0x00
0030 #define RNG_INTR_STS_ACK        0x10
0031 #define RNG_CONTROL         0x14
0032 #define RNG_CONFIG          0x18
0033 #define RNG_ALARMCNT            0x1c
0034 #define RNG_FROENABLE           0x20
0035 #define RNG_FRODETUNE           0x24
0036 #define RNG_ALARMMASK           0x28
0037 #define RNG_ALARMSTOP           0x2c
0038 #define RNG_OPTIONS         0x78
0039 #define RNG_EIP_REV         0x7c
0040
0041 #define MONOBIT_FAIL_MASK       BIT(7)
0042 #define POKER_FAIL_MASK         BIT(6)
0043 #define LONG_RUN_FAIL_MASK      BIT(5)
0044 #define RUN_FAIL_MASK           BIT(4)
0045 #define NOISE_FAIL_MASK         BIT(3)
0046 #define STUCK_OUT_MASK          BIT(2)
0047 #define SHUTDOWN_OFLO_MASK      BIT(1)
0048 #define READY_MASK          BIT(0)
0049
0050 #define MAJOR_HW_REV_RD(src)        (((src) & 0x0f000000) >> 24)
0051 #define MINOR_HW_REV_RD(src)        (((src) & 0x00f00000) >> 20)
0052 #define HW_PATCH_LEVEL_RD(src)      (((src) & 0x000f0000) >> 16)
0053 #define MAX_REFILL_CYCLES_SET(dst, src) \
0054             ((dst & ~0xffff0000) | (((u32)src << 16) & 0xffff0000))
0055 #define MIN_REFILL_CYCLES_SET(dst, src) \
0056             ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
0057 #define ALARM_THRESHOLD_SET(dst, src) \
0058             ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
0059 #define ENABLE_RNG_SET(dst, src) \
0060             ((dst & ~BIT(10)) | (((u32)src << 10) & BIT(10)))
0061 #define REGSPEC_TEST_MODE_SET(dst, src) \
0062             ((dst & ~BIT(8)) | (((u32)src << 8) & BIT(8)))
0063 #define MONOBIT_FAIL_MASK_SET(dst, src) \
0064             ((dst & ~BIT(7)) | (((u32)src << 7) & BIT(7)))
0065 #define POKER_FAIL_MASK_SET(dst, src) \
0066             ((dst & ~BIT(6)) | (((u32)src << 6) & BIT(6)))
0067 #define LONG_RUN_FAIL_MASK_SET(dst, src) \
0068             ((dst & ~BIT(5)) | (((u32)src << 5) & BIT(5)))
0069 #define RUN_FAIL_MASK_SET(dst, src) \
0070             ((dst & ~BIT(4)) | (((u32)src << 4) & BIT(4)))
0071 #define NOISE_FAIL_MASK_SET(dst, src) \
0072             ((dst & ~BIT(3)) | (((u32)src << 3) & BIT(3)))
0073 #define STUCK_OUT_MASK_SET(dst, src) \
0074             ((dst & ~BIT(2)) | (((u32)src << 2) & BIT(2)))
0075 #define SHUTDOWN_OFLO_MASK_SET(dst, src) \
0076             ((dst & ~BIT(1)) | (((u32)src << 1) & BIT(1)))
0077
0078 struct xgene_rng_dev {
0079     u32 irq;
0080     void  __iomem *csr_base;
0081     u32 revision;
0082     u32 datum_size;
0083     u32 failure_cnt;    /* Failure count last minute */
0084     unsigned long failure_ts;/* First failure timestamp */
0085     struct timer_list failure_timer;
0086     struct device *dev;
0087     struct clk *clk;
0088 };
0089
0090 static void xgene_rng_expired_timer(struct timer_list *t)
0091 {
0092     struct xgene_rng_dev *ctx = from_timer(ctx, t, failure_timer);
0093
0094     /* Clear failure counter as timer expired */
0095     disable_irq(ctx->irq);
0096     ctx->failure_cnt = 0;
0097     del_timer(&ctx->failure_timer);
0098     enable_irq(ctx->irq);
0099 }
0100
0101 static void xgene_rng_start_timer(struct xgene_rng_dev *ctx)
0102 {
0103     ctx->failure_timer.expires = jiffies + 120 * HZ;
0104     add_timer(&ctx->failure_timer);
0105 }
0106
0107 /*
0108  * Initialize or reinit free running oscillators (FROs)
0109  */
0110 static void xgene_rng_init_fro(struct xgene_rng_dev *ctx, u32 fro_val)
0111 {
0112     writel(fro_val, ctx->csr_base + RNG_FRODETUNE);
0113     writel(0x00000000, ctx->csr_base + RNG_ALARMMASK);
0114     writel(0x00000000, ctx->csr_base + RNG_ALARMSTOP);
0115     writel(0xFFFFFFFF, ctx->csr_base + RNG_FROENABLE);
0116 }
0117
0118 static void xgene_rng_chk_overflow(struct xgene_rng_dev *ctx)
0119 {
0120     u32 val;
0121
0122     val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
0123     if (val & MONOBIT_FAIL_MASK)
0124         /*
0125          * LFSR detected an out-of-bounds number of 1s after
0126          * checking 20,000 bits (test T1 as specified in the
0127          * AIS-31 standard)
0128          */
0129         dev_err(ctx->dev, "test monobit failure error 0x%08X\n", val);
0130     if (val & POKER_FAIL_MASK)
0131         /*
0132          * LFSR detected an out-of-bounds value in at least one
0133          * of the 16 poker_count_X counters or an out of bounds sum
0134          * of squares value after checking 20,000 bits (test T2 as
0135          * specified in the AIS-31 standard)
0136          */
0137         dev_err(ctx->dev, "test poker failure error 0x%08X\n", val);
0138     if (val & LONG_RUN_FAIL_MASK)
0139         /*
0140          * LFSR detected a sequence of 34 identical bits
0141          * (test T4 as specified in the AIS-31 standard)
0142          */
0143         dev_err(ctx->dev, "test long run failure error 0x%08X\n", val);
0144     if (val & RUN_FAIL_MASK)
0145         /*
0146          * LFSR detected an outof-bounds value for at least one
0147          * of the running counters after checking 20,000 bits
0148          * (test T3 as specified in the AIS-31 standard)
0149          */
0150         dev_err(ctx->dev, "test run failure error 0x%08X\n", val);
0151     if (val & NOISE_FAIL_MASK)
0152         /* LFSR detected a sequence of 48 identical bits */
0153         dev_err(ctx->dev, "noise failure error 0x%08X\n", val);
0154     if (val & STUCK_OUT_MASK)
0155         /*
0156          * Detected output data registers generated same value twice
0157          * in a row
0158          */
0159         dev_err(ctx->dev, "stuck out failure error 0x%08X\n", val);
0160
0161     if (val & SHUTDOWN_OFLO_MASK) {
0162         u32 frostopped;
0163
0164         /* FROs shut down after a second error event. Try recover. */
0165         if (++ctx->failure_cnt == 1) {
0166             /* 1st time, just recover */
0167             ctx->failure_ts = jiffies;
0168             frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
0169             xgene_rng_init_fro(ctx, frostopped);
0170
0171             /*
0172              * We must start a timer to clear out this error
0173              * in case the system timer wrap around
0174              */
0175             xgene_rng_start_timer(ctx);
0176         } else {
0177             /* 2nd time failure in lesser than 1 minute? */
0178             if (time_after(ctx->failure_ts + 60 * HZ, jiffies)) {
0179                 dev_err(ctx->dev,
0180                     "FRO shutdown failure error 0x%08X\n",
0181                     val);
0182             } else {
0183                 /* 2nd time failure after 1 minutes, recover */
0184                 ctx->failure_ts = jiffies;
0185                 ctx->failure_cnt = 1;
0186                 /*
0187                  * We must start a timer to clear out this
0188                  * error in case the system timer wrap
0189                  * around
0190                  */
0191                 xgene_rng_start_timer(ctx);
0192             }
0193             frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
0194             xgene_rng_init_fro(ctx, frostopped);
0195         }
0196     }
0197     /* Clear them all */
0198     writel(val, ctx->csr_base + RNG_INTR_STS_ACK);
0199 }
0200
0201 static irqreturn_t xgene_rng_irq_handler(int irq, void *id)
0202 {
0203     struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) id;
0204
0205     /* RNG Alarm Counter overflow */
0206     xgene_rng_chk_overflow(ctx);
0207
0208     return IRQ_HANDLED;
0209 }
0210
0211 static int xgene_rng_data_present(struct hwrng *rng, int wait)
0212 {
0213     struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
0214     u32 i, val = 0;
0215
0216     for (i = 0; i < XGENE_RNG_RETRY_COUNT; i++) {
0217         val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
0218         if ((val & READY_MASK) || !wait)
0219             break;
0220         udelay(XGENE_RNG_RETRY_INTERVAL);
0221     }
0222
0223     return (val & READY_MASK);
0224 }
0225
0226 static int xgene_rng_data_read(struct hwrng *rng, u32 *data)
0227 {
0228     struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
0229     int i;
0230
0231     for (i = 0; i < ctx->datum_size; i++)
0232         data[i] = readl(ctx->csr_base + RNG_INOUT_0 + i * 4);
0233
0234     /* Clear ready bit to start next transaction */
0235     writel(READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
0236
0237     return ctx->datum_size << 2;
0238 }
0239
0240 static void xgene_rng_init_internal(struct xgene_rng_dev *ctx)
0241 {
0242     u32 val;
0243
0244     writel(0x00000000, ctx->csr_base + RNG_CONTROL);
0245
0246     val = MAX_REFILL_CYCLES_SET(0, 10);
0247     val = MIN_REFILL_CYCLES_SET(val, 10);
0248     writel(val, ctx->csr_base + RNG_CONFIG);
0249
0250     val = ALARM_THRESHOLD_SET(0, 0xFF);
0251     writel(val, ctx->csr_base + RNG_ALARMCNT);
0252
0253     xgene_rng_init_fro(ctx, 0);
0254
0255     writel(MONOBIT_FAIL_MASK |
0256         POKER_FAIL_MASK |
0257         LONG_RUN_FAIL_MASK |
0258         RUN_FAIL_MASK |
0259         NOISE_FAIL_MASK |
0260         STUCK_OUT_MASK |
0261         SHUTDOWN_OFLO_MASK |
0262         READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
0263
0264     val = ENABLE_RNG_SET(0, 1);
0265     val = MONOBIT_FAIL_MASK_SET(val, 1);
0266     val = POKER_FAIL_MASK_SET(val, 1);
0267     val = LONG_RUN_FAIL_MASK_SET(val, 1);
0268     val = RUN_FAIL_MASK_SET(val, 1);
0269     val = NOISE_FAIL_MASK_SET(val, 1);
0270     val = STUCK_OUT_MASK_SET(val, 1);
0271     val = SHUTDOWN_OFLO_MASK_SET(val, 1);
0272     writel(val, ctx->csr_base + RNG_CONTROL);
0273 }
0274
0275 static int xgene_rng_init(struct hwrng *rng)
0276 {
0277     struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
0278
0279     ctx->failure_cnt = 0;
0280     timer_setup(&ctx->failure_timer, xgene_rng_expired_timer, 0);
0281
0282     ctx->revision = readl(ctx->csr_base + RNG_EIP_REV);
0283
0284     dev_dbg(ctx->dev, "Rev %d.%d.%d\n",
0285         MAJOR_HW_REV_RD(ctx->revision),
0286         MINOR_HW_REV_RD(ctx->revision),
0287         HW_PATCH_LEVEL_RD(ctx->revision));
0288
0289     dev_dbg(ctx->dev, "Options 0x%08X",
0290         readl(ctx->csr_base + RNG_OPTIONS));
0291
0292     xgene_rng_init_internal(ctx);
0293
0294     ctx->datum_size = RNG_MAX_DATUM;
0295
0296     return 0;
0297 }
0298
0299 #ifdef CONFIG_ACPI
0300 static const struct acpi_device_id xgene_rng_acpi_match[] = {
0301     { "APMC0D18", },
0302     { }
0303 };
0304 MODULE_DEVICE_TABLE(acpi, xgene_rng_acpi_match);
0305 #endif
0306
0307 static struct hwrng xgene_rng_func = {
0308     .name       = "xgene-rng",
0309     .init       = xgene_rng_init,
0310     .data_present   = xgene_rng_data_present,
0311     .data_read  = xgene_rng_data_read,
0312 };
0313
0314 static int xgene_rng_probe(struct platform_device *pdev)
0315 {
0316     struct xgene_rng_dev *ctx;
0317     int rc = 0;
0318
0319     ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
0320     if (!ctx)
0321         return -ENOMEM;
0322
0323     ctx->dev = &pdev->dev;
0324     platform_set_drvdata(pdev, ctx);
0325
0326     ctx->csr_base = devm_platform_ioremap_resource(pdev, 0);
0327     if (IS_ERR(ctx->csr_base))
0328         return PTR_ERR(ctx->csr_base);
0329
0330     rc = platform_get_irq(pdev, 0);
0331     if (rc < 0)
0332         return rc;
0333     ctx->irq = rc;
0334
0335     dev_dbg(&pdev->dev, "APM X-Gene RNG BASE %p ALARM IRQ %d",
0336         ctx->csr_base, ctx->irq);
0337
0338     rc = devm_request_irq(&pdev->dev, ctx->irq, xgene_rng_irq_handler, 0,
0339                 dev_name(&pdev->dev), ctx);
0340     if (rc) {
0341         dev_err(&pdev->dev, "Could not request RNG alarm IRQ\n");
0342         return rc;
0343     }
0344
0345     /* Enable IP clock */
0346     ctx->clk = devm_clk_get(&pdev->dev, NULL);
0347     if (IS_ERR(ctx->clk)) {
0348         dev_warn(&pdev->dev, "Couldn't get the clock for RNG\n");
0349     } else {
0350         rc = clk_prepare_enable(ctx->clk);
0351         if (rc) {
0352             dev_warn(&pdev->dev,
0353                  "clock prepare enable failed for RNG");
0354             return rc;
0355         }
0356     }
0357
0358     xgene_rng_func.priv = (unsigned long) ctx;
0359
0360     rc = devm_hwrng_register(&pdev->dev, &xgene_rng_func);
0361     if (rc) {
0362         dev_err(&pdev->dev, "RNG registering failed error %d\n", rc);
0363         if (!IS_ERR(ctx->clk))
0364             clk_disable_unprepare(ctx->clk);
0365         return rc;
0366     }
0367
0368     rc = device_init_wakeup(&pdev->dev, 1);
0369     if (rc) {
0370         dev_err(&pdev->dev, "RNG device_init_wakeup failed error %d\n",
0371             rc);
0372         if (!IS_ERR(ctx->clk))
0373             clk_disable_unprepare(ctx->clk);
0374         return rc;
0375     }
0376
0377     return 0;
0378 }
0379
0380 static int xgene_rng_remove(struct platform_device *pdev)
0381 {
0382     struct xgene_rng_dev *ctx = platform_get_drvdata(pdev);
0383     int rc;
0384
0385     rc = device_init_wakeup(&pdev->dev, 0);
0386     if (rc)
0387         dev_err(&pdev->dev, "RNG init wakeup failed error %d\n", rc);
0388     if (!IS_ERR(ctx->clk))
0389         clk_disable_unprepare(ctx->clk);
0390
0391     return rc;
0392 }
0393
0394 static const struct of_device_id xgene_rng_of_match[] = {
0395     { .compatible = "apm,xgene-rng" },
0396     { }
0397 };
0398
0399 MODULE_DEVICE_TABLE(of, xgene_rng_of_match);
0400
0401 static struct platform_driver xgene_rng_driver = {
0402     .probe = xgene_rng_probe,
0403     .remove = xgene_rng_remove,
0404     .driver = {
0405         .name       = "xgene-rng",
0406         .of_match_table = xgene_rng_of_match,
0407         .acpi_match_table = ACPI_PTR(xgene_rng_acpi_match),
0408     },
0409 };
0410
0411 module_platform_driver(xgene_rng_driver);
0412 MODULE_DESCRIPTION("APM X-Gene RNG driver");
0413 MODULE_LICENSE("GPL");