char/hw_random/via-rng.c

0001 /*
0002  * RNG driver for VIA RNGs
0003  *
0004  * Copyright 2005 (c) MontaVista Software, Inc.
0005  *
0006  * with the majority of the code coming from:
0007  *
0008  * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
0009  * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
0010  *
0011  * derived from
0012  *
0013  * Hardware driver for the AMD 768 Random Number Generator (RNG)
0014  * (c) Copyright 2001 Red Hat Inc
0015  *
0016  * derived from
0017  *
0018  * Hardware driver for Intel i810 Random Number Generator (RNG)
0019  * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
0020  * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
0021  *
0022  * This file is licensed under  the terms of the GNU General Public
0023  * License version 2. This program is licensed "as is" without any
0024  * warranty of any kind, whether express or implied.
0025  */
0026
0027 #include <crypto/padlock.h>
0028 #include <linux/module.h>
0029 #include <linux/kernel.h>
0030 #include <linux/hw_random.h>
0031 #include <linux/delay.h>
0032 #include <asm/cpu_device_id.h>
0033 #include <asm/io.h>
0034 #include <asm/msr.h>
0035 #include <asm/cpufeature.h>
0036 #include <asm/fpu/api.h>
0037
0038
0039
0040
0041 enum {
0042     VIA_STRFILT_CNT_SHIFT   = 16,
0043     VIA_STRFILT_FAIL    = (1 << 15),
0044     VIA_STRFILT_ENABLE  = (1 << 14),
0045     VIA_RAWBITS_ENABLE  = (1 << 13),
0046     VIA_RNG_ENABLE      = (1 << 6),
0047     VIA_NOISESRC1       = (1 << 8),
0048     VIA_NOISESRC2       = (1 << 9),
0049     VIA_XSTORE_CNT_MASK = 0x0F,
0050
0051     VIA_RNG_CHUNK_8     = 0x00, /* 64 rand bits, 64 stored bits */
0052     VIA_RNG_CHUNK_4     = 0x01, /* 32 rand bits, 32 stored bits */
0053     VIA_RNG_CHUNK_4_MASK    = 0xFFFFFFFF,
0054     VIA_RNG_CHUNK_2     = 0x02, /* 16 rand bits, 32 stored bits */
0055     VIA_RNG_CHUNK_2_MASK    = 0xFFFF,
0056     VIA_RNG_CHUNK_1     = 0x03, /* 8 rand bits, 32 stored bits */
0057     VIA_RNG_CHUNK_1_MASK    = 0xFF,
0058 };
0059
0060 /*
0061  * Investigate using the 'rep' prefix to obtain 32 bits of random data
0062  * in one insn.  The upside is potentially better performance.  The
0063  * downside is that the instruction becomes no longer atomic.  Due to
0064  * this, just like familiar issues with /dev/random itself, the worst
0065  * case of a 'rep xstore' could potentially pause a cpu for an
0066  * unreasonably long time.  In practice, this condition would likely
0067  * only occur when the hardware is failing.  (or so we hope :))
0068  *
0069  * Another possible performance boost may come from simply buffering
0070  * until we have 4 bytes, thus returning a u32 at a time,
0071  * instead of the current u8-at-a-time.
0072  *
0073  * Padlock instructions can generate a spurious DNA fault, but the
0074  * kernel doesn't use CR0.TS, so this doesn't matter.
0075  */
0076
0077 static inline u32 xstore(u32 *addr, u32 edx_in)
0078 {
0079     u32 eax_out;
0080
0081     asm(".byte 0x0F,0xA7,0xC0 /* xstore %%edi (addr=%0) */"
0082         : "=m" (*addr), "=a" (eax_out), "+d" (edx_in), "+D" (addr));
0083
0084     return eax_out;
0085 }
0086
0087 static int via_rng_data_present(struct hwrng *rng, int wait)
0088 {
0089     char buf[16 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
0090         ((aligned(STACK_ALIGN)));
0091     u32 *via_rng_datum = (u32 *)PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
0092     u32 bytes_out;
0093     int i;
0094
0095     /* We choose the recommended 1-byte-per-instruction RNG rate,
0096      * for greater randomness at the expense of speed.  Larger
0097      * values 2, 4, or 8 bytes-per-instruction yield greater
0098      * speed at lesser randomness.
0099      *
0100      * If you change this to another VIA_CHUNK_n, you must also
0101      * change the ->n_bytes values in rng_vendor_ops[] tables.
0102      * VIA_CHUNK_8 requires further code changes.
0103      *
0104      * A copy of MSR_VIA_RNG is placed in eax_out when xstore
0105      * completes.
0106      */
0107
0108     for (i = 0; i < 20; i++) {
0109         *via_rng_datum = 0; /* paranoia, not really necessary */
0110         bytes_out = xstore(via_rng_datum, VIA_RNG_CHUNK_1);
0111         bytes_out &= VIA_XSTORE_CNT_MASK;
0112         if (bytes_out || !wait)
0113             break;
0114         udelay(10);
0115     }
0116     rng->priv = *via_rng_datum;
0117     return bytes_out ? 1 : 0;
0118 }
0119
0120 static int via_rng_data_read(struct hwrng *rng, u32 *data)
0121 {
0122     u32 via_rng_datum = (u32)rng->priv;
0123
0124     *data = via_rng_datum;
0125
0126     return 1;
0127 }
0128
0129 static int via_rng_init(struct hwrng *rng)
0130 {
0131     struct cpuinfo_x86 *c = &cpu_data(0);
0132     u32 lo, hi, old_lo;
0133
0134     /* VIA Nano CPUs don't have the MSR_VIA_RNG anymore.  The RNG
0135      * is always enabled if CPUID rng_en is set.  There is no
0136      * RNG configuration like it used to be the case in this
0137      * register */
0138     if (((c->x86 == 6) && (c->x86_model >= 0x0f))  || (c->x86 > 6)){
0139         if (!boot_cpu_has(X86_FEATURE_XSTORE_EN)) {
0140             pr_err(PFX "can't enable hardware RNG "
0141                 "if XSTORE is not enabled\n");
0142             return -ENODEV;
0143         }
0144         return 0;
0145     }
0146
0147     /* Control the RNG via MSR.  Tread lightly and pay very close
0148      * attention to values written, as the reserved fields
0149      * are documented to be "undefined and unpredictable"; but it
0150      * does not say to write them as zero, so I make a guess that
0151      * we restore the values we find in the register.
0152      */
0153     rdmsr(MSR_VIA_RNG, lo, hi);
0154
0155     old_lo = lo;
0156     lo &= ~(0x7f << VIA_STRFILT_CNT_SHIFT);
0157     lo &= ~VIA_XSTORE_CNT_MASK;
0158     lo &= ~(VIA_STRFILT_ENABLE | VIA_STRFILT_FAIL | VIA_RAWBITS_ENABLE);
0159     lo |= VIA_RNG_ENABLE;
0160     lo |= VIA_NOISESRC1;
0161
0162     /* Enable secondary noise source on CPUs where it is present. */
0163
0164     /* Nehemiah stepping 8 and higher */
0165     if ((c->x86_model == 9) && (c->x86_stepping > 7))
0166         lo |= VIA_NOISESRC2;
0167
0168     /* Esther */
0169     if (c->x86_model >= 10)
0170         lo |= VIA_NOISESRC2;
0171
0172     if (lo != old_lo)
0173         wrmsr(MSR_VIA_RNG, lo, hi);
0174
0175     /* perhaps-unnecessary sanity check; remove after testing if
0176        unneeded */
0177     rdmsr(MSR_VIA_RNG, lo, hi);
0178     if ((lo & VIA_RNG_ENABLE) == 0) {
0179         pr_err(PFX "cannot enable VIA C3 RNG, aborting\n");
0180         return -ENODEV;
0181     }
0182
0183     return 0;
0184 }
0185
0186
0187 static struct hwrng via_rng = {
0188     .name       = "via",
0189     .init       = via_rng_init,
0190     .data_present   = via_rng_data_present,
0191     .data_read  = via_rng_data_read,
0192 };
0193
0194
0195 static int __init via_rng_mod_init(void)
0196 {
0197     int err;
0198
0199     if (!boot_cpu_has(X86_FEATURE_XSTORE))
0200         return -ENODEV;
0201
0202     pr_info("VIA RNG detected\n");
0203     err = hwrng_register(&via_rng);
0204     if (err) {
0205         pr_err(PFX "RNG registering failed (%d)\n",
0206                err);
0207         goto out;
0208     }
0209 out:
0210     return err;
0211 }
0212 module_init(via_rng_mod_init);
0213
0214 static void __exit via_rng_mod_exit(void)
0215 {
0216     hwrng_unregister(&via_rng);
0217 }
0218 module_exit(via_rng_mod_exit);
0219
0220 static struct x86_cpu_id __maybe_unused via_rng_cpu_id[] = {
0221     X86_MATCH_FEATURE(X86_FEATURE_XSTORE, NULL),
0222     {}
0223 };
0224 MODULE_DEVICE_TABLE(x86cpu, via_rng_cpu_id);
0225
0226 MODULE_DESCRIPTION("H/W RNG driver for VIA CPU with PadLock");
0227 MODULE_LICENSE("GPL");