char/hw_random/n2rng.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* n2rng.h: Niagara2 RNG defines.
0003  *
0004  * Copyright (C) 2008 David S. Miller <davem@davemloft.net>
0005  */
0006
0007 #ifndef _N2RNG_H
0008 #define _N2RNG_H
0009
0010 /* ver1 devices - n2-rng, vf-rng, kt-rng */
0011 #define RNG_v1_CTL_WAIT       0x0000000001fffe00ULL /* Minimum wait time    */
0012 #define RNG_v1_CTL_WAIT_SHIFT 9
0013 #define RNG_v1_CTL_BYPASS     0x0000000000000100ULL /* VCO voltage source   */
0014 #define RNG_v1_CTL_VCO        0x00000000000000c0ULL /* VCO rate control     */
0015 #define RNG_v1_CTL_VCO_SHIFT  6
0016 #define RNG_v1_CTL_ASEL       0x0000000000000030ULL /* Analog MUX select    */
0017 #define RNG_v1_CTL_ASEL_SHIFT 4
0018 #define RNG_v1_CTL_ASEL_NOOUT 2
0019
0020 /* these are the same in v2 as in v1 */
0021 #define RNG_CTL_LFSR       0x0000000000000008ULL /* Use LFSR or plain shift */
0022 #define RNG_CTL_ES3        0x0000000000000004ULL /* Enable entropy source 3 */
0023 #define RNG_CTL_ES2        0x0000000000000002ULL /* Enable entropy source 2 */
0024 #define RNG_CTL_ES1        0x0000000000000001ULL /* Enable entropy source 1 */
0025
0026 /* ver2 devices - m4-rng, m7-rng */
0027 #define RNG_v2_CTL_WAIT       0x0000000007fff800ULL /* Minimum wait time    */
0028 #define RNG_v2_CTL_WAIT_SHIFT 12
0029 #define RNG_v2_CTL_BYPASS     0x0000000000000400ULL /* VCO voltage source   */
0030 #define RNG_v2_CTL_VCO        0x0000000000000300ULL /* VCO rate control     */
0031 #define RNG_v2_CTL_VCO_SHIFT  9
0032 #define RNG_v2_CTL_PERF       0x0000000000000180ULL /* Perf */
0033 #define RNG_v2_CTL_ASEL       0x0000000000000070ULL /* Analog MUX select    */
0034 #define RNG_v2_CTL_ASEL_SHIFT 4
0035 #define RNG_v2_CTL_ASEL_NOOUT 7
0036
0037
0038 #define HV_FAST_RNG_GET_DIAG_CTL    0x130
0039 #define HV_FAST_RNG_CTL_READ        0x131
0040 #define HV_FAST_RNG_CTL_WRITE       0x132
0041 #define HV_FAST_RNG_DATA_READ_DIAG  0x133
0042 #define HV_FAST_RNG_DATA_READ       0x134
0043
0044 #define HV_RNG_STATE_UNCONFIGURED   0
0045 #define HV_RNG_STATE_CONFIGURED     1
0046 #define HV_RNG_STATE_HEALTHCHECK    2
0047 #define HV_RNG_STATE_ERROR      3
0048
0049 #define HV_RNG_NUM_CONTROL      4
0050
0051 #ifndef __ASSEMBLY__
0052 extern unsigned long sun4v_rng_get_diag_ctl(void);
0053 extern unsigned long sun4v_rng_ctl_read_v1(unsigned long ctl_regs_ra,
0054                        unsigned long *state,
0055                        unsigned long *tick_delta);
0056 extern unsigned long sun4v_rng_ctl_read_v2(unsigned long ctl_regs_ra,
0057                        unsigned long unit,
0058                        unsigned long *state,
0059                        unsigned long *tick_delta,
0060                        unsigned long *watchdog,
0061                        unsigned long *write_status);
0062 extern unsigned long sun4v_rng_ctl_write_v1(unsigned long ctl_regs_ra,
0063                         unsigned long state,
0064                         unsigned long write_timeout,
0065                         unsigned long *tick_delta);
0066 extern unsigned long sun4v_rng_ctl_write_v2(unsigned long ctl_regs_ra,
0067                         unsigned long state,
0068                         unsigned long write_timeout,
0069                         unsigned long unit);
0070 extern unsigned long sun4v_rng_data_read_diag_v1(unsigned long data_ra,
0071                          unsigned long len,
0072                          unsigned long *tick_delta);
0073 extern unsigned long sun4v_rng_data_read_diag_v2(unsigned long data_ra,
0074                          unsigned long len,
0075                          unsigned long unit,
0076                          unsigned long *tick_delta);
0077 extern unsigned long sun4v_rng_data_read(unsigned long data_ra,
0078                      unsigned long *tick_delta);
0079
0080 enum n2rng_compat_id {
0081     N2_n2_rng,
0082     N2_vf_rng,
0083     N2_kt_rng,
0084     N2_m4_rng,
0085     N2_m7_rng,
0086 };
0087
0088 struct n2rng_template {
0089     enum n2rng_compat_id id;
0090     int multi_capable;
0091     int chip_version;
0092 };
0093
0094 struct n2rng_unit {
0095     u64         control[HV_RNG_NUM_CONTROL];
0096 };
0097
0098 struct n2rng {
0099     struct platform_device  *op;
0100
0101     unsigned long       flags;
0102 #define N2RNG_FLAG_MULTI    0x00000001 /* Multi-unit capable RNG */
0103 #define N2RNG_FLAG_CONTROL  0x00000002 /* Operating in control domain */
0104 #define N2RNG_FLAG_READY    0x00000008 /* Ready for hw-rng layer      */
0105 #define N2RNG_FLAG_SHUTDOWN 0x00000010 /* Driver unregistering        */
0106 #define N2RNG_FLAG_BUFFER_VALID 0x00000020 /* u32 buffer holds valid data */
0107
0108     struct n2rng_template   *data;
0109     int         num_units;
0110     struct n2rng_unit   *units;
0111
0112     struct hwrng        hwrng;
0113     u32         buffer;
0114
0115     /* Registered hypervisor group API major and minor version.  */
0116     unsigned long       hvapi_major;
0117     unsigned long       hvapi_minor;
0118
0119     struct delayed_work work;
0120
0121     unsigned long       hv_state; /* HV_RNG_STATE_foo */
0122
0123     unsigned long       health_check_sec;
0124     unsigned long       accum_cycles;
0125     unsigned long       wd_timeo;
0126 #define N2RNG_HEALTH_CHECK_SEC_DEFAULT  0
0127 #define N2RNG_ACCUM_CYCLES_DEFAULT  2048
0128 #define N2RNG_WD_TIMEO_DEFAULT      0
0129
0130     u64         scratch_control[HV_RNG_NUM_CONTROL];
0131
0132 #define RNG_v1_SELFTEST_TICKS   38859
0133 #define RNG_v1_SELFTEST_VAL ((u64)0xB8820C7BD387E32C)
0134 #define RNG_v2_SELFTEST_TICKS   64
0135 #define RNG_v2_SELFTEST_VAL ((u64)0xffffffffffffffff)
0136 #define SELFTEST_POLY       ((u64)0x231DCEE91262B8A3)
0137 #define SELFTEST_MATCH_GOAL 6
0138 #define SELFTEST_LOOPS_MAX  40000
0139 #define SELFTEST_BUFFER_WORDS   8
0140
0141     u64         test_data;
0142     u64         test_control[HV_RNG_NUM_CONTROL];
0143     u64         test_buffer[SELFTEST_BUFFER_WORDS];
0144 };
0145
0146 #define N2RNG_BLOCK_LIMIT   60000
0147 #define N2RNG_BUSY_LIMIT    100
0148 #define N2RNG_HCHECK_LIMIT  100
0149
0150 #endif /* !(__ASSEMBLY__) */
0151
0152 #endif /* _N2RNG_H */