char/hw_random/n2-drv.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* n2-drv.c: Niagara-2 RNG driver.
0003  *
0004  * Copyright (C) 2008, 2011 David S. Miller <davem@davemloft.net>
0005  */
0006
0007 #include <linux/kernel.h>
0008 #include <linux/module.h>
0009 #include <linux/types.h>
0010 #include <linux/delay.h>
0011 #include <linux/slab.h>
0012 #include <linux/workqueue.h>
0013 #include <linux/preempt.h>
0014 #include <linux/hw_random.h>
0015
0016 #include <linux/of.h>
0017 #include <linux/of_device.h>
0018
0019 #include <asm/hypervisor.h>
0020
0021 #include "n2rng.h"
0022
0023 #define DRV_MODULE_NAME     "n2rng"
0024 #define PFX DRV_MODULE_NAME ": "
0025 #define DRV_MODULE_VERSION  "0.3"
0026 #define DRV_MODULE_RELDATE  "Jan 7, 2017"
0027
0028 static char version[] =
0029     DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
0030
0031 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
0032 MODULE_DESCRIPTION("Niagara2 RNG driver");
0033 MODULE_LICENSE("GPL");
0034 MODULE_VERSION(DRV_MODULE_VERSION);
0035
0036 /* The Niagara2 RNG provides a 64-bit read-only random number
0037  * register, plus a control register.  Access to the RNG is
0038  * virtualized through the hypervisor so that both guests and control
0039  * nodes can access the device.
0040  *
0041  * The entropy source consists of raw entropy sources, each
0042  * constructed from a voltage controlled oscillator whose phase is
0043  * jittered by thermal noise sources.
0044  *
0045  * The oscillator in each of the three raw entropy sources run at
0046  * different frequencies.  Normally, all three generator outputs are
0047  * gathered, xored together, and fed into a CRC circuit, the output of
0048  * which is the 64-bit read-only register.
0049  *
0050  * Some time is necessary for all the necessary entropy to build up
0051  * such that a full 64-bits of entropy are available in the register.
0052  * In normal operating mode (RNG_CTL_LFSR is set), the chip implements
0053  * an interlock which blocks register reads until sufficient entropy
0054  * is available.
0055  *
0056  * A control register is provided for adjusting various aspects of RNG
0057  * operation, and to enable diagnostic modes.  Each of the three raw
0058  * entropy sources has an enable bit (RNG_CTL_ES{1,2,3}).  Also
0059  * provided are fields for controlling the minimum time in cycles
0060  * between read accesses to the register (RNG_CTL_WAIT, this controls
0061  * the interlock described in the previous paragraph).
0062  *
0063  * The standard setting is to have the mode bit (RNG_CTL_LFSR) set,
0064  * all three entropy sources enabled, and the interlock time set
0065  * appropriately.
0066  *
0067  * The CRC polynomial used by the chip is:
0068  *
0069  * P(X) = x64 + x61 + x57 + x56 + x52 + x51 + x50 + x48 + x47 + x46 +
0070  *        x43 + x42 + x41 + x39 + x38 + x37 + x35 + x32 + x28 + x25 +
0071  *        x22 + x21 + x17 + x15 + x13 + x12 + x11 + x7 + x5 + x + 1
0072  *
0073  * The RNG_CTL_VCO value of each noise cell must be programmed
0074  * separately.  This is why 4 control register values must be provided
0075  * to the hypervisor.  During a write, the hypervisor writes them all,
0076  * one at a time, to the actual RNG_CTL register.  The first three
0077  * values are used to setup the desired RNG_CTL_VCO for each entropy
0078  * source, for example:
0079  *
0080  *  control 0: (1 << RNG_CTL_VCO_SHIFT) | RNG_CTL_ES1
0081  *  control 1: (2 << RNG_CTL_VCO_SHIFT) | RNG_CTL_ES2
0082  *  control 2: (3 << RNG_CTL_VCO_SHIFT) | RNG_CTL_ES3
0083  *
0084  * And then the fourth value sets the final chip state and enables
0085  * desired.
0086  */
0087
0088 static int n2rng_hv_err_trans(unsigned long hv_err)
0089 {
0090     switch (hv_err) {
0091     case HV_EOK:
0092         return 0;
0093     case HV_EWOULDBLOCK:
0094         return -EAGAIN;
0095     case HV_ENOACCESS:
0096         return -EPERM;
0097     case HV_EIO:
0098         return -EIO;
0099     case HV_EBUSY:
0100         return -EBUSY;
0101     case HV_EBADALIGN:
0102     case HV_ENORADDR:
0103         return -EFAULT;
0104     default:
0105         return -EINVAL;
0106     }
0107 }
0108
0109 static unsigned long n2rng_generic_read_control_v2(unsigned long ra,
0110                            unsigned long unit)
0111 {
0112     unsigned long hv_err, state, ticks, watchdog_delta, watchdog_status;
0113     int block = 0, busy = 0;
0114
0115     while (1) {
0116         hv_err = sun4v_rng_ctl_read_v2(ra, unit, &state,
0117                            &ticks,
0118                            &watchdog_delta,
0119                            &watchdog_status);
0120         if (hv_err == HV_EOK)
0121             break;
0122
0123         if (hv_err == HV_EBUSY) {
0124             if (++busy >= N2RNG_BUSY_LIMIT)
0125                 break;
0126
0127             udelay(1);
0128         } else if (hv_err == HV_EWOULDBLOCK) {
0129             if (++block >= N2RNG_BLOCK_LIMIT)
0130                 break;
0131
0132             __delay(ticks);
0133         } else
0134             break;
0135     }
0136
0137     return hv_err;
0138 }
0139
0140 /* In multi-socket situations, the hypervisor might need to
0141  * queue up the RNG control register write if it's for a unit
0142  * that is on a cpu socket other than the one we are executing on.
0143  *
0144  * We poll here waiting for a successful read of that control
0145  * register to make sure the write has been actually performed.
0146  */
0147 static unsigned long n2rng_control_settle_v2(struct n2rng *np, int unit)
0148 {
0149     unsigned long ra = __pa(&np->scratch_control[0]);
0150
0151     return n2rng_generic_read_control_v2(ra, unit);
0152 }
0153
0154 static unsigned long n2rng_write_ctl_one(struct n2rng *np, int unit,
0155                      unsigned long state,
0156                      unsigned long control_ra,
0157                      unsigned long watchdog_timeout,
0158                      unsigned long *ticks)
0159 {
0160     unsigned long hv_err;
0161
0162     if (np->hvapi_major == 1) {
0163         hv_err = sun4v_rng_ctl_write_v1(control_ra, state,
0164                         watchdog_timeout, ticks);
0165     } else {
0166         hv_err = sun4v_rng_ctl_write_v2(control_ra, state,
0167                         watchdog_timeout, unit);
0168         if (hv_err == HV_EOK)
0169             hv_err = n2rng_control_settle_v2(np, unit);
0170         *ticks = N2RNG_ACCUM_CYCLES_DEFAULT;
0171     }
0172
0173     return hv_err;
0174 }
0175
0176 static int n2rng_generic_read_data(unsigned long data_ra)
0177 {
0178     unsigned long ticks, hv_err;
0179     int block = 0, hcheck = 0;
0180
0181     while (1) {
0182         hv_err = sun4v_rng_data_read(data_ra, &ticks);
0183         if (hv_err == HV_EOK)
0184             return 0;
0185
0186         if (hv_err == HV_EWOULDBLOCK) {
0187             if (++block >= N2RNG_BLOCK_LIMIT)
0188                 return -EWOULDBLOCK;
0189             __delay(ticks);
0190         } else if (hv_err == HV_ENOACCESS) {
0191             return -EPERM;
0192         } else if (hv_err == HV_EIO) {
0193             if (++hcheck >= N2RNG_HCHECK_LIMIT)
0194                 return -EIO;
0195             udelay(10000);
0196         } else
0197             return -ENODEV;
0198     }
0199 }
0200
0201 static unsigned long n2rng_read_diag_data_one(struct n2rng *np,
0202                           unsigned long unit,
0203                           unsigned long data_ra,
0204                           unsigned long data_len,
0205                           unsigned long *ticks)
0206 {
0207     unsigned long hv_err;
0208
0209     if (np->hvapi_major == 1) {
0210         hv_err = sun4v_rng_data_read_diag_v1(data_ra, data_len, ticks);
0211     } else {
0212         hv_err = sun4v_rng_data_read_diag_v2(data_ra, data_len,
0213                              unit, ticks);
0214         if (!*ticks)
0215             *ticks = N2RNG_ACCUM_CYCLES_DEFAULT;
0216     }
0217     return hv_err;
0218 }
0219
0220 static int n2rng_generic_read_diag_data(struct n2rng *np,
0221                     unsigned long unit,
0222                     unsigned long data_ra,
0223                     unsigned long data_len)
0224 {
0225     unsigned long ticks, hv_err;
0226     int block = 0;
0227
0228     while (1) {
0229         hv_err = n2rng_read_diag_data_one(np, unit,
0230                           data_ra, data_len,
0231                           &ticks);
0232         if (hv_err == HV_EOK)
0233             return 0;
0234
0235         if (hv_err == HV_EWOULDBLOCK) {
0236             if (++block >= N2RNG_BLOCK_LIMIT)
0237                 return -EWOULDBLOCK;
0238             __delay(ticks);
0239         } else if (hv_err == HV_ENOACCESS) {
0240             return -EPERM;
0241         } else if (hv_err == HV_EIO) {
0242             return -EIO;
0243         } else
0244             return -ENODEV;
0245     }
0246 }
0247
0248
0249 static int n2rng_generic_write_control(struct n2rng *np,
0250                        unsigned long control_ra,
0251                        unsigned long unit,
0252                        unsigned long state)
0253 {
0254     unsigned long hv_err, ticks;
0255     int block = 0, busy = 0;
0256
0257     while (1) {
0258         hv_err = n2rng_write_ctl_one(np, unit, state, control_ra,
0259                          np->wd_timeo, &ticks);
0260         if (hv_err == HV_EOK)
0261             return 0;
0262
0263         if (hv_err == HV_EWOULDBLOCK) {
0264             if (++block >= N2RNG_BLOCK_LIMIT)
0265                 return -EWOULDBLOCK;
0266             __delay(ticks);
0267         } else if (hv_err == HV_EBUSY) {
0268             if (++busy >= N2RNG_BUSY_LIMIT)
0269                 return -EBUSY;
0270             udelay(1);
0271         } else
0272             return -ENODEV;
0273     }
0274 }
0275
0276 /* Just try to see if we can successfully access the control register
0277  * of the RNG on the domain on which we are currently executing.
0278  */
0279 static int n2rng_try_read_ctl(struct n2rng *np)
0280 {
0281     unsigned long hv_err;
0282     unsigned long x;
0283
0284     if (np->hvapi_major == 1) {
0285         hv_err = sun4v_rng_get_diag_ctl();
0286     } else {
0287         /* We purposefully give invalid arguments, HV_NOACCESS
0288          * is higher priority than the errors we'd get from
0289          * these other cases, and that's the error we are
0290          * truly interested in.
0291          */
0292         hv_err = sun4v_rng_ctl_read_v2(0UL, ~0UL, &x, &x, &x, &x);
0293         switch (hv_err) {
0294         case HV_EWOULDBLOCK:
0295         case HV_ENOACCESS:
0296             break;
0297         default:
0298             hv_err = HV_EOK;
0299             break;
0300         }
0301     }
0302
0303     return n2rng_hv_err_trans(hv_err);
0304 }
0305
0306 static u64 n2rng_control_default(struct n2rng *np, int ctl)
0307 {
0308     u64 val = 0;
0309
0310     if (np->data->chip_version == 1) {
0311         val = ((2 << RNG_v1_CTL_ASEL_SHIFT) |
0312             (N2RNG_ACCUM_CYCLES_DEFAULT << RNG_v1_CTL_WAIT_SHIFT) |
0313              RNG_CTL_LFSR);
0314
0315         switch (ctl) {
0316         case 0:
0317             val |= (1 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES1;
0318             break;
0319         case 1:
0320             val |= (2 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES2;
0321             break;
0322         case 2:
0323             val |= (3 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES3;
0324             break;
0325         case 3:
0326             val |= RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3;
0327             break;
0328         default:
0329             break;
0330         }
0331
0332     } else {
0333         val = ((2 << RNG_v2_CTL_ASEL_SHIFT) |
0334             (N2RNG_ACCUM_CYCLES_DEFAULT << RNG_v2_CTL_WAIT_SHIFT) |
0335              RNG_CTL_LFSR);
0336
0337         switch (ctl) {
0338         case 0:
0339             val |= (1 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES1;
0340             break;
0341         case 1:
0342             val |= (2 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES2;
0343             break;
0344         case 2:
0345             val |= (3 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES3;
0346             break;
0347         case 3:
0348             val |= RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3;
0349             break;
0350         default:
0351             break;
0352         }
0353     }
0354
0355     return val;
0356 }
0357
0358 static void n2rng_control_swstate_init(struct n2rng *np)
0359 {
0360     int i;
0361
0362     np->flags |= N2RNG_FLAG_CONTROL;
0363
0364     np->health_check_sec = N2RNG_HEALTH_CHECK_SEC_DEFAULT;
0365     np->accum_cycles = N2RNG_ACCUM_CYCLES_DEFAULT;
0366     np->wd_timeo = N2RNG_WD_TIMEO_DEFAULT;
0367
0368     for (i = 0; i < np->num_units; i++) {
0369         struct n2rng_unit *up = &np->units[i];
0370
0371         up->control[0] = n2rng_control_default(np, 0);
0372         up->control[1] = n2rng_control_default(np, 1);
0373         up->control[2] = n2rng_control_default(np, 2);
0374         up->control[3] = n2rng_control_default(np, 3);
0375     }
0376
0377     np->hv_state = HV_RNG_STATE_UNCONFIGURED;
0378 }
0379
0380 static int n2rng_grab_diag_control(struct n2rng *np)
0381 {
0382     int i, busy_count, err = -ENODEV;
0383
0384     busy_count = 0;
0385     for (i = 0; i < 100; i++) {
0386         err = n2rng_try_read_ctl(np);
0387         if (err != -EAGAIN)
0388             break;
0389
0390         if (++busy_count > 100) {
0391             dev_err(&np->op->dev,
0392                 "Grab diag control timeout.\n");
0393             return -ENODEV;
0394         }
0395
0396         udelay(1);
0397     }
0398
0399     return err;
0400 }
0401
0402 static int n2rng_init_control(struct n2rng *np)
0403 {
0404     int err = n2rng_grab_diag_control(np);
0405
0406     /* Not in the control domain, that's OK we are only a consumer
0407      * of the RNG data, we don't setup and program it.
0408      */
0409     if (err == -EPERM)
0410         return 0;
0411     if (err)
0412         return err;
0413
0414     n2rng_control_swstate_init(np);
0415
0416     return 0;
0417 }
0418
0419 static int n2rng_data_read(struct hwrng *rng, u32 *data)
0420 {
0421     struct n2rng *np = (struct n2rng *) rng->priv;
0422     unsigned long ra = __pa(&np->test_data);
0423     int len;
0424
0425     if (!(np->flags & N2RNG_FLAG_READY)) {
0426         len = 0;
0427     } else if (np->flags & N2RNG_FLAG_BUFFER_VALID) {
0428         np->flags &= ~N2RNG_FLAG_BUFFER_VALID;
0429         *data = np->buffer;
0430         len = 4;
0431     } else {
0432         int err = n2rng_generic_read_data(ra);
0433         if (!err) {
0434             np->flags |= N2RNG_FLAG_BUFFER_VALID;
0435             np->buffer = np->test_data >> 32;
0436             *data = np->test_data & 0xffffffff;
0437             len = 4;
0438         } else {
0439             dev_err(&np->op->dev, "RNG error, retesting\n");
0440             np->flags &= ~N2RNG_FLAG_READY;
0441             if (!(np->flags & N2RNG_FLAG_SHUTDOWN))
0442                 schedule_delayed_work(&np->work, 0);
0443             len = 0;
0444         }
0445     }
0446
0447     return len;
0448 }
0449
0450 /* On a guest node, just make sure we can read random data properly.
0451  * If a control node reboots or reloads it's n2rng driver, this won't
0452  * work during that time.  So we have to keep probing until the device
0453  * becomes usable.
0454  */
0455 static int n2rng_guest_check(struct n2rng *np)
0456 {
0457     unsigned long ra = __pa(&np->test_data);
0458
0459     return n2rng_generic_read_data(ra);
0460 }
0461
0462 static int n2rng_entropy_diag_read(struct n2rng *np, unsigned long unit,
0463                    u64 *pre_control, u64 pre_state,
0464                    u64 *buffer, unsigned long buf_len,
0465                    u64 *post_control, u64 post_state)
0466 {
0467     unsigned long post_ctl_ra = __pa(post_control);
0468     unsigned long pre_ctl_ra = __pa(pre_control);
0469     unsigned long buffer_ra = __pa(buffer);
0470     int err;
0471
0472     err = n2rng_generic_write_control(np, pre_ctl_ra, unit, pre_state);
0473     if (err)
0474         return err;
0475
0476     err = n2rng_generic_read_diag_data(np, unit,
0477                        buffer_ra, buf_len);
0478
0479     (void) n2rng_generic_write_control(np, post_ctl_ra, unit,
0480                        post_state);
0481
0482     return err;
0483 }
0484
0485 static u64 advance_polynomial(u64 poly, u64 val, int count)
0486 {
0487     int i;
0488
0489     for (i = 0; i < count; i++) {
0490         int highbit_set = ((s64)val < 0);
0491
0492         val <<= 1;
0493         if (highbit_set)
0494             val ^= poly;
0495     }
0496
0497     return val;
0498 }
0499
0500 static int n2rng_test_buffer_find(struct n2rng *np, u64 val)
0501 {
0502     int i, count = 0;
0503
0504     /* Purposefully skip over the first word.  */
0505     for (i = 1; i < SELFTEST_BUFFER_WORDS; i++) {
0506         if (np->test_buffer[i] == val)
0507             count++;
0508     }
0509     return count;
0510 }
0511
0512 static void n2rng_dump_test_buffer(struct n2rng *np)
0513 {
0514     int i;
0515
0516     for (i = 0; i < SELFTEST_BUFFER_WORDS; i++)
0517         dev_err(&np->op->dev, "Test buffer slot %d [0x%016llx]\n",
0518             i, np->test_buffer[i]);
0519 }
0520
0521 static int n2rng_check_selftest_buffer(struct n2rng *np, unsigned long unit)
0522 {
0523     u64 val;
0524     int err, matches, limit;
0525
0526     switch (np->data->id) {
0527     case N2_n2_rng:
0528     case N2_vf_rng:
0529     case N2_kt_rng:
0530     case N2_m4_rng:  /* yes, m4 uses the old value */
0531         val = RNG_v1_SELFTEST_VAL;
0532         break;
0533     default:
0534         val = RNG_v2_SELFTEST_VAL;
0535         break;
0536     }
0537
0538     matches = 0;
0539     for (limit = 0; limit < SELFTEST_LOOPS_MAX; limit++) {
0540         matches += n2rng_test_buffer_find(np, val);
0541         if (matches >= SELFTEST_MATCH_GOAL)
0542             break;
0543         val = advance_polynomial(SELFTEST_POLY, val, 1);
0544     }
0545
0546     err = 0;
0547     if (limit >= SELFTEST_LOOPS_MAX) {
0548         err = -ENODEV;
0549         dev_err(&np->op->dev, "Selftest failed on unit %lu\n", unit);
0550         n2rng_dump_test_buffer(np);
0551     } else
0552         dev_info(&np->op->dev, "Selftest passed on unit %lu\n", unit);
0553
0554     return err;
0555 }
0556
0557 static int n2rng_control_selftest(struct n2rng *np, unsigned long unit)
0558 {
0559     int err;
0560     u64 base, base3;
0561
0562     switch (np->data->id) {
0563     case N2_n2_rng:
0564     case N2_vf_rng:
0565     case N2_kt_rng:
0566         base = RNG_v1_CTL_ASEL_NOOUT << RNG_v1_CTL_ASEL_SHIFT;
0567         base3 = base | RNG_CTL_LFSR |
0568             ((RNG_v1_SELFTEST_TICKS - 2) << RNG_v1_CTL_WAIT_SHIFT);
0569         break;
0570     case N2_m4_rng:
0571         base = RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT;
0572         base3 = base | RNG_CTL_LFSR |
0573             ((RNG_v1_SELFTEST_TICKS - 2) << RNG_v2_CTL_WAIT_SHIFT);
0574         break;
0575     default:
0576         base = RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT;
0577         base3 = base | RNG_CTL_LFSR |
0578             (RNG_v2_SELFTEST_TICKS << RNG_v2_CTL_WAIT_SHIFT);
0579         break;
0580     }
0581
0582     np->test_control[0] = base;
0583     np->test_control[1] = base;
0584     np->test_control[2] = base;
0585     np->test_control[3] = base3;
0586
0587     err = n2rng_entropy_diag_read(np, unit, np->test_control,
0588                       HV_RNG_STATE_HEALTHCHECK,
0589                       np->test_buffer,
0590                       sizeof(np->test_buffer),
0591                       &np->units[unit].control[0],
0592                       np->hv_state);
0593     if (err)
0594         return err;
0595
0596     return n2rng_check_selftest_buffer(np, unit);
0597 }
0598
0599 static int n2rng_control_check(struct n2rng *np)
0600 {
0601     int i;
0602
0603     for (i = 0; i < np->num_units; i++) {
0604         int err = n2rng_control_selftest(np, i);
0605         if (err)
0606             return err;
0607     }
0608     return 0;
0609 }
0610
0611 /* The sanity checks passed, install the final configuration into the
0612  * chip, it's ready to use.
0613  */
0614 static int n2rng_control_configure_units(struct n2rng *np)
0615 {
0616     int unit, err;
0617
0618     err = 0;
0619     for (unit = 0; unit < np->num_units; unit++) {
0620         struct n2rng_unit *up = &np->units[unit];
0621         unsigned long ctl_ra = __pa(&up->control[0]);
0622         int esrc;
0623         u64 base, shift;
0624
0625         if (np->data->chip_version == 1) {
0626             base = ((np->accum_cycles << RNG_v1_CTL_WAIT_SHIFT) |
0627                   (RNG_v1_CTL_ASEL_NOOUT << RNG_v1_CTL_ASEL_SHIFT) |
0628                   RNG_CTL_LFSR);
0629             shift = RNG_v1_CTL_VCO_SHIFT;
0630         } else {
0631             base = ((np->accum_cycles << RNG_v2_CTL_WAIT_SHIFT) |
0632                   (RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT) |
0633                   RNG_CTL_LFSR);
0634             shift = RNG_v2_CTL_VCO_SHIFT;
0635         }
0636
0637         /* XXX This isn't the best.  We should fetch a bunch
0638          * XXX of words using each entropy source combined XXX
0639          * with each VCO setting, and see which combinations
0640          * XXX give the best random data.
0641          */
0642         for (esrc = 0; esrc < 3; esrc++)
0643             up->control[esrc] = base |
0644                 (esrc << shift) |
0645                 (RNG_CTL_ES1 << esrc);
0646
0647         up->control[3] = base |
0648             (RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3);
0649
0650         err = n2rng_generic_write_control(np, ctl_ra, unit,
0651                           HV_RNG_STATE_CONFIGURED);
0652         if (err)
0653             break;
0654     }
0655
0656     return err;
0657 }
0658
0659 static void n2rng_work(struct work_struct *work)
0660 {
0661     struct n2rng *np = container_of(work, struct n2rng, work.work);
0662     int err = 0;
0663     static int retries = 4;
0664
0665     if (!(np->flags & N2RNG_FLAG_CONTROL)) {
0666         err = n2rng_guest_check(np);
0667     } else {
0668         preempt_disable();
0669         err = n2rng_control_check(np);
0670         preempt_enable();
0671
0672         if (!err)
0673             err = n2rng_control_configure_units(np);
0674     }
0675
0676     if (!err) {
0677         np->flags |= N2RNG_FLAG_READY;
0678         dev_info(&np->op->dev, "RNG ready\n");
0679     }
0680
0681     if (--retries == 0)
0682         dev_err(&np->op->dev, "Self-test retries failed, RNG not ready\n");
0683     else if (err && !(np->flags & N2RNG_FLAG_SHUTDOWN))
0684         schedule_delayed_work(&np->work, HZ * 2);
0685 }
0686
0687 static void n2rng_driver_version(void)
0688 {
0689     static int n2rng_version_printed;
0690
0691     if (n2rng_version_printed++ == 0)
0692         pr_info("%s", version);
0693 }
0694
0695 static const struct of_device_id n2rng_match[];
0696 static int n2rng_probe(struct platform_device *op)
0697 {
0698     const struct of_device_id *match;
0699     int err = -ENOMEM;
0700     struct n2rng *np;
0701
0702     match = of_match_device(n2rng_match, &op->dev);
0703     if (!match)
0704         return -EINVAL;
0705
0706     n2rng_driver_version();
0707     np = devm_kzalloc(&op->dev, sizeof(*np), GFP_KERNEL);
0708     if (!np)
0709         goto out;
0710     np->op = op;
0711     np->data = (struct n2rng_template *)match->data;
0712
0713     INIT_DELAYED_WORK(&np->work, n2rng_work);
0714
0715     if (np->data->multi_capable)
0716         np->flags |= N2RNG_FLAG_MULTI;
0717
0718     err = -ENODEV;
0719     np->hvapi_major = 2;
0720     if (sun4v_hvapi_register(HV_GRP_RNG,
0721                  np->hvapi_major,
0722                  &np->hvapi_minor)) {
0723         np->hvapi_major = 1;
0724         if (sun4v_hvapi_register(HV_GRP_RNG,
0725                      np->hvapi_major,
0726                      &np->hvapi_minor)) {
0727             dev_err(&op->dev, "Cannot register suitable "
0728                 "HVAPI version.\n");
0729             goto out;
0730         }
0731     }
0732
0733     if (np->flags & N2RNG_FLAG_MULTI) {
0734         if (np->hvapi_major < 2) {
0735             dev_err(&op->dev, "multi-unit-capable RNG requires "
0736                 "HVAPI major version 2 or later, got %lu\n",
0737                 np->hvapi_major);
0738             goto out_hvapi_unregister;
0739         }
0740         np->num_units = of_getintprop_default(op->dev.of_node,
0741                               "rng-#units", 0);
0742         if (!np->num_units) {
0743             dev_err(&op->dev, "VF RNG lacks rng-#units property\n");
0744             goto out_hvapi_unregister;
0745         }
0746     } else {
0747         np->num_units = 1;
0748     }
0749
0750     dev_info(&op->dev, "Registered RNG HVAPI major %lu minor %lu\n",
0751          np->hvapi_major, np->hvapi_minor);
0752     np->units = devm_kcalloc(&op->dev, np->num_units, sizeof(*np->units),
0753                  GFP_KERNEL);
0754     err = -ENOMEM;
0755     if (!np->units)
0756         goto out_hvapi_unregister;
0757
0758     err = n2rng_init_control(np);
0759     if (err)
0760         goto out_hvapi_unregister;
0761
0762     dev_info(&op->dev, "Found %s RNG, units: %d\n",
0763          ((np->flags & N2RNG_FLAG_MULTI) ?
0764           "multi-unit-capable" : "single-unit"),
0765          np->num_units);
0766
0767     np->hwrng.name = DRV_MODULE_NAME;
0768     np->hwrng.data_read = n2rng_data_read;
0769     np->hwrng.priv = (unsigned long) np;
0770
0771     err = devm_hwrng_register(&op->dev, &np->hwrng);
0772     if (err)
0773         goto out_hvapi_unregister;
0774
0775     platform_set_drvdata(op, np);
0776
0777     schedule_delayed_work(&np->work, 0);
0778
0779     return 0;
0780
0781 out_hvapi_unregister:
0782     sun4v_hvapi_unregister(HV_GRP_RNG);
0783
0784 out:
0785     return err;
0786 }
0787
0788 static int n2rng_remove(struct platform_device *op)
0789 {
0790     struct n2rng *np = platform_get_drvdata(op);
0791
0792     np->flags |= N2RNG_FLAG_SHUTDOWN;
0793
0794     cancel_delayed_work_sync(&np->work);
0795
0796     sun4v_hvapi_unregister(HV_GRP_RNG);
0797
0798     return 0;
0799 }
0800
0801 static struct n2rng_template n2_template = {
0802     .id = N2_n2_rng,
0803     .multi_capable = 0,
0804     .chip_version = 1,
0805 };
0806
0807 static struct n2rng_template vf_template = {
0808     .id = N2_vf_rng,
0809     .multi_capable = 1,
0810     .chip_version = 1,
0811 };
0812
0813 static struct n2rng_template kt_template = {
0814     .id = N2_kt_rng,
0815     .multi_capable = 1,
0816     .chip_version = 1,
0817 };
0818
0819 static struct n2rng_template m4_template = {
0820     .id = N2_m4_rng,
0821     .multi_capable = 1,
0822     .chip_version = 2,
0823 };
0824
0825 static struct n2rng_template m7_template = {
0826     .id = N2_m7_rng,
0827     .multi_capable = 1,
0828     .chip_version = 2,
0829 };
0830
0831 static const struct of_device_id n2rng_match[] = {
0832     {
0833         .name       = "random-number-generator",
0834         .compatible = "SUNW,n2-rng",
0835         .data       = &n2_template,
0836     },
0837     {
0838         .name       = "random-number-generator",
0839         .compatible = "SUNW,vf-rng",
0840         .data       = &vf_template,
0841     },
0842     {
0843         .name       = "random-number-generator",
0844         .compatible = "SUNW,kt-rng",
0845         .data       = &kt_template,
0846     },
0847     {
0848         .name       = "random-number-generator",
0849         .compatible = "ORCL,m4-rng",
0850         .data       = &m4_template,
0851     },
0852     {
0853         .name       = "random-number-generator",
0854         .compatible = "ORCL,m7-rng",
0855         .data       = &m7_template,
0856     },
0857     {},
0858 };
0859 MODULE_DEVICE_TABLE(of, n2rng_match);
0860
0861 static struct platform_driver n2rng_driver = {
0862     .driver = {
0863         .name = "n2rng",
0864         .of_match_table = n2rng_match,
0865     },
0866     .probe      = n2rng_probe,
0867     .remove     = n2rng_remove,
0868 };
0869
0870 module_platform_driver(n2rng_driver);