char/hw_random/mtk-rng.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for Mediatek Hardware Random Number Generator
0004  *
0005  * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
0006  */
0007 #define MTK_RNG_DEV KBUILD_MODNAME
0008
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/err.h>
0012 #include <linux/hw_random.h>
0013 #include <linux/io.h>
0014 #include <linux/iopoll.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/of.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/pm_runtime.h>
0020
0021 /* Runtime PM autosuspend timeout: */
0022 #define RNG_AUTOSUSPEND_TIMEOUT     100
0023
0024 #define USEC_POLL           2
0025 #define TIMEOUT_POLL            20
0026
0027 #define RNG_CTRL            0x00
0028 #define RNG_EN              BIT(0)
0029 #define RNG_READY           BIT(31)
0030
0031 #define RNG_DATA            0x08
0032
0033 #define to_mtk_rng(p)   container_of(p, struct mtk_rng, rng)
0034
0035 struct mtk_rng {
0036     void __iomem *base;
0037     struct clk *clk;
0038     struct hwrng rng;
0039 };
0040
0041 static int mtk_rng_init(struct hwrng *rng)
0042 {
0043     struct mtk_rng *priv = to_mtk_rng(rng);
0044     u32 val;
0045     int err;
0046
0047     err = clk_prepare_enable(priv->clk);
0048     if (err)
0049         return err;
0050
0051     val = readl(priv->base + RNG_CTRL);
0052     val |= RNG_EN;
0053     writel(val, priv->base + RNG_CTRL);
0054
0055     return 0;
0056 }
0057
0058 static void mtk_rng_cleanup(struct hwrng *rng)
0059 {
0060     struct mtk_rng *priv = to_mtk_rng(rng);
0061     u32 val;
0062
0063     val = readl(priv->base + RNG_CTRL);
0064     val &= ~RNG_EN;
0065     writel(val, priv->base + RNG_CTRL);
0066
0067     clk_disable_unprepare(priv->clk);
0068 }
0069
0070 static bool mtk_rng_wait_ready(struct hwrng *rng, bool wait)
0071 {
0072     struct mtk_rng *priv = to_mtk_rng(rng);
0073     int ready;
0074
0075     ready = readl(priv->base + RNG_CTRL) & RNG_READY;
0076     if (!ready && wait)
0077         readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready,
0078                       ready & RNG_READY, USEC_POLL,
0079                       TIMEOUT_POLL);
0080     return !!ready;
0081 }
0082
0083 static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
0084 {
0085     struct mtk_rng *priv = to_mtk_rng(rng);
0086     int retval = 0;
0087
0088     pm_runtime_get_sync((struct device *)priv->rng.priv);
0089
0090     while (max >= sizeof(u32)) {
0091         if (!mtk_rng_wait_ready(rng, wait))
0092             break;
0093
0094         *(u32 *)buf = readl(priv->base + RNG_DATA);
0095         retval += sizeof(u32);
0096         buf += sizeof(u32);
0097         max -= sizeof(u32);
0098     }
0099
0100     pm_runtime_mark_last_busy((struct device *)priv->rng.priv);
0101     pm_runtime_put_sync_autosuspend((struct device *)priv->rng.priv);
0102
0103     return retval || !wait ? retval : -EIO;
0104 }
0105
0106 static int mtk_rng_probe(struct platform_device *pdev)
0107 {
0108     int ret;
0109     struct mtk_rng *priv;
0110
0111     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0112     if (!priv)
0113         return -ENOMEM;
0114
0115     priv->rng.name = pdev->name;
0116 #ifndef CONFIG_PM
0117     priv->rng.init = mtk_rng_init;
0118     priv->rng.cleanup = mtk_rng_cleanup;
0119 #endif
0120     priv->rng.read = mtk_rng_read;
0121     priv->rng.priv = (unsigned long)&pdev->dev;
0122     priv->rng.quality = 900;
0123
0124     priv->clk = devm_clk_get(&pdev->dev, "rng");
0125     if (IS_ERR(priv->clk)) {
0126         ret = PTR_ERR(priv->clk);
0127         dev_err(&pdev->dev, "no clock for device: %d\n", ret);
0128         return ret;
0129     }
0130
0131     priv->base = devm_platform_ioremap_resource(pdev, 0);
0132     if (IS_ERR(priv->base))
0133         return PTR_ERR(priv->base);
0134
0135     ret = devm_hwrng_register(&pdev->dev, &priv->rng);
0136     if (ret) {
0137         dev_err(&pdev->dev, "failed to register rng device: %d\n",
0138             ret);
0139         return ret;
0140     }
0141
0142     dev_set_drvdata(&pdev->dev, priv);
0143     pm_runtime_set_autosuspend_delay(&pdev->dev, RNG_AUTOSUSPEND_TIMEOUT);
0144     pm_runtime_use_autosuspend(&pdev->dev);
0145     pm_runtime_enable(&pdev->dev);
0146
0147     dev_info(&pdev->dev, "registered RNG driver\n");
0148
0149     return 0;
0150 }
0151
0152 #ifdef CONFIG_PM
0153 static int mtk_rng_runtime_suspend(struct device *dev)
0154 {
0155     struct mtk_rng *priv = dev_get_drvdata(dev);
0156
0157     mtk_rng_cleanup(&priv->rng);
0158
0159     return 0;
0160 }
0161
0162 static int mtk_rng_runtime_resume(struct device *dev)
0163 {
0164     struct mtk_rng *priv = dev_get_drvdata(dev);
0165
0166     return mtk_rng_init(&priv->rng);
0167 }
0168
0169 static const struct dev_pm_ops mtk_rng_pm_ops = {
0170     SET_RUNTIME_PM_OPS(mtk_rng_runtime_suspend,
0171                mtk_rng_runtime_resume, NULL)
0172     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0173                 pm_runtime_force_resume)
0174 };
0175
0176 #define MTK_RNG_PM_OPS (&mtk_rng_pm_ops)
0177 #else   /* CONFIG_PM */
0178 #define MTK_RNG_PM_OPS NULL
0179 #endif  /* CONFIG_PM */
0180
0181 static const struct of_device_id mtk_rng_match[] = {
0182     { .compatible = "mediatek,mt7623-rng" },
0183     {},
0184 };
0185 MODULE_DEVICE_TABLE(of, mtk_rng_match);
0186
0187 static struct platform_driver mtk_rng_driver = {
0188     .probe          = mtk_rng_probe,
0189     .driver = {
0190         .name = MTK_RNG_DEV,
0191         .pm = MTK_RNG_PM_OPS,
0192         .of_match_table = mtk_rng_match,
0193     },
0194 };
0195
0196 module_platform_driver(mtk_rng_driver);
0197
0198 MODULE_DESCRIPTION("Mediatek Random Number Generator Driver");
0199 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
0200 MODULE_LICENSE("GPL");