char/hw_random/mpfs-rng.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Microchip PolarFire SoC (MPFS) hardware random driver
0004  *
0005  * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
0006  *
0007  * Author: Conor Dooley <conor.dooley@microchip.com>
0008  */
0009
0010 #include <linux/module.h>
0011 #include <linux/hw_random.h>
0012 #include <linux/platform_device.h>
0013 #include <soc/microchip/mpfs.h>
0014
0015 #define CMD_OPCODE  0x21
0016 #define CMD_DATA_SIZE   0U
0017 #define CMD_DATA    NULL
0018 #define MBOX_OFFSET 0U
0019 #define RESP_OFFSET 0U
0020 #define RNG_RESP_BYTES  32U
0021
0022 struct mpfs_rng {
0023     struct mpfs_sys_controller *sys_controller;
0024     struct hwrng rng;
0025 };
0026
0027 static int mpfs_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
0028 {
0029     struct mpfs_rng *rng_priv = container_of(rng, struct mpfs_rng, rng);
0030     u32 response_msg[RNG_RESP_BYTES / sizeof(u32)];
0031     unsigned int count = 0, copy_size_bytes;
0032     int ret;
0033
0034     struct mpfs_mss_response response = {
0035         .resp_status = 0U,
0036         .resp_msg = (u32 *)response_msg,
0037         .resp_size = RNG_RESP_BYTES
0038     };
0039     struct mpfs_mss_msg msg = {
0040         .cmd_opcode = CMD_OPCODE,
0041         .cmd_data_size = CMD_DATA_SIZE,
0042         .response = &response,
0043         .cmd_data = CMD_DATA,
0044         .mbox_offset = MBOX_OFFSET,
0045         .resp_offset = RESP_OFFSET
0046     };
0047
0048     while (count < max) {
0049         ret = mpfs_blocking_transaction(rng_priv->sys_controller, &msg);
0050         if (ret)
0051             return ret;
0052
0053         copy_size_bytes = max - count > RNG_RESP_BYTES ? RNG_RESP_BYTES : max - count;
0054         memcpy(buf + count, response_msg, copy_size_bytes);
0055
0056         count += copy_size_bytes;
0057         if (!wait)
0058             break;
0059     }
0060
0061     return count;
0062 }
0063
0064 static int mpfs_rng_probe(struct platform_device *pdev)
0065 {
0066     struct device *dev = &pdev->dev;
0067     struct mpfs_rng *rng_priv;
0068     int ret;
0069
0070     rng_priv = devm_kzalloc(dev, sizeof(*rng_priv), GFP_KERNEL);
0071     if (!rng_priv)
0072         return -ENOMEM;
0073
0074     rng_priv->sys_controller =  mpfs_sys_controller_get(&pdev->dev);
0075     if (IS_ERR(rng_priv->sys_controller))
0076         return dev_err_probe(dev, PTR_ERR(rng_priv->sys_controller),
0077                      "Failed to register system controller hwrng sub device\n");
0078
0079     rng_priv->rng.read = mpfs_rng_read;
0080     rng_priv->rng.name = pdev->name;
0081     rng_priv->rng.quality = 1024;
0082
0083     platform_set_drvdata(pdev, rng_priv);
0084
0085     ret = devm_hwrng_register(&pdev->dev, &rng_priv->rng);
0086     if (ret)
0087         return dev_err_probe(&pdev->dev, ret, "Failed to register MPFS hwrng\n");
0088
0089     dev_info(&pdev->dev, "Registered MPFS hwrng\n");
0090
0091     return 0;
0092 }
0093
0094 static struct platform_driver mpfs_rng_driver = {
0095     .driver = {
0096         .name = "mpfs-rng",
0097     },
0098     .probe = mpfs_rng_probe,
0099 };
0100 module_platform_driver(mpfs_rng_driver);
0101
0102 MODULE_LICENSE("GPL");
0103 MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
0104 MODULE_DESCRIPTION("PolarFire SoC (MPFS) hardware random driver");