char/hw_random/iproc-rng200.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2015 Broadcom Corporation
0004 *
0005 */
0006 /*
0007  * DESCRIPTION: The Broadcom iProc RNG200 Driver
0008  */
0009
0010 #include <linux/hw_random.h>
0011 #include <linux/init.h>
0012 #include <linux/io.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of_platform.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/delay.h>
0019
0020 /* Registers */
0021 #define RNG_CTRL_OFFSET                 0x00
0022 #define RNG_CTRL_RNG_RBGEN_MASK             0x00001FFF
0023 #define RNG_CTRL_RNG_RBGEN_ENABLE           0x00000001
0024
0025 #define RNG_SOFT_RESET_OFFSET               0x04
0026 #define RNG_SOFT_RESET                  0x00000001
0027
0028 #define RBG_SOFT_RESET_OFFSET               0x08
0029 #define RBG_SOFT_RESET                  0x00000001
0030
0031 #define RNG_INT_STATUS_OFFSET               0x18
0032 #define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK 0x80000000
0033 #define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK 0x00020000
0034 #define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK       0x00000020
0035 #define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK    0x00000001
0036
0037 #define RNG_FIFO_DATA_OFFSET                0x20
0038
0039 #define RNG_FIFO_COUNT_OFFSET               0x24
0040 #define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK      0x000000FF
0041
0042 struct iproc_rng200_dev {
0043     struct hwrng rng;
0044     void __iomem *base;
0045 };
0046
0047 #define to_rng_priv(rng)    container_of(rng, struct iproc_rng200_dev, rng)
0048
0049 static void iproc_rng200_enable_set(void __iomem *rng_base, bool enable)
0050 {
0051     u32 val;
0052
0053     val = ioread32(rng_base + RNG_CTRL_OFFSET);
0054     val &= ~RNG_CTRL_RNG_RBGEN_MASK;
0055
0056     if (enable)
0057         val |= RNG_CTRL_RNG_RBGEN_ENABLE;
0058
0059     iowrite32(val, rng_base + RNG_CTRL_OFFSET);
0060 }
0061
0062 static void iproc_rng200_restart(void __iomem *rng_base)
0063 {
0064     uint32_t val;
0065
0066     iproc_rng200_enable_set(rng_base, false);
0067
0068     /* Clear all interrupt status */
0069     iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
0070
0071     /* Reset RNG and RBG */
0072     val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
0073     val |= RBG_SOFT_RESET;
0074     iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
0075
0076     val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
0077     val |= RNG_SOFT_RESET;
0078     iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
0079
0080     val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
0081     val &= ~RNG_SOFT_RESET;
0082     iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
0083
0084     val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
0085     val &= ~RBG_SOFT_RESET;
0086     iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
0087
0088     iproc_rng200_enable_set(rng_base, true);
0089 }
0090
0091 static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max,
0092                  bool wait)
0093 {
0094     struct iproc_rng200_dev *priv = to_rng_priv(rng);
0095     uint32_t num_remaining = max;
0096     uint32_t status;
0097
0098     #define MAX_RESETS_PER_READ 1
0099     uint32_t num_resets = 0;
0100
0101     #define MAX_IDLE_TIME   (1 * HZ)
0102     unsigned long idle_endtime = jiffies + MAX_IDLE_TIME;
0103
0104     while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
0105
0106         /* Is RNG sane? If not, reset it. */
0107         status = ioread32(priv->base + RNG_INT_STATUS_OFFSET);
0108         if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
0109             RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
0110
0111             if (num_resets >= MAX_RESETS_PER_READ)
0112                 return max - num_remaining;
0113
0114             iproc_rng200_restart(priv->base);
0115             num_resets++;
0116         }
0117
0118         /* Are there any random numbers available? */
0119         if ((ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) &
0120                 RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
0121
0122             if (num_remaining >= sizeof(uint32_t)) {
0123                 /* Buffer has room to store entire word */
0124                 *(uint32_t *)buf = ioread32(priv->base +
0125                             RNG_FIFO_DATA_OFFSET);
0126                 buf += sizeof(uint32_t);
0127                 num_remaining -= sizeof(uint32_t);
0128             } else {
0129                 /* Buffer can only store partial word */
0130                 uint32_t rnd_number = ioread32(priv->base +
0131                             RNG_FIFO_DATA_OFFSET);
0132                 memcpy(buf, &rnd_number, num_remaining);
0133                 buf += num_remaining;
0134                 num_remaining = 0;
0135             }
0136
0137             /* Reset the IDLE timeout */
0138             idle_endtime = jiffies + MAX_IDLE_TIME;
0139         } else {
0140             if (!wait)
0141                 /* Cannot wait, return immediately */
0142                 return max - num_remaining;
0143
0144             /* Can wait, give others chance to run */
0145             usleep_range(min(num_remaining * 10, 500U), 500);
0146         }
0147     }
0148
0149     return max - num_remaining;
0150 }
0151
0152 static int iproc_rng200_init(struct hwrng *rng)
0153 {
0154     struct iproc_rng200_dev *priv = to_rng_priv(rng);
0155
0156     iproc_rng200_enable_set(priv->base, true);
0157
0158     return 0;
0159 }
0160
0161 static void iproc_rng200_cleanup(struct hwrng *rng)
0162 {
0163     struct iproc_rng200_dev *priv = to_rng_priv(rng);
0164
0165     iproc_rng200_enable_set(priv->base, false);
0166 }
0167
0168 static int iproc_rng200_probe(struct platform_device *pdev)
0169 {
0170     struct iproc_rng200_dev *priv;
0171     struct device *dev = &pdev->dev;
0172     int ret;
0173
0174     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0175     if (!priv)
0176         return -ENOMEM;
0177
0178     /* Map peripheral */
0179     priv->base = devm_platform_ioremap_resource(pdev, 0);
0180     if (IS_ERR(priv->base)) {
0181         dev_err(dev, "failed to remap rng regs\n");
0182         return PTR_ERR(priv->base);
0183     }
0184
0185     priv->rng.name = "iproc-rng200";
0186     priv->rng.read = iproc_rng200_read;
0187     priv->rng.init = iproc_rng200_init;
0188     priv->rng.cleanup = iproc_rng200_cleanup;
0189
0190     /* Register driver */
0191     ret = devm_hwrng_register(dev, &priv->rng);
0192     if (ret) {
0193         dev_err(dev, "hwrng registration failed\n");
0194         return ret;
0195     }
0196
0197     dev_info(dev, "hwrng registered\n");
0198
0199     return 0;
0200 }
0201
0202 static const struct of_device_id iproc_rng200_of_match[] = {
0203     { .compatible = "brcm,bcm2711-rng200", },
0204     { .compatible = "brcm,bcm7211-rng200", },
0205     { .compatible = "brcm,bcm7278-rng200", },
0206     { .compatible = "brcm,iproc-rng200", },
0207     {},
0208 };
0209 MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
0210
0211 static struct platform_driver iproc_rng200_driver = {
0212     .driver = {
0213         .name       = "iproc-rng200",
0214         .of_match_table = iproc_rng200_of_match,
0215     },
0216     .probe      = iproc_rng200_probe,
0217 };
0218 module_platform_driver(iproc_rng200_driver);
0219
0220 MODULE_AUTHOR("Broadcom");
0221 MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
0222 MODULE_LICENSE("GPL v2");