char/hw_random/exynos-trng.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * RNG driver for Exynos TRNGs
0004  *
0005  * Author: Łukasz Stelmach <l.stelmach@samsung.com>
0006  *
0007  * Copyright 2017 (c) Samsung Electronics Software, Inc.
0008  *
0009  * Based on the Exynos PRNG driver drivers/crypto/exynos-rng by
0010  * Krzysztof Kozłowski <krzk@kernel.org>
0011  */
0012
0013 #include <linux/clk.h>
0014 #include <linux/crypto.h>
0015 #include <linux/delay.h>
0016 #include <linux/err.h>
0017 #include <linux/hw_random.h>
0018 #include <linux/io.h>
0019 #include <linux/iopoll.h>
0020 #include <linux/kernel.h>
0021 #include <linux/module.h>
0022 #include <linux/mod_devicetable.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/pm_runtime.h>
0025
0026 #define EXYNOS_TRNG_CLKDIV         (0x0)
0027
0028 #define EXYNOS_TRNG_CTRL           (0x20)
0029 #define EXYNOS_TRNG_CTRL_RNGEN     BIT(31)
0030
0031 #define EXYNOS_TRNG_POST_CTRL      (0x30)
0032 #define EXYNOS_TRNG_ONLINE_CTRL    (0x40)
0033 #define EXYNOS_TRNG_ONLINE_STAT    (0x44)
0034 #define EXYNOS_TRNG_ONLINE_MAXCHI2 (0x48)
0035 #define EXYNOS_TRNG_FIFO_CTRL      (0x50)
0036 #define EXYNOS_TRNG_FIFO_0         (0x80)
0037 #define EXYNOS_TRNG_FIFO_1         (0x84)
0038 #define EXYNOS_TRNG_FIFO_2         (0x88)
0039 #define EXYNOS_TRNG_FIFO_3         (0x8c)
0040 #define EXYNOS_TRNG_FIFO_4         (0x90)
0041 #define EXYNOS_TRNG_FIFO_5         (0x94)
0042 #define EXYNOS_TRNG_FIFO_6         (0x98)
0043 #define EXYNOS_TRNG_FIFO_7         (0x9c)
0044 #define EXYNOS_TRNG_FIFO_LEN       (8)
0045 #define EXYNOS_TRNG_CLOCK_RATE     (500000)
0046
0047
0048 struct exynos_trng_dev {
0049     struct device    *dev;
0050     void __iomem     *mem;
0051     struct clk       *clk;
0052     struct hwrng rng;
0053 };
0054
0055 static int exynos_trng_do_read(struct hwrng *rng, void *data, size_t max,
0056                    bool wait)
0057 {
0058     struct exynos_trng_dev *trng;
0059     int val;
0060
0061     max = min_t(size_t, max, (EXYNOS_TRNG_FIFO_LEN * 4));
0062
0063     trng = (struct exynos_trng_dev *)rng->priv;
0064
0065     writel_relaxed(max * 8, trng->mem + EXYNOS_TRNG_FIFO_CTRL);
0066     val = readl_poll_timeout(trng->mem + EXYNOS_TRNG_FIFO_CTRL, val,
0067                  val == 0, 200, 1000000);
0068     if (val < 0)
0069         return val;
0070
0071     memcpy_fromio(data, trng->mem + EXYNOS_TRNG_FIFO_0, max);
0072
0073     return max;
0074 }
0075
0076 static int exynos_trng_init(struct hwrng *rng)
0077 {
0078     struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv;
0079     unsigned long sss_rate;
0080     u32 val;
0081
0082     sss_rate = clk_get_rate(trng->clk);
0083
0084     /*
0085      * For most TRNG circuits the clock frequency of under 500 kHz
0086      * is safe.
0087      */
0088     val = sss_rate / (EXYNOS_TRNG_CLOCK_RATE * 2);
0089     if (val > 0x7fff) {
0090         dev_err(trng->dev, "clock divider too large: %d", val);
0091         return -ERANGE;
0092     }
0093     val = val << 1;
0094     writel_relaxed(val, trng->mem + EXYNOS_TRNG_CLKDIV);
0095
0096     /* Enable the generator. */
0097     val = EXYNOS_TRNG_CTRL_RNGEN;
0098     writel_relaxed(val, trng->mem + EXYNOS_TRNG_CTRL);
0099
0100     /*
0101      * Disable post-processing. /dev/hwrng is supposed to deliver
0102      * unprocessed data.
0103      */
0104     writel_relaxed(0, trng->mem + EXYNOS_TRNG_POST_CTRL);
0105
0106     return 0;
0107 }
0108
0109 static int exynos_trng_probe(struct platform_device *pdev)
0110 {
0111     struct exynos_trng_dev *trng;
0112     int ret = -ENOMEM;
0113
0114     trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
0115     if (!trng)
0116         return ret;
0117
0118     trng->rng.name = devm_kstrdup(&pdev->dev, dev_name(&pdev->dev),
0119                       GFP_KERNEL);
0120     if (!trng->rng.name)
0121         return ret;
0122
0123     trng->rng.init = exynos_trng_init;
0124     trng->rng.read = exynos_trng_do_read;
0125     trng->rng.priv = (unsigned long) trng;
0126
0127     platform_set_drvdata(pdev, trng);
0128     trng->dev = &pdev->dev;
0129
0130     trng->mem = devm_platform_ioremap_resource(pdev, 0);
0131     if (IS_ERR(trng->mem))
0132         return PTR_ERR(trng->mem);
0133
0134     pm_runtime_enable(&pdev->dev);
0135     ret = pm_runtime_resume_and_get(&pdev->dev);
0136     if (ret < 0) {
0137         dev_err(&pdev->dev, "Could not get runtime PM.\n");
0138         goto err_pm_get;
0139     }
0140
0141     trng->clk = devm_clk_get(&pdev->dev, "secss");
0142     if (IS_ERR(trng->clk)) {
0143         ret = PTR_ERR(trng->clk);
0144         dev_err(&pdev->dev, "Could not get clock.\n");
0145         goto err_clock;
0146     }
0147
0148     ret = clk_prepare_enable(trng->clk);
0149     if (ret) {
0150         dev_err(&pdev->dev, "Could not enable the clk.\n");
0151         goto err_clock;
0152     }
0153
0154     ret = devm_hwrng_register(&pdev->dev, &trng->rng);
0155     if (ret) {
0156         dev_err(&pdev->dev, "Could not register hwrng device.\n");
0157         goto err_register;
0158     }
0159
0160     dev_info(&pdev->dev, "Exynos True Random Number Generator.\n");
0161
0162     return 0;
0163
0164 err_register:
0165     clk_disable_unprepare(trng->clk);
0166
0167 err_clock:
0168     pm_runtime_put_noidle(&pdev->dev);
0169
0170 err_pm_get:
0171     pm_runtime_disable(&pdev->dev);
0172
0173     return ret;
0174 }
0175
0176 static int exynos_trng_remove(struct platform_device *pdev)
0177 {
0178     struct exynos_trng_dev *trng =  platform_get_drvdata(pdev);
0179
0180     clk_disable_unprepare(trng->clk);
0181
0182     pm_runtime_put_sync(&pdev->dev);
0183     pm_runtime_disable(&pdev->dev);
0184
0185     return 0;
0186 }
0187
0188 static int __maybe_unused exynos_trng_suspend(struct device *dev)
0189 {
0190     pm_runtime_put_sync(dev);
0191
0192     return 0;
0193 }
0194
0195 static int __maybe_unused exynos_trng_resume(struct device *dev)
0196 {
0197     int ret;
0198
0199     ret = pm_runtime_resume_and_get(dev);
0200     if (ret < 0) {
0201         dev_err(dev, "Could not get runtime PM.\n");
0202         return ret;
0203     }
0204
0205     return 0;
0206 }
0207
0208 static SIMPLE_DEV_PM_OPS(exynos_trng_pm_ops, exynos_trng_suspend,
0209              exynos_trng_resume);
0210
0211 static const struct of_device_id exynos_trng_dt_match[] = {
0212     {
0213         .compatible = "samsung,exynos5250-trng",
0214     },
0215     { },
0216 };
0217 MODULE_DEVICE_TABLE(of, exynos_trng_dt_match);
0218
0219 static struct platform_driver exynos_trng_driver = {
0220     .driver = {
0221         .name = "exynos-trng",
0222         .pm = &exynos_trng_pm_ops,
0223         .of_match_table = exynos_trng_dt_match,
0224     },
0225     .probe = exynos_trng_probe,
0226     .remove = exynos_trng_remove,
0227 };
0228
0229 module_platform_driver(exynos_trng_driver);
0230 MODULE_AUTHOR("Łukasz Stelmach");
0231 MODULE_DESCRIPTION("H/W TRNG driver for Exynos chips");
0232 MODULE_LICENSE("GPL v2");