char/hw_random/cctrng.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (C) 2019-2020 ARM Limited or its affiliates. */
0003
0004 #include <linux/bitops.h>
0005
0006 #define POWER_DOWN_ENABLE 0x01
0007 #define POWER_DOWN_DISABLE 0x00
0008
0009 /* hwrng quality: bits of true entropy per 1024 bits of input */
0010 #define CC_TRNG_QUALITY 1024
0011
0012 /* CryptoCell TRNG HW definitions */
0013 #define CC_TRNG_NUM_OF_ROSCS    4
0014 /* The number of words generated in the entropy holding register (EHR)
0015  * 6 words (192 bit) according to HW implementation
0016  */
0017 #define CC_TRNG_EHR_IN_WORDS    6
0018 #define CC_TRNG_EHR_IN_BITS (CC_TRNG_EHR_IN_WORDS * BITS_PER_TYPE(u32))
0019
0020 #define CC_HOST_RNG_IRQ_MASK BIT(CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT)
0021
0022 /* RNG interrupt mask */
0023 #define CC_RNG_INT_MASK (BIT(CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT) | \
0024              BIT(CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT) | \
0025              BIT(CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT) | \
0026              BIT(CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT) | \
0027              BIT(CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT))
0028
0029 // --------------------------------------
0030 // BLOCK: RNG
0031 // --------------------------------------
0032 #define CC_RNG_IMR_REG_OFFSET   0x0100UL
0033 #define CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT 0x0UL
0034 #define CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT  0x1UL
0035 #define CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT 0x2UL
0036 #define CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT    0x3UL
0037 #define CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT  0x4UL
0038 #define CC_RNG_ISR_REG_OFFSET   0x0104UL
0039 #define CC_RNG_ISR_EHR_VALID_BIT_SHIFT  0x0UL
0040 #define CC_RNG_ISR_EHR_VALID_BIT_SIZE   0x1UL
0041 #define CC_RNG_ISR_AUTOCORR_ERR_BIT_SHIFT   0x1UL
0042 #define CC_RNG_ISR_AUTOCORR_ERR_BIT_SIZE    0x1UL
0043 #define CC_RNG_ISR_CRNGT_ERR_BIT_SHIFT  0x2UL
0044 #define CC_RNG_ISR_CRNGT_ERR_BIT_SIZE   0x1UL
0045 #define CC_RNG_ISR_WATCHDOG_BIT_SHIFT   0x4UL
0046 #define CC_RNG_ISR_WATCHDOG_BIT_SIZE    0x1UL
0047 #define CC_RNG_ICR_REG_OFFSET   0x0108UL
0048 #define CC_TRNG_CONFIG_REG_OFFSET   0x010CUL
0049 #define CC_EHR_DATA_0_REG_OFFSET    0x0114UL
0050 #define CC_RND_SOURCE_ENABLE_REG_OFFSET 0x012CUL
0051 #define CC_SAMPLE_CNT1_REG_OFFSET   0x0130UL
0052 #define CC_TRNG_DEBUG_CONTROL_REG_OFFSET    0x0138UL
0053 #define CC_RNG_SW_RESET_REG_OFFSET  0x0140UL
0054 #define CC_RNG_CLK_ENABLE_REG_OFFSET    0x01C4UL
0055 #define CC_RNG_DMA_ENABLE_REG_OFFSET    0x01C8UL
0056 #define CC_RNG_WATCHDOG_VAL_REG_OFFSET  0x01D8UL
0057 // --------------------------------------
0058 // BLOCK: SEC_HOST_RGF
0059 // --------------------------------------
0060 #define CC_HOST_RGF_IRR_REG_OFFSET  0x0A00UL
0061 #define CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT   0xAUL
0062 #define CC_HOST_RGF_IMR_REG_OFFSET  0x0A04UL
0063 #define CC_HOST_RGF_ICR_REG_OFFSET  0x0A08UL
0064
0065 #define CC_HOST_POWER_DOWN_EN_REG_OFFSET    0x0A78UL
0066
0067 // --------------------------------------
0068 // BLOCK: NVM
0069 // --------------------------------------
0070 #define CC_NVM_IS_IDLE_REG_OFFSET   0x0F10UL
0071 #define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT  0x0UL
0072 #define CC_NVM_IS_IDLE_VALUE_BIT_SIZE   0x1UL