char/agp/parisc-agp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * HP Quicksilver AGP GART routines
0004  *
0005  * Copyright (c) 2006, Kyle McMartin <kyle@parisc-linux.org>
0006  *
0007  * Based on drivers/char/agpgart/hp-agp.c which is
0008  * (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P.
0009  *  Bjorn Helgaas <bjorn.helgaas@hp.com>
0010  */
0011
0012 #include <linux/module.h>
0013 #include <linux/pci.h>
0014 #include <linux/init.h>
0015 #include <linux/klist.h>
0016 #include <linux/agp_backend.h>
0017 #include <linux/log2.h>
0018 #include <linux/slab.h>
0019
0020 #include <asm/parisc-device.h>
0021 #include <asm/ropes.h>
0022
0023 #include "agp.h"
0024
0025 #define DRVNAME "quicksilver"
0026 #define DRVPFX  DRVNAME ": "
0027
0028 #define AGP8X_MODE_BIT      3
0029 #define AGP8X_MODE      (1 << AGP8X_MODE_BIT)
0030
0031 static unsigned long
0032 parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr,
0033                int type);
0034
0035 static struct _parisc_agp_info {
0036     void __iomem *ioc_regs;
0037     void __iomem *lba_regs;
0038
0039     int lba_cap_offset;
0040
0041     u64 *gatt;
0042     u64 gatt_entries;
0043
0044     u64 gart_base;
0045     u64 gart_size;
0046
0047     int io_page_size;
0048     int io_pages_per_kpage;
0049 } parisc_agp_info;
0050
0051 static struct gatt_mask parisc_agp_masks[] =
0052 {
0053         {
0054         .mask = SBA_PDIR_VALID_BIT,
0055         .type = 0
0056     }
0057 };
0058
0059 static struct aper_size_info_fixed parisc_agp_sizes[] =
0060 {
0061         {0, 0, 0},              /* filled in by parisc_agp_fetch_size() */
0062 };
0063
0064 static int
0065 parisc_agp_fetch_size(void)
0066 {
0067     int size;
0068
0069     size = parisc_agp_info.gart_size / MB(1);
0070     parisc_agp_sizes[0].size = size;
0071     agp_bridge->current_size = (void *) &parisc_agp_sizes[0];
0072
0073     return size;
0074 }
0075
0076 static int
0077 parisc_agp_configure(void)
0078 {
0079     struct _parisc_agp_info *info = &parisc_agp_info;
0080
0081     agp_bridge->gart_bus_addr = info->gart_base;
0082     agp_bridge->capndx = info->lba_cap_offset;
0083     agp_bridge->mode = readl(info->lba_regs+info->lba_cap_offset+PCI_AGP_STATUS);
0084
0085     return 0;
0086 }
0087
0088 static void
0089 parisc_agp_tlbflush(struct agp_memory *mem)
0090 {
0091     struct _parisc_agp_info *info = &parisc_agp_info;
0092
0093     writeq(info->gart_base | ilog2(info->gart_size), info->ioc_regs+IOC_PCOM);
0094     readq(info->ioc_regs+IOC_PCOM); /* flush */
0095 }
0096
0097 static int
0098 parisc_agp_create_gatt_table(struct agp_bridge_data *bridge)
0099 {
0100     struct _parisc_agp_info *info = &parisc_agp_info;
0101     int i;
0102
0103     for (i = 0; i < info->gatt_entries; i++) {
0104         info->gatt[i] = (unsigned long)agp_bridge->scratch_page;
0105     }
0106
0107     return 0;
0108 }
0109
0110 static int
0111 parisc_agp_free_gatt_table(struct agp_bridge_data *bridge)
0112 {
0113     struct _parisc_agp_info *info = &parisc_agp_info;
0114
0115     info->gatt[0] = SBA_AGPGART_COOKIE;
0116
0117     return 0;
0118 }
0119
0120 static int
0121 parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
0122 {
0123     struct _parisc_agp_info *info = &parisc_agp_info;
0124     int i, k;
0125     off_t j, io_pg_start;
0126     int io_pg_count;
0127
0128     if (type != mem->type ||
0129         agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type)) {
0130         return -EINVAL;
0131     }
0132
0133     io_pg_start = info->io_pages_per_kpage * pg_start;
0134     io_pg_count = info->io_pages_per_kpage * mem->page_count;
0135     if ((io_pg_start + io_pg_count) > info->gatt_entries) {
0136         return -EINVAL;
0137     }
0138
0139     j = io_pg_start;
0140     while (j < (io_pg_start + io_pg_count)) {
0141         if (info->gatt[j])
0142             return -EBUSY;
0143         j++;
0144     }
0145
0146     if (!mem->is_flushed) {
0147         global_cache_flush();
0148         mem->is_flushed = true;
0149     }
0150
0151     for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
0152         unsigned long paddr;
0153
0154         paddr = page_to_phys(mem->pages[i]);
0155         for (k = 0;
0156              k < info->io_pages_per_kpage;
0157              k++, j++, paddr += info->io_page_size) {
0158             info->gatt[j] =
0159                 parisc_agp_mask_memory(agp_bridge,
0160                     paddr, type);
0161         }
0162     }
0163
0164     agp_bridge->driver->tlb_flush(mem);
0165
0166     return 0;
0167 }
0168
0169 static int
0170 parisc_agp_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
0171 {
0172     struct _parisc_agp_info *info = &parisc_agp_info;
0173     int i, io_pg_start, io_pg_count;
0174
0175     if (type != mem->type ||
0176         agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type)) {
0177         return -EINVAL;
0178     }
0179
0180     io_pg_start = info->io_pages_per_kpage * pg_start;
0181     io_pg_count = info->io_pages_per_kpage * mem->page_count;
0182     for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
0183         info->gatt[i] = agp_bridge->scratch_page;
0184     }
0185
0186     agp_bridge->driver->tlb_flush(mem);
0187     return 0;
0188 }
0189
0190 static unsigned long
0191 parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr,
0192                int type)
0193 {
0194     return SBA_PDIR_VALID_BIT | addr;
0195 }
0196
0197 static void
0198 parisc_agp_enable(struct agp_bridge_data *bridge, u32 mode)
0199 {
0200     struct _parisc_agp_info *info = &parisc_agp_info;
0201     u32 command;
0202
0203     command = readl(info->lba_regs + info->lba_cap_offset + PCI_AGP_STATUS);
0204
0205     command = agp_collect_device_status(bridge, mode, command);
0206     command |= 0x00000100;
0207
0208     writel(command, info->lba_regs + info->lba_cap_offset + PCI_AGP_COMMAND);
0209
0210     agp_device_command(command, (mode & AGP8X_MODE) != 0);
0211 }
0212
0213 static const struct agp_bridge_driver parisc_agp_driver = {
0214     .owner          = THIS_MODULE,
0215     .size_type      = FIXED_APER_SIZE,
0216     .configure      = parisc_agp_configure,
0217     .fetch_size     = parisc_agp_fetch_size,
0218     .tlb_flush      = parisc_agp_tlbflush,
0219     .mask_memory        = parisc_agp_mask_memory,
0220     .masks          = parisc_agp_masks,
0221     .agp_enable     = parisc_agp_enable,
0222     .cache_flush        = global_cache_flush,
0223     .create_gatt_table  = parisc_agp_create_gatt_table,
0224     .free_gatt_table    = parisc_agp_free_gatt_table,
0225     .insert_memory      = parisc_agp_insert_memory,
0226     .remove_memory      = parisc_agp_remove_memory,
0227     .alloc_by_type      = agp_generic_alloc_by_type,
0228     .free_by_type       = agp_generic_free_by_type,
0229     .agp_alloc_page     = agp_generic_alloc_page,
0230     .agp_alloc_pages    = agp_generic_alloc_pages,
0231     .agp_destroy_page   = agp_generic_destroy_page,
0232     .agp_destroy_pages  = agp_generic_destroy_pages,
0233     .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
0234     .cant_use_aperture  = true,
0235 };
0236
0237 static int __init
0238 agp_ioc_init(void __iomem *ioc_regs)
0239 {
0240     struct _parisc_agp_info *info = &parisc_agp_info;
0241         u64 iova_base, *io_pdir, io_tlb_ps;
0242         int io_tlb_shift;
0243
0244         printk(KERN_INFO DRVPFX "IO PDIR shared with sba_iommu\n");
0245
0246         info->ioc_regs = ioc_regs;
0247
0248         io_tlb_ps = readq(info->ioc_regs+IOC_TCNFG);
0249         switch (io_tlb_ps) {
0250         case 0: io_tlb_shift = 12; break;
0251         case 1: io_tlb_shift = 13; break;
0252         case 2: io_tlb_shift = 14; break;
0253         case 3: io_tlb_shift = 16; break;
0254         default:
0255                 printk(KERN_ERR DRVPFX "Invalid IOTLB page size "
0256                        "configuration 0x%llx\n", io_tlb_ps);
0257                 info->gatt = NULL;
0258                 info->gatt_entries = 0;
0259                 return -ENODEV;
0260         }
0261         info->io_page_size = 1 << io_tlb_shift;
0262         info->io_pages_per_kpage = PAGE_SIZE / info->io_page_size;
0263
0264         iova_base = readq(info->ioc_regs+IOC_IBASE) & ~0x1;
0265         info->gart_base = iova_base + PLUTO_IOVA_SIZE - PLUTO_GART_SIZE;
0266
0267         info->gart_size = PLUTO_GART_SIZE;
0268         info->gatt_entries = info->gart_size / info->io_page_size;
0269
0270         io_pdir = phys_to_virt(readq(info->ioc_regs+IOC_PDIR_BASE));
0271         info->gatt = &io_pdir[(PLUTO_IOVA_SIZE/2) >> PAGE_SHIFT];
0272
0273         if (info->gatt[0] != SBA_AGPGART_COOKIE) {
0274                 info->gatt = NULL;
0275                 info->gatt_entries = 0;
0276                 printk(KERN_ERR DRVPFX "No reserved IO PDIR entry found; "
0277                        "GART disabled\n");
0278                 return -ENODEV;
0279         }
0280
0281         return 0;
0282 }
0283
0284 static int __init
0285 lba_find_capability(int cap)
0286 {
0287     struct _parisc_agp_info *info = &parisc_agp_info;
0288         u16 status;
0289         u8 pos, id;
0290         int ttl = 48;
0291
0292         status = readw(info->lba_regs + PCI_STATUS);
0293         if (!(status & PCI_STATUS_CAP_LIST))
0294                 return 0;
0295         pos = readb(info->lba_regs + PCI_CAPABILITY_LIST);
0296         while (ttl-- && pos >= 0x40) {
0297                 pos &= ~3;
0298                 id = readb(info->lba_regs + pos + PCI_CAP_LIST_ID);
0299                 if (id == 0xff)
0300                         break;
0301                 if (id == cap)
0302                         return pos;
0303                 pos = readb(info->lba_regs + pos + PCI_CAP_LIST_NEXT);
0304         }
0305         return 0;
0306 }
0307
0308 static int __init
0309 agp_lba_init(void __iomem *lba_hpa)
0310 {
0311     struct _parisc_agp_info *info = &parisc_agp_info;
0312         int cap;
0313
0314     info->lba_regs = lba_hpa;
0315         info->lba_cap_offset = lba_find_capability(PCI_CAP_ID_AGP);
0316
0317         cap = readl(lba_hpa + info->lba_cap_offset) & 0xff;
0318         if (cap != PCI_CAP_ID_AGP) {
0319                 printk(KERN_ERR DRVPFX "Invalid capability ID 0x%02x at 0x%x\n",
0320                        cap, info->lba_cap_offset);
0321                 return -ENODEV;
0322         }
0323
0324         return 0;
0325 }
0326
0327 static int __init
0328 parisc_agp_setup(void __iomem *ioc_hpa, void __iomem *lba_hpa)
0329 {
0330     struct pci_dev *fake_bridge_dev = NULL;
0331     struct agp_bridge_data *bridge;
0332     int error = 0;
0333
0334     fake_bridge_dev = pci_alloc_dev(NULL);
0335     if (!fake_bridge_dev) {
0336         error = -ENOMEM;
0337         goto fail;
0338     }
0339
0340     error = agp_ioc_init(ioc_hpa);
0341     if (error)
0342         goto fail;
0343
0344     error = agp_lba_init(lba_hpa);
0345     if (error)
0346         goto fail;
0347
0348     bridge = agp_alloc_bridge();
0349     if (!bridge) {
0350         error = -ENOMEM;
0351         goto fail;
0352     }
0353     bridge->driver = &parisc_agp_driver;
0354
0355     fake_bridge_dev->vendor = PCI_VENDOR_ID_HP;
0356     fake_bridge_dev->device = PCI_DEVICE_ID_HP_PCIX_LBA;
0357     bridge->dev = fake_bridge_dev;
0358
0359     error = agp_add_bridge(bridge);
0360     if (error)
0361         goto fail;
0362     return 0;
0363
0364 fail:
0365     kfree(fake_bridge_dev);
0366     return error;
0367 }
0368
0369 static int __init
0370 find_quicksilver(struct device *dev, void *data)
0371 {
0372     struct parisc_device **lba = data;
0373     struct parisc_device *padev = to_parisc_device(dev);
0374
0375     if (IS_QUICKSILVER(padev))
0376         *lba = padev;
0377
0378     return 0;
0379 }
0380
0381 static int __init
0382 parisc_agp_init(void)
0383 {
0384     extern struct sba_device *sba_list;
0385
0386     int err = -1;
0387     struct parisc_device *sba = NULL, *lba = NULL;
0388     struct lba_device *lbadev = NULL;
0389
0390     if (!sba_list)
0391         goto out;
0392
0393     /* Find our parent Pluto */
0394     sba = sba_list->dev;
0395     if (!IS_PLUTO(sba)) {
0396         printk(KERN_INFO DRVPFX "No Pluto found, so no AGPGART for you.\n");
0397         goto out;
0398     }
0399
0400     /* Now search our Pluto for our precious AGP device... */
0401     device_for_each_child(&sba->dev, &lba, find_quicksilver);
0402
0403     if (!lba) {
0404         printk(KERN_INFO DRVPFX "No AGP devices found.\n");
0405         goto out;
0406     }
0407
0408     lbadev = parisc_get_drvdata(lba);
0409
0410     /* w00t, let's go find our cookies... */
0411     parisc_agp_setup(sba_list->ioc[0].ioc_hpa, lbadev->hba.base_addr);
0412
0413     return 0;
0414
0415 out:
0416     return err;
0417 }
0418
0419 module_init(parisc_agp_init);
0420
0421 MODULE_AUTHOR("Kyle McMartin <kyle@parisc-linux.org>");
0422 MODULE_LICENSE("GPL");