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0001 /*
0002  * For documentation on the i460 AGP interface, see Chapter 7 (AGP Subsystem) of
0003  * the "Intel 460GTX Chipset Software Developer's Manual":
0004  * http://www.intel.com/design/archives/itanium/downloads/248704.htm 
0005  */
0006 /*
0007  * 460GX support by Chris Ahna <christopher.j.ahna@intel.com>
0008  * Clean up & simplification by David Mosberger-Tang <davidm@hpl.hp.com>
0009  */
0010 #include <linux/module.h>
0011 #include <linux/pci.h>
0012 #include <linux/init.h>
0013 #include <linux/string.h>
0014 #include <linux/slab.h>
0015 #include <linux/agp_backend.h>
0016 #include <linux/log2.h>
0017 
0018 #include "agp.h"
0019 
0020 #define INTEL_I460_BAPBASE      0x98
0021 #define INTEL_I460_GXBCTL       0xa0
0022 #define INTEL_I460_AGPSIZ       0xa2
0023 #define INTEL_I460_ATTBASE      0xfe200000
0024 #define INTEL_I460_GATT_VALID       (1UL << 24)
0025 #define INTEL_I460_GATT_COHERENT    (1UL << 25)
0026 
0027 /*
0028  * The i460 can operate with large (4MB) pages, but there is no sane way to support this
0029  * within the current kernel/DRM environment, so we disable the relevant code for now.
0030  * See also comments in ia64_alloc_page()...
0031  */
0032 #define I460_LARGE_IO_PAGES     0
0033 
0034 #if I460_LARGE_IO_PAGES
0035 # define I460_IO_PAGE_SHIFT     i460.io_page_shift
0036 #else
0037 # define I460_IO_PAGE_SHIFT     12
0038 #endif
0039 
0040 #define I460_IOPAGES_PER_KPAGE      (PAGE_SIZE >> I460_IO_PAGE_SHIFT)
0041 #define I460_KPAGES_PER_IOPAGE      (1 << (I460_IO_PAGE_SHIFT - PAGE_SHIFT))
0042 #define I460_SRAM_IO_DISABLE        (1 << 4)
0043 #define I460_BAPBASE_ENABLE     (1 << 3)
0044 #define I460_AGPSIZ_MASK        0x7
0045 #define I460_4M_PS          (1 << 1)
0046 
0047 /* Control bits for Out-Of-GART coherency and Burst Write Combining */
0048 #define I460_GXBCTL_OOG     (1UL << 0)
0049 #define I460_GXBCTL_BWC     (1UL << 2)
0050 
0051 /*
0052  * gatt_table entries are 32-bits wide on the i460; the generic code ought to declare the
0053  * gatt_table and gatt_table_real pointers a "void *"...
0054  */
0055 #define RD_GATT(index)      readl((u32 *) i460.gatt + (index))
0056 #define WR_GATT(index, val) writel((val), (u32 *) i460.gatt + (index))
0057 /*
0058  * The 460 spec says we have to read the last location written to make sure that all
0059  * writes have taken effect
0060  */
0061 #define WR_FLUSH_GATT(index)    RD_GATT(index)
0062 
0063 static unsigned long i460_mask_memory (struct agp_bridge_data *bridge,
0064                        dma_addr_t addr, int type);
0065 
0066 static struct {
0067     void *gatt;             /* ioremap'd GATT area */
0068 
0069     /* i460 supports multiple GART page sizes, so GART pageshift is dynamic: */
0070     u8 io_page_shift;
0071 
0072     /* BIOS configures chipset to one of 2 possible apbase values: */
0073     u8 dynamic_apbase;
0074 
0075     /* structure for tracking partial use of 4MB GART pages: */
0076     struct lp_desc {
0077         unsigned long *alloced_map; /* bitmap of kernel-pages in use */
0078         int refcount;           /* number of kernel pages using the large page */
0079         u64 paddr;          /* physical address of large page */
0080         struct page *page;      /* page pointer */
0081     } *lp_desc;
0082 } i460;
0083 
0084 static const struct aper_size_info_8 i460_sizes[3] =
0085 {
0086     /*
0087      * The 32GB aperture is only available with a 4M GART page size.  Due to the
0088      * dynamic GART page size, we can't figure out page_order or num_entries until
0089      * runtime.
0090      */
0091     {32768, 0, 0, 4},
0092     {1024, 0, 0, 2},
0093     {256, 0, 0, 1}
0094 };
0095 
0096 static struct gatt_mask i460_masks[] =
0097 {
0098     {
0099       .mask = INTEL_I460_GATT_VALID | INTEL_I460_GATT_COHERENT,
0100       .type = 0
0101     }
0102 };
0103 
0104 static int i460_fetch_size (void)
0105 {
0106     int i;
0107     u8 temp;
0108     struct aper_size_info_8 *values;
0109 
0110     /* Determine the GART page size */
0111     pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &temp);
0112     i460.io_page_shift = (temp & I460_4M_PS) ? 22 : 12;
0113     pr_debug("i460_fetch_size: io_page_shift=%d\n", i460.io_page_shift);
0114 
0115     if (i460.io_page_shift != I460_IO_PAGE_SHIFT) {
0116         printk(KERN_ERR PFX
0117             "I/O (GART) page-size %luKB doesn't match expected "
0118                 "size %luKB\n",
0119             1UL << (i460.io_page_shift - 10),
0120             1UL << (I460_IO_PAGE_SHIFT));
0121         return 0;
0122     }
0123 
0124     values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
0125 
0126     pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
0127 
0128     /* Exit now if the IO drivers for the GART SRAMS are turned off */
0129     if (temp & I460_SRAM_IO_DISABLE) {
0130         printk(KERN_ERR PFX "GART SRAMS disabled on 460GX chipset\n");
0131         printk(KERN_ERR PFX "AGPGART operation not possible\n");
0132         return 0;
0133     }
0134 
0135     /* Make sure we don't try to create an 2 ^ 23 entry GATT */
0136     if ((i460.io_page_shift == 0) && ((temp & I460_AGPSIZ_MASK) == 4)) {
0137         printk(KERN_ERR PFX "We can't have a 32GB aperture with 4KB GART pages\n");
0138         return 0;
0139     }
0140 
0141     /* Determine the proper APBASE register */
0142     if (temp & I460_BAPBASE_ENABLE)
0143         i460.dynamic_apbase = INTEL_I460_BAPBASE;
0144     else
0145         i460.dynamic_apbase = AGP_APBASE;
0146 
0147     for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
0148         /*
0149          * Dynamically calculate the proper num_entries and page_order values for
0150          * the define aperture sizes. Take care not to shift off the end of
0151          * values[i].size.
0152          */
0153         values[i].num_entries = (values[i].size << 8) >> (I460_IO_PAGE_SHIFT - 12);
0154         values[i].page_order = ilog2((sizeof(u32)*values[i].num_entries) >> PAGE_SHIFT);
0155     }
0156 
0157     for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
0158         /* Neglect control bits when matching up size_value */
0159         if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) {
0160             agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
0161             agp_bridge->aperture_size_idx = i;
0162             return values[i].size;
0163         }
0164     }
0165 
0166     return 0;
0167 }
0168 
0169 /* There isn't anything to do here since 460 has no GART TLB. */
0170 static void i460_tlb_flush (struct agp_memory *mem)
0171 {
0172     return;
0173 }
0174 
0175 /*
0176  * This utility function is needed to prevent corruption of the control bits
0177  * which are stored along with the aperture size in 460's AGPSIZ register
0178  */
0179 static void i460_write_agpsiz (u8 size_value)
0180 {
0181     u8 temp;
0182 
0183     pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
0184     pci_write_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ,
0185                   ((temp & ~I460_AGPSIZ_MASK) | size_value));
0186 }
0187 
0188 static void i460_cleanup (void)
0189 {
0190     struct aper_size_info_8 *previous_size;
0191 
0192     previous_size = A_SIZE_8(agp_bridge->previous_size);
0193     i460_write_agpsiz(previous_size->size_value);
0194 
0195     if (I460_IO_PAGE_SHIFT > PAGE_SHIFT)
0196         kfree(i460.lp_desc);
0197 }
0198 
0199 static int i460_configure (void)
0200 {
0201     union {
0202         u32 small[2];
0203         u64 large;
0204     } temp;
0205     size_t size;
0206     u8 scratch;
0207     struct aper_size_info_8 *current_size;
0208 
0209     temp.large = 0;
0210 
0211     current_size = A_SIZE_8(agp_bridge->current_size);
0212     i460_write_agpsiz(current_size->size_value);
0213 
0214     /*
0215      * Do the necessary rigmarole to read all eight bytes of APBASE.
0216      * This has to be done since the AGP aperture can be above 4GB on
0217      * 460 based systems.
0218      */
0219     pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase, &(temp.small[0]));
0220     pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase + 4, &(temp.small[1]));
0221 
0222     /* Clear BAR control bits */
0223     agp_bridge->gart_bus_addr = temp.large & ~((1UL << 3) - 1);
0224 
0225     pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &scratch);
0226     pci_write_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL,
0227                   (scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC);
0228 
0229     /*
0230      * Initialize partial allocation trackers if a GART page is bigger than a kernel
0231      * page.
0232      */
0233     if (I460_IO_PAGE_SHIFT > PAGE_SHIFT) {
0234         size = current_size->num_entries * sizeof(i460.lp_desc[0]);
0235         i460.lp_desc = kzalloc(size, GFP_KERNEL);
0236         if (!i460.lp_desc)
0237             return -ENOMEM;
0238     }
0239     return 0;
0240 }
0241 
0242 static int i460_create_gatt_table (struct agp_bridge_data *bridge)
0243 {
0244     int page_order, num_entries, i;
0245     void *temp;
0246 
0247     /*
0248      * Load up the fixed address of the GART SRAMS which hold our GATT table.
0249      */
0250     temp = agp_bridge->current_size;
0251     page_order = A_SIZE_8(temp)->page_order;
0252     num_entries = A_SIZE_8(temp)->num_entries;
0253 
0254     i460.gatt = ioremap(INTEL_I460_ATTBASE, PAGE_SIZE << page_order);
0255     if (!i460.gatt) {
0256         printk(KERN_ERR PFX "ioremap failed\n");
0257         return -ENOMEM;
0258     }
0259 
0260     /* These are no good, the should be removed from the agp_bridge strucure... */
0261     agp_bridge->gatt_table_real = NULL;
0262     agp_bridge->gatt_table = NULL;
0263     agp_bridge->gatt_bus_addr = 0;
0264 
0265     for (i = 0; i < num_entries; ++i)
0266         WR_GATT(i, 0);
0267     WR_FLUSH_GATT(i - 1);
0268     return 0;
0269 }
0270 
0271 static int i460_free_gatt_table (struct agp_bridge_data *bridge)
0272 {
0273     int num_entries, i;
0274     void *temp;
0275 
0276     temp = agp_bridge->current_size;
0277 
0278     num_entries = A_SIZE_8(temp)->num_entries;
0279 
0280     for (i = 0; i < num_entries; ++i)
0281         WR_GATT(i, 0);
0282     WR_FLUSH_GATT(num_entries - 1);
0283 
0284     iounmap(i460.gatt);
0285     return 0;
0286 }
0287 
0288 /*
0289  * The following functions are called when the I/O (GART) page size is smaller than
0290  * PAGE_SIZE.
0291  */
0292 
0293 static int i460_insert_memory_small_io_page (struct agp_memory *mem,
0294                 off_t pg_start, int type)
0295 {
0296     unsigned long paddr, io_pg_start, io_page_size;
0297     int i, j, k, num_entries;
0298     void *temp;
0299 
0300     pr_debug("i460_insert_memory_small_io_page(mem=%p, pg_start=%ld, type=%d, paddr0=0x%lx)\n",
0301          mem, pg_start, type, page_to_phys(mem->pages[0]));
0302 
0303     if (type >= AGP_USER_TYPES || mem->type >= AGP_USER_TYPES)
0304         return -EINVAL;
0305 
0306     io_pg_start = I460_IOPAGES_PER_KPAGE * pg_start;
0307 
0308     temp = agp_bridge->current_size;
0309     num_entries = A_SIZE_8(temp)->num_entries;
0310 
0311     if ((io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count) > num_entries) {
0312         printk(KERN_ERR PFX "Looks like we're out of AGP memory\n");
0313         return -EINVAL;
0314     }
0315 
0316     j = io_pg_start;
0317     while (j < (io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count)) {
0318         if (!PGE_EMPTY(agp_bridge, RD_GATT(j))) {
0319             pr_debug("i460_insert_memory_small_io_page: GATT[%d]=0x%x is busy\n",
0320                  j, RD_GATT(j));
0321             return -EBUSY;
0322         }
0323         j++;
0324     }
0325 
0326     io_page_size = 1UL << I460_IO_PAGE_SHIFT;
0327     for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
0328         paddr = page_to_phys(mem->pages[i]);
0329         for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size)
0330             WR_GATT(j, i460_mask_memory(agp_bridge, paddr, mem->type));
0331     }
0332     WR_FLUSH_GATT(j - 1);
0333     return 0;
0334 }
0335 
0336 static int i460_remove_memory_small_io_page(struct agp_memory *mem,
0337                 off_t pg_start, int type)
0338 {
0339     int i;
0340 
0341     pr_debug("i460_remove_memory_small_io_page(mem=%p, pg_start=%ld, type=%d)\n",
0342          mem, pg_start, type);
0343 
0344     pg_start = I460_IOPAGES_PER_KPAGE * pg_start;
0345 
0346     for (i = pg_start; i < (pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count); i++)
0347         WR_GATT(i, 0);
0348     WR_FLUSH_GATT(i - 1);
0349     return 0;
0350 }
0351 
0352 #if I460_LARGE_IO_PAGES
0353 
0354 /*
0355  * These functions are called when the I/O (GART) page size exceeds PAGE_SIZE.
0356  *
0357  * This situation is interesting since AGP memory allocations that are smaller than a
0358  * single GART page are possible.  The i460.lp_desc array tracks partial allocation of the
0359  * large GART pages to work around this issue.
0360  *
0361  * i460.lp_desc[pg_num].refcount tracks the number of kernel pages in use within GART page
0362  * pg_num.  i460.lp_desc[pg_num].paddr is the physical address of the large page and
0363  * i460.lp_desc[pg_num].alloced_map is a bitmap of kernel pages that are in use (allocated).
0364  */
0365 
0366 static int i460_alloc_large_page (struct lp_desc *lp)
0367 {
0368     unsigned long order = I460_IO_PAGE_SHIFT - PAGE_SHIFT;
0369     size_t map_size;
0370 
0371     lp->page = alloc_pages(GFP_KERNEL, order);
0372     if (!lp->page) {
0373         printk(KERN_ERR PFX "Couldn't alloc 4M GART page...\n");
0374         return -ENOMEM;
0375     }
0376 
0377     map_size = ((I460_KPAGES_PER_IOPAGE + BITS_PER_LONG - 1) & -BITS_PER_LONG)/8;
0378     lp->alloced_map = kzalloc(map_size, GFP_KERNEL);
0379     if (!lp->alloced_map) {
0380         __free_pages(lp->page, order);
0381         printk(KERN_ERR PFX "Out of memory, we're in trouble...\n");
0382         return -ENOMEM;
0383     }
0384 
0385     lp->paddr = page_to_phys(lp->page);
0386     lp->refcount = 0;
0387     atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
0388     return 0;
0389 }
0390 
0391 static void i460_free_large_page (struct lp_desc *lp)
0392 {
0393     kfree(lp->alloced_map);
0394     lp->alloced_map = NULL;
0395 
0396     __free_pages(lp->page, I460_IO_PAGE_SHIFT - PAGE_SHIFT);
0397     atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
0398 }
0399 
0400 static int i460_insert_memory_large_io_page (struct agp_memory *mem,
0401                 off_t pg_start, int type)
0402 {
0403     int i, start_offset, end_offset, idx, pg, num_entries;
0404     struct lp_desc *start, *end, *lp;
0405     void *temp;
0406 
0407     if (type >= AGP_USER_TYPES || mem->type >= AGP_USER_TYPES)
0408         return -EINVAL;
0409 
0410     temp = agp_bridge->current_size;
0411     num_entries = A_SIZE_8(temp)->num_entries;
0412 
0413     /* Figure out what pg_start means in terms of our large GART pages */
0414     start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
0415     end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
0416     start_offset = pg_start % I460_KPAGES_PER_IOPAGE;
0417     end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;
0418 
0419     if (end > i460.lp_desc + num_entries) {
0420         printk(KERN_ERR PFX "Looks like we're out of AGP memory\n");
0421         return -EINVAL;
0422     }
0423 
0424     /* Check if the requested region of the aperture is free */
0425     for (lp = start; lp <= end; ++lp) {
0426         if (!lp->alloced_map)
0427             continue;   /* OK, the entire large page is available... */
0428 
0429         for (idx = ((lp == start) ? start_offset : 0);
0430              idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
0431              idx++)
0432         {
0433             if (test_bit(idx, lp->alloced_map))
0434                 return -EBUSY;
0435         }
0436     }
0437 
0438     for (lp = start, i = 0; lp <= end; ++lp) {
0439         if (!lp->alloced_map) {
0440             /* Allocate new GART pages... */
0441             if (i460_alloc_large_page(lp) < 0)
0442                 return -ENOMEM;
0443             pg = lp - i460.lp_desc;
0444             WR_GATT(pg, i460_mask_memory(agp_bridge,
0445                              lp->paddr, 0));
0446             WR_FLUSH_GATT(pg);
0447         }
0448 
0449         for (idx = ((lp == start) ? start_offset : 0);
0450              idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
0451              idx++, i++)
0452         {
0453             mem->pages[i] = lp->page;
0454             __set_bit(idx, lp->alloced_map);
0455             ++lp->refcount;
0456         }
0457     }
0458     return 0;
0459 }
0460 
0461 static int i460_remove_memory_large_io_page (struct agp_memory *mem,
0462                 off_t pg_start, int type)
0463 {
0464     int i, pg, start_offset, end_offset, idx, num_entries;
0465     struct lp_desc *start, *end, *lp;
0466     void *temp;
0467 
0468     temp = agp_bridge->current_size;
0469     num_entries = A_SIZE_8(temp)->num_entries;
0470 
0471     /* Figure out what pg_start means in terms of our large GART pages */
0472     start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
0473     end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
0474     start_offset = pg_start % I460_KPAGES_PER_IOPAGE;
0475     end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;
0476 
0477     for (i = 0, lp = start; lp <= end; ++lp) {
0478         for (idx = ((lp == start) ? start_offset : 0);
0479              idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
0480              idx++, i++)
0481         {
0482             mem->pages[i] = NULL;
0483             __clear_bit(idx, lp->alloced_map);
0484             --lp->refcount;
0485         }
0486 
0487         /* Free GART pages if they are unused */
0488         if (lp->refcount == 0) {
0489             pg = lp - i460.lp_desc;
0490             WR_GATT(pg, 0);
0491             WR_FLUSH_GATT(pg);
0492             i460_free_large_page(lp);
0493         }
0494     }
0495     return 0;
0496 }
0497 
0498 /* Wrapper routines to call the approriate {small_io_page,large_io_page} function */
0499 
0500 static int i460_insert_memory (struct agp_memory *mem,
0501                 off_t pg_start, int type)
0502 {
0503     if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
0504         return i460_insert_memory_small_io_page(mem, pg_start, type);
0505     else
0506         return i460_insert_memory_large_io_page(mem, pg_start, type);
0507 }
0508 
0509 static int i460_remove_memory (struct agp_memory *mem,
0510                 off_t pg_start, int type)
0511 {
0512     if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
0513         return i460_remove_memory_small_io_page(mem, pg_start, type);
0514     else
0515         return i460_remove_memory_large_io_page(mem, pg_start, type);
0516 }
0517 
0518 /*
0519  * If the I/O (GART) page size is bigger than the kernel page size, we don't want to
0520  * allocate memory until we know where it is to be bound in the aperture (a
0521  * multi-kernel-page alloc might fit inside of an already allocated GART page).
0522  *
0523  * Let's just hope nobody counts on the allocated AGP memory being there before bind time
0524  * (I don't think current drivers do)...
0525  */
0526 static struct page *i460_alloc_page (struct agp_bridge_data *bridge)
0527 {
0528     void *page;
0529 
0530     if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) {
0531         page = agp_generic_alloc_page(agp_bridge);
0532     } else
0533         /* Returning NULL would cause problems */
0534         /* AK: really dubious code. */
0535         page = (void *)~0UL;
0536     return page;
0537 }
0538 
0539 static void i460_destroy_page (struct page *page, int flags)
0540 {
0541     if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) {
0542         agp_generic_destroy_page(page, flags);
0543     }
0544 }
0545 
0546 #endif /* I460_LARGE_IO_PAGES */
0547 
0548 static unsigned long i460_mask_memory (struct agp_bridge_data *bridge,
0549                        dma_addr_t addr, int type)
0550 {
0551     /* Make sure the returned address is a valid GATT entry */
0552     return bridge->driver->masks[0].mask
0553         | (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xfffff000) >> 12);
0554 }
0555 
0556 const struct agp_bridge_driver intel_i460_driver = {
0557     .owner          = THIS_MODULE,
0558     .aperture_sizes     = i460_sizes,
0559     .size_type      = U8_APER_SIZE,
0560     .num_aperture_sizes = 3,
0561     .configure      = i460_configure,
0562     .fetch_size     = i460_fetch_size,
0563     .cleanup        = i460_cleanup,
0564     .tlb_flush      = i460_tlb_flush,
0565     .mask_memory        = i460_mask_memory,
0566     .masks          = i460_masks,
0567     .agp_enable     = agp_generic_enable,
0568     .cache_flush        = global_cache_flush,
0569     .create_gatt_table  = i460_create_gatt_table,
0570     .free_gatt_table    = i460_free_gatt_table,
0571 #if I460_LARGE_IO_PAGES
0572     .insert_memory      = i460_insert_memory,
0573     .remove_memory      = i460_remove_memory,
0574     .agp_alloc_page     = i460_alloc_page,
0575     .agp_destroy_page   = i460_destroy_page,
0576 #else
0577     .insert_memory      = i460_insert_memory_small_io_page,
0578     .remove_memory      = i460_remove_memory_small_io_page,
0579     .agp_alloc_page     = agp_generic_alloc_page,
0580     .agp_alloc_pages    = agp_generic_alloc_pages,
0581     .agp_destroy_page   = agp_generic_destroy_page,
0582     .agp_destroy_pages  = agp_generic_destroy_pages,
0583 #endif
0584     .alloc_by_type      = agp_generic_alloc_by_type,
0585     .free_by_type       = agp_generic_free_by_type,
0586     .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
0587     .cant_use_aperture  = true,
0588 };
0589 
0590 static int agp_intel_i460_probe(struct pci_dev *pdev,
0591                 const struct pci_device_id *ent)
0592 {
0593     struct agp_bridge_data *bridge;
0594     u8 cap_ptr;
0595 
0596     cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
0597     if (!cap_ptr)
0598         return -ENODEV;
0599 
0600     bridge = agp_alloc_bridge();
0601     if (!bridge)
0602         return -ENOMEM;
0603 
0604     bridge->driver = &intel_i460_driver;
0605     bridge->dev = pdev;
0606     bridge->capndx = cap_ptr;
0607 
0608     printk(KERN_INFO PFX "Detected Intel 460GX chipset\n");
0609 
0610     pci_set_drvdata(pdev, bridge);
0611     return agp_add_bridge(bridge);
0612 }
0613 
0614 static void agp_intel_i460_remove(struct pci_dev *pdev)
0615 {
0616     struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
0617 
0618     agp_remove_bridge(bridge);
0619     agp_put_bridge(bridge);
0620 }
0621 
0622 static struct pci_device_id agp_intel_i460_pci_table[] = {
0623     {
0624     .class      = (PCI_CLASS_BRIDGE_HOST << 8),
0625     .class_mask = ~0,
0626     .vendor     = PCI_VENDOR_ID_INTEL,
0627     .device     = PCI_DEVICE_ID_INTEL_84460GX,
0628     .subvendor  = PCI_ANY_ID,
0629     .subdevice  = PCI_ANY_ID,
0630     },
0631     { }
0632 };
0633 
0634 MODULE_DEVICE_TABLE(pci, agp_intel_i460_pci_table);
0635 
0636 static struct pci_driver agp_intel_i460_pci_driver = {
0637     .name       = "agpgart-intel-i460",
0638     .id_table   = agp_intel_i460_pci_table,
0639     .probe      = agp_intel_i460_probe,
0640     .remove     = agp_intel_i460_remove,
0641 };
0642 
0643 static int __init agp_intel_i460_init(void)
0644 {
0645     if (agp_off)
0646         return -EINVAL;
0647     return pci_register_driver(&agp_intel_i460_pci_driver);
0648 }
0649 
0650 static void __exit agp_intel_i460_cleanup(void)
0651 {
0652     pci_unregister_driver(&agp_intel_i460_pci_driver);
0653 }
0654 
0655 module_init(agp_intel_i460_init);
0656 module_exit(agp_intel_i460_cleanup);
0657 
0658 MODULE_AUTHOR("Chris Ahna <Christopher.J.Ahna@intel.com>");
0659 MODULE_LICENSE("GPL and additional rights");
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