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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright 2001-2003 SuSE Labs.
0004  * Distributed under the GNU public license, v2.
0005  *
0006  * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
0007  * It also includes support for the AMD 8151 AGP bridge,
0008  * although it doesn't actually do much, as all the real
0009  * work is done in the northbridge(s).
0010  */
0011 
0012 #include <linux/module.h>
0013 #include <linux/pci.h>
0014 #include <linux/init.h>
0015 #include <linux/agp_backend.h>
0016 #include <linux/mmzone.h>
0017 #include <asm/page.h>       /* PAGE_SIZE */
0018 #include <asm/e820/api.h>
0019 #include <asm/amd_nb.h>
0020 #include <asm/gart.h>
0021 #include "agp.h"
0022 
0023 /* NVIDIA K8 registers */
0024 #define NVIDIA_X86_64_0_APBASE      0x10
0025 #define NVIDIA_X86_64_1_APBASE1     0x50
0026 #define NVIDIA_X86_64_1_APLIMIT1    0x54
0027 #define NVIDIA_X86_64_1_APSIZE      0xa8
0028 #define NVIDIA_X86_64_1_APBASE2     0xd8
0029 #define NVIDIA_X86_64_1_APLIMIT2    0xdc
0030 
0031 /* ULi K8 registers */
0032 #define ULI_X86_64_BASE_ADDR        0x10
0033 #define ULI_X86_64_HTT_FEA_REG      0x50
0034 #define ULI_X86_64_ENU_SCR_REG      0x54
0035 
0036 static struct resource *aperture_resource;
0037 static bool __initdata agp_try_unsupported = 1;
0038 static int agp_bridges_found;
0039 
0040 static void amd64_tlbflush(struct agp_memory *temp)
0041 {
0042     amd_flush_garts();
0043 }
0044 
0045 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
0046 {
0047     int i, j, num_entries;
0048     long long tmp;
0049     int mask_type;
0050     struct agp_bridge_data *bridge = mem->bridge;
0051     u32 pte;
0052 
0053     num_entries = agp_num_entries();
0054 
0055     if (type != mem->type)
0056         return -EINVAL;
0057     mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
0058     if (mask_type != 0)
0059         return -EINVAL;
0060 
0061 
0062     /* Make sure we can fit the range in the gatt table. */
0063     /* FIXME: could wrap */
0064     if (((unsigned long)pg_start + mem->page_count) > num_entries)
0065         return -EINVAL;
0066 
0067     j = pg_start;
0068 
0069     /* gatt table should be empty. */
0070     while (j < (pg_start + mem->page_count)) {
0071         if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
0072             return -EBUSY;
0073         j++;
0074     }
0075 
0076     if (!mem->is_flushed) {
0077         global_cache_flush();
0078         mem->is_flushed = true;
0079     }
0080 
0081     for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
0082         tmp = agp_bridge->driver->mask_memory(agp_bridge,
0083                               page_to_phys(mem->pages[i]),
0084                               mask_type);
0085 
0086         BUG_ON(tmp & 0xffffff0000000ffcULL);
0087         pte = (tmp & 0x000000ff00000000ULL) >> 28;
0088         pte |=(tmp & 0x00000000fffff000ULL);
0089         pte |= GPTE_VALID | GPTE_COHERENT;
0090 
0091         writel(pte, agp_bridge->gatt_table+j);
0092         readl(agp_bridge->gatt_table+j);    /* PCI Posting. */
0093     }
0094     amd64_tlbflush(mem);
0095     return 0;
0096 }
0097 
0098 /*
0099  * This hack alters the order element according
0100  * to the size of a long. It sucks. I totally disown this, even
0101  * though it does appear to work for the most part.
0102  */
0103 static struct aper_size_info_32 amd64_aperture_sizes[7] =
0104 {
0105     {32,   8192,   3+(sizeof(long)/8), 0 },
0106     {64,   16384,  4+(sizeof(long)/8), 1<<1 },
0107     {128,  32768,  5+(sizeof(long)/8), 1<<2 },
0108     {256,  65536,  6+(sizeof(long)/8), 1<<1 | 1<<2 },
0109     {512,  131072, 7+(sizeof(long)/8), 1<<3 },
0110     {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
0111     {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
0112 };
0113 
0114 
0115 /*
0116  * Get the current Aperture size from the x86-64.
0117  * Note, that there may be multiple x86-64's, but we just return
0118  * the value from the first one we find. The set_size functions
0119  * keep the rest coherent anyway. Or at least should do.
0120  */
0121 static int amd64_fetch_size(void)
0122 {
0123     struct pci_dev *dev;
0124     int i;
0125     u32 temp;
0126     struct aper_size_info_32 *values;
0127 
0128     dev = node_to_amd_nb(0)->misc;
0129     if (dev==NULL)
0130         return 0;
0131 
0132     pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
0133     temp = (temp & 0xe);
0134     values = A_SIZE_32(amd64_aperture_sizes);
0135 
0136     for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
0137         if (temp == values[i].size_value) {
0138             agp_bridge->previous_size =
0139                 agp_bridge->current_size = (void *) (values + i);
0140 
0141             agp_bridge->aperture_size_idx = i;
0142             return values[i].size;
0143         }
0144     }
0145     return 0;
0146 }
0147 
0148 /*
0149  * In a multiprocessor x86-64 system, this function gets
0150  * called once for each CPU.
0151  */
0152 static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
0153 {
0154     u64 aperturebase;
0155     u32 tmp;
0156     u64 aper_base;
0157 
0158     /* Address to map to */
0159     pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp);
0160     aperturebase = (u64)tmp << 25;
0161     aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
0162 
0163     enable_gart_translation(hammer, gatt_table);
0164 
0165     return aper_base;
0166 }
0167 
0168 
0169 static const struct aper_size_info_32 amd_8151_sizes[7] =
0170 {
0171     {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
0172     {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
0173     {512,  131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
0174     {256,  65536,  6, 0x00000700 }, /* 1 1 1 0 0 0 */
0175     {128,  32768,  5, 0x00000720 }, /* 1 1 1 1 0 0 */
0176     {64,   16384,  4, 0x00000730 }, /* 1 1 1 1 1 0 */
0177     {32,   8192,   3, 0x00000738 }  /* 1 1 1 1 1 1 */
0178 };
0179 
0180 static int amd_8151_configure(void)
0181 {
0182     unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
0183     int i;
0184 
0185     if (!amd_nb_has_feature(AMD_NB_GART))
0186         return 0;
0187 
0188     /* Configure AGP regs in each x86-64 host bridge. */
0189     for (i = 0; i < amd_nb_num(); i++) {
0190         agp_bridge->gart_bus_addr =
0191             amd64_configure(node_to_amd_nb(i)->misc, gatt_bus);
0192     }
0193     amd_flush_garts();
0194     return 0;
0195 }
0196 
0197 
0198 static void amd64_cleanup(void)
0199 {
0200     u32 tmp;
0201     int i;
0202 
0203     if (!amd_nb_has_feature(AMD_NB_GART))
0204         return;
0205 
0206     for (i = 0; i < amd_nb_num(); i++) {
0207         struct pci_dev *dev = node_to_amd_nb(i)->misc;
0208         /* disable gart translation */
0209         pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
0210         tmp &= ~GARTEN;
0211         pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
0212     }
0213 }
0214 
0215 
0216 static const struct agp_bridge_driver amd_8151_driver = {
0217     .owner          = THIS_MODULE,
0218     .aperture_sizes     = amd_8151_sizes,
0219     .size_type      = U32_APER_SIZE,
0220     .num_aperture_sizes = 7,
0221     .needs_scratch_page = true,
0222     .configure      = amd_8151_configure,
0223     .fetch_size     = amd64_fetch_size,
0224     .cleanup        = amd64_cleanup,
0225     .tlb_flush      = amd64_tlbflush,
0226     .mask_memory        = agp_generic_mask_memory,
0227     .masks          = NULL,
0228     .agp_enable     = agp_generic_enable,
0229     .cache_flush        = global_cache_flush,
0230     .create_gatt_table  = agp_generic_create_gatt_table,
0231     .free_gatt_table    = agp_generic_free_gatt_table,
0232     .insert_memory      = amd64_insert_memory,
0233     .remove_memory      = agp_generic_remove_memory,
0234     .alloc_by_type      = agp_generic_alloc_by_type,
0235     .free_by_type       = agp_generic_free_by_type,
0236     .agp_alloc_page     = agp_generic_alloc_page,
0237     .agp_alloc_pages    = agp_generic_alloc_pages,
0238     .agp_destroy_page   = agp_generic_destroy_page,
0239     .agp_destroy_pages  = agp_generic_destroy_pages,
0240     .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
0241 };
0242 
0243 /* Some basic sanity checks for the aperture. */
0244 static int agp_aperture_valid(u64 aper, u32 size)
0245 {
0246     if (!aperture_valid(aper, size, 32*1024*1024))
0247         return 0;
0248 
0249     /* Request the Aperture. This catches cases when someone else
0250        already put a mapping in there - happens with some very broken BIOS
0251 
0252        Maybe better to use pci_assign_resource/pci_enable_device instead
0253        trusting the bridges? */
0254     if (!aperture_resource &&
0255         !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
0256         printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
0257         return 0;
0258     }
0259     return 1;
0260 }
0261 
0262 /*
0263  * W*s centric BIOS sometimes only set up the aperture in the AGP
0264  * bridge, not the northbridge. On AMD64 this is handled early
0265  * in aperture.c, but when IOMMU is not enabled or we run
0266  * on a 32bit kernel this needs to be redone.
0267  * Unfortunately it is impossible to fix the aperture here because it's too late
0268  * to allocate that much memory. But at least error out cleanly instead of
0269  * crashing.
0270  */
0271 static int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, u16 cap)
0272 {
0273     u64 aper, nb_aper;
0274     int order = 0;
0275     u32 nb_order, nb_base;
0276     u16 apsize;
0277 
0278     pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order);
0279     nb_order = (nb_order >> 1) & 7;
0280     pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
0281     nb_aper = (u64)nb_base << 25;
0282 
0283     /* Northbridge seems to contain crap. Try the AGP bridge. */
0284 
0285     pci_read_config_word(agp, cap+0x14, &apsize);
0286     if (apsize == 0xffff) {
0287         if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
0288             return 0;
0289         return -1;
0290     }
0291 
0292     apsize &= 0xfff;
0293     /* Some BIOS use weird encodings not in the AGPv3 table. */
0294     if (apsize & 0xff)
0295         apsize |= 0xf00;
0296     order = 7 - hweight16(apsize);
0297 
0298     aper = pci_bus_address(agp, AGP_APERTURE_BAR);
0299 
0300     /*
0301      * On some sick chips APSIZE is 0. This means it wants 4G
0302      * so let double check that order, and lets trust the AMD NB settings
0303      */
0304     if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) {
0305         dev_info(&agp->dev, "aperture size %u MB is not right, using settings from NB\n",
0306              32 << order);
0307         order = nb_order;
0308     }
0309 
0310     if (nb_order >= order) {
0311         if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
0312             return 0;
0313     }
0314 
0315     dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n",
0316          aper, 32 << order);
0317     if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
0318         return -1;
0319 
0320     gart_set_size_and_enable(nb, order);
0321     pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
0322 
0323     return 0;
0324 }
0325 
0326 static int cache_nbs(struct pci_dev *pdev, u32 cap_ptr)
0327 {
0328     int i;
0329 
0330     if (!amd_nb_num())
0331         return -ENODEV;
0332 
0333     if (!amd_nb_has_feature(AMD_NB_GART))
0334         return -ENODEV;
0335 
0336     i = 0;
0337     for (i = 0; i < amd_nb_num(); i++) {
0338         struct pci_dev *dev = node_to_amd_nb(i)->misc;
0339         if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
0340             dev_err(&dev->dev, "no usable aperture found\n");
0341 #ifdef __x86_64__
0342             /* should port this to i386 */
0343             dev_err(&dev->dev, "consider rebooting with iommu=memaper=2 to get a good aperture\n");
0344 #endif
0345             return -1;
0346         }
0347     }
0348     return 0;
0349 }
0350 
0351 /* Handle AMD 8151 quirks */
0352 static void amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
0353 {
0354     char *revstring;
0355 
0356     switch (pdev->revision) {
0357     case 0x01: revstring="A0"; break;
0358     case 0x02: revstring="A1"; break;
0359     case 0x11: revstring="B0"; break;
0360     case 0x12: revstring="B1"; break;
0361     case 0x13: revstring="B2"; break;
0362     case 0x14: revstring="B3"; break;
0363     default:   revstring="??"; break;
0364     }
0365 
0366     dev_info(&pdev->dev, "AMD 8151 AGP Bridge rev %s\n", revstring);
0367 
0368     /*
0369      * Work around errata.
0370      * Chips before B2 stepping incorrectly reporting v3.5
0371      */
0372     if (pdev->revision < 0x13) {
0373         dev_info(&pdev->dev, "correcting AGP revision (reports 3.5, is really 3.0)\n");
0374         bridge->major_version = 3;
0375         bridge->minor_version = 0;
0376     }
0377 }
0378 
0379 
0380 static const struct aper_size_info_32 uli_sizes[7] =
0381 {
0382     {256, 65536, 6, 10},
0383     {128, 32768, 5, 9},
0384     {64, 16384, 4, 8},
0385     {32, 8192, 3, 7},
0386     {16, 4096, 2, 6},
0387     {8, 2048, 1, 4},
0388     {4, 1024, 0, 3}
0389 };
0390 static int uli_agp_init(struct pci_dev *pdev)
0391 {
0392     u32 httfea,baseaddr,enuscr;
0393     struct pci_dev *dev1;
0394     int i, ret;
0395     unsigned size = amd64_fetch_size();
0396 
0397     dev_info(&pdev->dev, "setting up ULi AGP\n");
0398     dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0));
0399     if (dev1 == NULL) {
0400         dev_info(&pdev->dev, "can't find ULi secondary device\n");
0401         return -ENODEV;
0402     }
0403 
0404     for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
0405         if (uli_sizes[i].size == size)
0406             break;
0407 
0408     if (i == ARRAY_SIZE(uli_sizes)) {
0409         dev_info(&pdev->dev, "no ULi size found for %d\n", size);
0410         ret = -ENODEV;
0411         goto put;
0412     }
0413 
0414     /* shadow x86-64 registers into ULi registers */
0415     pci_read_config_dword (node_to_amd_nb(0)->misc, AMD64_GARTAPERTUREBASE,
0416                    &httfea);
0417 
0418     /* if x86-64 aperture base is beyond 4G, exit here */
0419     if ((httfea & 0x7fff) >> (32 - 25)) {
0420         ret = -ENODEV;
0421         goto put;
0422     }
0423 
0424     httfea = (httfea& 0x7fff) << 25;
0425 
0426     pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
0427     baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
0428     baseaddr|= httfea;
0429     pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
0430 
0431     enuscr= httfea+ (size * 1024 * 1024) - 1;
0432     pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
0433     pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
0434     ret = 0;
0435 put:
0436     pci_dev_put(dev1);
0437     return ret;
0438 }
0439 
0440 
0441 static const struct aper_size_info_32 nforce3_sizes[5] =
0442 {
0443     {512,  131072, 7, 0x00000000 },
0444     {256,  65536,  6, 0x00000008 },
0445     {128,  32768,  5, 0x0000000C },
0446     {64,   16384,  4, 0x0000000E },
0447     {32,   8192,   3, 0x0000000F }
0448 };
0449 
0450 /* Handle shadow device of the Nvidia NForce3 */
0451 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
0452 static int nforce3_agp_init(struct pci_dev *pdev)
0453 {
0454     u32 tmp, apbase, apbar, aplimit;
0455     struct pci_dev *dev1;
0456     int i, ret;
0457     unsigned size = amd64_fetch_size();
0458 
0459     dev_info(&pdev->dev, "setting up Nforce3 AGP\n");
0460 
0461     dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0));
0462     if (dev1 == NULL) {
0463         dev_info(&pdev->dev, "can't find Nforce3 secondary device\n");
0464         return -ENODEV;
0465     }
0466 
0467     for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
0468         if (nforce3_sizes[i].size == size)
0469             break;
0470 
0471     if (i == ARRAY_SIZE(nforce3_sizes)) {
0472         dev_info(&pdev->dev, "no NForce3 size found for %d\n", size);
0473         ret = -ENODEV;
0474         goto put;
0475     }
0476 
0477     pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
0478     tmp &= ~(0xf);
0479     tmp |= nforce3_sizes[i].size_value;
0480     pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
0481 
0482     /* shadow x86-64 registers into NVIDIA registers */
0483     pci_read_config_dword (node_to_amd_nb(0)->misc, AMD64_GARTAPERTUREBASE,
0484                    &apbase);
0485 
0486     /* if x86-64 aperture base is beyond 4G, exit here */
0487     if ( (apbase & 0x7fff) >> (32 - 25) ) {
0488         dev_info(&pdev->dev, "aperture base > 4G\n");
0489         ret = -ENODEV;
0490         goto put;
0491     }
0492 
0493     apbase = (apbase & 0x7fff) << 25;
0494 
0495     pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
0496     apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
0497     apbar |= apbase;
0498     pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
0499 
0500     aplimit = apbase + (size * 1024 * 1024) - 1;
0501     pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
0502     pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
0503     pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
0504     pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
0505 
0506     ret = 0;
0507 put:
0508     pci_dev_put(dev1);
0509 
0510     return ret;
0511 }
0512 
0513 static int agp_amd64_probe(struct pci_dev *pdev,
0514                const struct pci_device_id *ent)
0515 {
0516     struct agp_bridge_data *bridge;
0517     u8 cap_ptr;
0518     int err;
0519 
0520     /* The Highlander principle */
0521     if (agp_bridges_found)
0522         return -ENODEV;
0523 
0524     cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
0525     if (!cap_ptr)
0526         return -ENODEV;
0527 
0528     /* Could check for AGPv3 here */
0529 
0530     bridge = agp_alloc_bridge();
0531     if (!bridge)
0532         return -ENOMEM;
0533 
0534     if (pdev->vendor == PCI_VENDOR_ID_AMD &&
0535         pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
0536         amd8151_init(pdev, bridge);
0537     } else {
0538         dev_info(&pdev->dev, "AGP bridge [%04x/%04x]\n",
0539              pdev->vendor, pdev->device);
0540     }
0541 
0542     bridge->driver = &amd_8151_driver;
0543     bridge->dev = pdev;
0544     bridge->capndx = cap_ptr;
0545 
0546     /* Fill in the mode register */
0547     pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
0548 
0549     if (cache_nbs(pdev, cap_ptr) == -1) {
0550         agp_put_bridge(bridge);
0551         return -ENODEV;
0552     }
0553 
0554     if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
0555         int ret = nforce3_agp_init(pdev);
0556         if (ret) {
0557             agp_put_bridge(bridge);
0558             return ret;
0559         }
0560     }
0561 
0562     if (pdev->vendor == PCI_VENDOR_ID_AL) {
0563         int ret = uli_agp_init(pdev);
0564         if (ret) {
0565             agp_put_bridge(bridge);
0566             return ret;
0567         }
0568     }
0569 
0570     pci_set_drvdata(pdev, bridge);
0571     err = agp_add_bridge(bridge);
0572     if (err < 0)
0573         return err;
0574 
0575     agp_bridges_found++;
0576     return 0;
0577 }
0578 
0579 static void agp_amd64_remove(struct pci_dev *pdev)
0580 {
0581     struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
0582 
0583     release_mem_region(virt_to_phys(bridge->gatt_table_real),
0584                amd64_aperture_sizes[bridge->aperture_size_idx].size);
0585     agp_remove_bridge(bridge);
0586     agp_put_bridge(bridge);
0587 
0588     agp_bridges_found--;
0589 }
0590 
0591 #define agp_amd64_suspend NULL
0592 
0593 static int __maybe_unused agp_amd64_resume(struct device *dev)
0594 {
0595     struct pci_dev *pdev = to_pci_dev(dev);
0596 
0597     if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
0598         nforce3_agp_init(pdev);
0599 
0600     return amd_8151_configure();
0601 }
0602 
0603 static const struct pci_device_id agp_amd64_pci_table[] = {
0604     {
0605     .class      = (PCI_CLASS_BRIDGE_HOST << 8),
0606     .class_mask = ~0,
0607     .vendor     = PCI_VENDOR_ID_AMD,
0608     .device     = PCI_DEVICE_ID_AMD_8151_0,
0609     .subvendor  = PCI_ANY_ID,
0610     .subdevice  = PCI_ANY_ID,
0611     },
0612     /* ULi M1689 */
0613     {
0614     .class      = (PCI_CLASS_BRIDGE_HOST << 8),
0615     .class_mask = ~0,
0616     .vendor     = PCI_VENDOR_ID_AL,
0617     .device     = PCI_DEVICE_ID_AL_M1689,
0618     .subvendor  = PCI_ANY_ID,
0619     .subdevice  = PCI_ANY_ID,
0620     },
0621     /* VIA K8T800Pro */
0622     {
0623     .class      = (PCI_CLASS_BRIDGE_HOST << 8),
0624     .class_mask = ~0,
0625     .vendor     = PCI_VENDOR_ID_VIA,
0626     .device     = PCI_DEVICE_ID_VIA_K8T800PRO_0,
0627     .subvendor  = PCI_ANY_ID,
0628     .subdevice  = PCI_ANY_ID,
0629     },
0630     /* VIA K8T800 */
0631     {
0632     .class      = (PCI_CLASS_BRIDGE_HOST << 8),
0633     .class_mask = ~0,
0634     .vendor     = PCI_VENDOR_ID_VIA,
0635     .device     = PCI_DEVICE_ID_VIA_8385_0,
0636     .subvendor  = PCI_ANY_ID,
0637     .subdevice  = PCI_ANY_ID,
0638     },
0639     /* VIA K8M800 / K8N800 */
0640     {
0641     .class      = (PCI_CLASS_BRIDGE_HOST << 8),
0642     .class_mask = ~0,
0643     .vendor     = PCI_VENDOR_ID_VIA,
0644     .device     = PCI_DEVICE_ID_VIA_8380_0,
0645     .subvendor  = PCI_ANY_ID,
0646     .subdevice  = PCI_ANY_ID,
0647     },
0648     /* VIA K8M890 / K8N890 */
0649     {
0650     .class          = (PCI_CLASS_BRIDGE_HOST << 8),
0651     .class_mask     = ~0,
0652     .vendor         = PCI_VENDOR_ID_VIA,
0653     .device         = PCI_DEVICE_ID_VIA_VT3336,
0654     .subvendor      = PCI_ANY_ID,
0655     .subdevice      = PCI_ANY_ID,
0656     },
0657     /* VIA K8T890 */
0658     {
0659     .class      = (PCI_CLASS_BRIDGE_HOST << 8),
0660     .class_mask = ~0,
0661     .vendor     = PCI_VENDOR_ID_VIA,
0662     .device     = PCI_DEVICE_ID_VIA_3238_0,
0663     .subvendor  = PCI_ANY_ID,
0664     .subdevice  = PCI_ANY_ID,
0665     },
0666     /* VIA K8T800/K8M800/K8N800 */
0667     {
0668     .class      = (PCI_CLASS_BRIDGE_HOST << 8),
0669     .class_mask = ~0,
0670     .vendor     = PCI_VENDOR_ID_VIA,
0671     .device     = PCI_DEVICE_ID_VIA_838X_1,
0672     .subvendor  = PCI_ANY_ID,
0673     .subdevice  = PCI_ANY_ID,
0674     },
0675     /* NForce3 */
0676     {
0677     .class      = (PCI_CLASS_BRIDGE_HOST << 8),
0678     .class_mask = ~0,
0679     .vendor     = PCI_VENDOR_ID_NVIDIA,
0680     .device     = PCI_DEVICE_ID_NVIDIA_NFORCE3,
0681     .subvendor  = PCI_ANY_ID,
0682     .subdevice  = PCI_ANY_ID,
0683     },
0684     {
0685     .class      = (PCI_CLASS_BRIDGE_HOST << 8),
0686     .class_mask = ~0,
0687     .vendor     = PCI_VENDOR_ID_NVIDIA,
0688     .device     = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
0689     .subvendor  = PCI_ANY_ID,
0690     .subdevice  = PCI_ANY_ID,
0691     },
0692     /* SIS 755 */
0693     {
0694     .class      = (PCI_CLASS_BRIDGE_HOST << 8),
0695     .class_mask = ~0,
0696     .vendor     = PCI_VENDOR_ID_SI,
0697     .device     = PCI_DEVICE_ID_SI_755,
0698     .subvendor  = PCI_ANY_ID,
0699     .subdevice  = PCI_ANY_ID,
0700     },
0701     /* SIS 760 */
0702     {
0703     .class      = (PCI_CLASS_BRIDGE_HOST << 8),
0704     .class_mask = ~0,
0705     .vendor     = PCI_VENDOR_ID_SI,
0706     .device     = PCI_DEVICE_ID_SI_760,
0707     .subvendor  = PCI_ANY_ID,
0708     .subdevice  = PCI_ANY_ID,
0709     },
0710     /* ALI/ULI M1695 */
0711     {
0712     .class      = (PCI_CLASS_BRIDGE_HOST << 8),
0713     .class_mask = ~0,
0714     .vendor     = PCI_VENDOR_ID_AL,
0715     .device     = 0x1695,
0716     .subvendor  = PCI_ANY_ID,
0717     .subdevice  = PCI_ANY_ID,
0718     },
0719 
0720     { }
0721 };
0722 
0723 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
0724 
0725 static const struct pci_device_id agp_amd64_pci_promisc_table[] = {
0726     { PCI_DEVICE_CLASS(0, 0) },
0727     { }
0728 };
0729 
0730 static SIMPLE_DEV_PM_OPS(agp_amd64_pm_ops, agp_amd64_suspend, agp_amd64_resume);
0731 
0732 static struct pci_driver agp_amd64_pci_driver = {
0733     .name       = "agpgart-amd64",
0734     .id_table   = agp_amd64_pci_table,
0735     .probe      = agp_amd64_probe,
0736     .remove     = agp_amd64_remove,
0737     .driver.pm  = &agp_amd64_pm_ops,
0738 };
0739 
0740 
0741 /* Not static due to IOMMU code calling it early. */
0742 int __init agp_amd64_init(void)
0743 {
0744     int err = 0;
0745 
0746     if (agp_off)
0747         return -EINVAL;
0748 
0749     err = pci_register_driver(&agp_amd64_pci_driver);
0750     if (err < 0)
0751         return err;
0752 
0753     if (agp_bridges_found == 0) {
0754         if (!agp_try_unsupported && !agp_try_unsupported_boot) {
0755             printk(KERN_INFO PFX "No supported AGP bridge found.\n");
0756 #ifdef MODULE
0757             printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
0758 #else
0759             printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
0760 #endif
0761             pci_unregister_driver(&agp_amd64_pci_driver);
0762             return -ENODEV;
0763         }
0764 
0765         /* First check that we have at least one AMD64 NB */
0766         if (!amd_nb_num()) {
0767             pci_unregister_driver(&agp_amd64_pci_driver);
0768             return -ENODEV;
0769         }
0770 
0771         /* Look for any AGP bridge */
0772         agp_amd64_pci_driver.id_table = agp_amd64_pci_promisc_table;
0773         err = driver_attach(&agp_amd64_pci_driver.driver);
0774         if (err == 0 && agp_bridges_found == 0) {
0775             pci_unregister_driver(&agp_amd64_pci_driver);
0776             err = -ENODEV;
0777         }
0778     }
0779     return err;
0780 }
0781 
0782 static int __init agp_amd64_mod_init(void)
0783 {
0784 #ifndef MODULE
0785     if (gart_iommu_aperture)
0786         return agp_bridges_found ? 0 : -ENODEV;
0787 #endif
0788     return agp_amd64_init();
0789 }
0790 
0791 static void __exit agp_amd64_cleanup(void)
0792 {
0793 #ifndef MODULE
0794     if (gart_iommu_aperture)
0795         return;
0796 #endif
0797     if (aperture_resource)
0798         release_resource(aperture_resource);
0799     pci_unregister_driver(&agp_amd64_pci_driver);
0800 }
0801 
0802 module_init(agp_amd64_mod_init);
0803 module_exit(agp_amd64_cleanup);
0804 
0805 MODULE_AUTHOR("Dave Jones, Andi Kleen");
0806 module_param(agp_try_unsupported, bool, 0);
0807 MODULE_LICENSE("GPL");
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