drivers/bus/uniphier-system-bus.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
0004  */
0005
0006 #include <linux/io.h>
0007 #include <linux/log2.h>
0008 #include <linux/module.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/of_platform.h>
0012 #include <linux/platform_device.h>
0013
0014 /* System Bus Controller registers */
0015 #define UNIPHIER_SBC_BASE   0x100   /* base address of bank0 space */
0016 #define    UNIPHIER_SBC_BASE_BE     BIT(0)  /* bank_enable */
0017 #define UNIPHIER_SBC_CTRL0  0x200   /* timing parameter 0 of bank0 */
0018 #define UNIPHIER_SBC_CTRL1  0x204   /* timing parameter 1 of bank0 */
0019 #define UNIPHIER_SBC_CTRL2  0x208   /* timing parameter 2 of bank0 */
0020 #define UNIPHIER_SBC_CTRL3  0x20c   /* timing parameter 3 of bank0 */
0021 #define UNIPHIER_SBC_CTRL4  0x300   /* timing parameter 4 of bank0 */
0022
0023 #define UNIPHIER_SBC_STRIDE 0x10    /* register stride to next bank */
0024 #define UNIPHIER_SBC_NR_BANKS   8   /* number of banks (chip select) */
0025 #define UNIPHIER_SBC_BASE_DUMMY 0xffffffff  /* data to squash bank 0, 1 */
0026
0027 struct uniphier_system_bus_bank {
0028     u32 base;
0029     u32 end;
0030 };
0031
0032 struct uniphier_system_bus_priv {
0033     struct device *dev;
0034     void __iomem *membase;
0035     struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS];
0036 };
0037
0038 static int uniphier_system_bus_add_bank(struct uniphier_system_bus_priv *priv,
0039                     int bank, u32 addr, u64 paddr, u32 size)
0040 {
0041     u64 end, mask;
0042
0043     dev_dbg(priv->dev,
0044         "range found: bank = %d, addr = %08x, paddr = %08llx, size = %08x\n",
0045         bank, addr, paddr, size);
0046
0047     if (bank >= ARRAY_SIZE(priv->bank)) {
0048         dev_err(priv->dev, "unsupported bank number %d\n", bank);
0049         return -EINVAL;
0050     }
0051
0052     if (priv->bank[bank].base || priv->bank[bank].end) {
0053         dev_err(priv->dev,
0054             "range for bank %d has already been specified\n", bank);
0055         return -EINVAL;
0056     }
0057
0058     if (paddr > U32_MAX) {
0059         dev_err(priv->dev, "base address %llx is too high\n", paddr);
0060         return -EINVAL;
0061     }
0062
0063     end = paddr + size;
0064
0065     if (addr > paddr) {
0066         dev_err(priv->dev,
0067             "base %08x cannot be mapped to %08llx of parent\n",
0068             addr, paddr);
0069         return -EINVAL;
0070     }
0071     paddr -= addr;
0072
0073     paddr = round_down(paddr, 0x00020000);
0074     end = round_up(end, 0x00020000);
0075
0076     if (end > U32_MAX) {
0077         dev_err(priv->dev, "end address %08llx is too high\n", end);
0078         return -EINVAL;
0079     }
0080     mask = paddr ^ (end - 1);
0081     mask = roundup_pow_of_two(mask);
0082
0083     paddr = round_down(paddr, mask);
0084     end = round_up(end, mask);
0085
0086     priv->bank[bank].base = paddr;
0087     priv->bank[bank].end = end;
0088
0089     dev_dbg(priv->dev, "range added: bank = %d, addr = %08x, end = %08x\n",
0090         bank, priv->bank[bank].base, priv->bank[bank].end);
0091
0092     return 0;
0093 }
0094
0095 static int uniphier_system_bus_check_overlap(
0096                 const struct uniphier_system_bus_priv *priv)
0097 {
0098     int i, j;
0099
0100     for (i = 0; i < ARRAY_SIZE(priv->bank); i++) {
0101         for (j = i + 1; j < ARRAY_SIZE(priv->bank); j++) {
0102             if (priv->bank[i].end > priv->bank[j].base &&
0103                 priv->bank[i].base < priv->bank[j].end) {
0104                 dev_err(priv->dev,
0105                     "region overlap between bank%d and bank%d\n",
0106                     i, j);
0107                 return -EINVAL;
0108             }
0109         }
0110     }
0111
0112     return 0;
0113 }
0114
0115 static void uniphier_system_bus_check_boot_swap(
0116                     struct uniphier_system_bus_priv *priv)
0117 {
0118     void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE;
0119     int is_swapped;
0120
0121     is_swapped = !(readl(base_reg) & UNIPHIER_SBC_BASE_BE);
0122
0123     dev_dbg(priv->dev, "Boot Swap: %s\n", is_swapped ? "on" : "off");
0124
0125     /*
0126      * If BOOT_SWAP was asserted on power-on-reset, the CS0 and CS1 are
0127      * swapped.  In this case, bank0 and bank1 should be swapped as well.
0128      */
0129     if (is_swapped)
0130         swap(priv->bank[0], priv->bank[1]);
0131 }
0132
0133 static void uniphier_system_bus_set_reg(
0134                 const struct uniphier_system_bus_priv *priv)
0135 {
0136     void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE;
0137     u32 base, end, mask, val;
0138     int i;
0139
0140     for (i = 0; i < ARRAY_SIZE(priv->bank); i++) {
0141         base = priv->bank[i].base;
0142         end = priv->bank[i].end;
0143
0144         if (base == end) {
0145             /*
0146              * If SBC_BASE0 or SBC_BASE1 is set to zero, the access
0147              * to anywhere in the system bus space is routed to
0148              * bank 0 (if boot swap if off) or bank 1 (if boot swap
0149              * if on).  It means that CPUs cannot get access to
0150              * bank 2 or later.  In other words, bank 0/1 cannot
0151              * be disabled even if its bank_enable bits is cleared.
0152              * This seems odd, but it is how this hardware goes.
0153              * As a workaround, dummy data (0xffffffff) should be
0154              * set when the bank 0/1 is unused.  As for bank 2 and
0155              * later, they can be simply disable by clearing the
0156              * bank_enable bit.
0157              */
0158             if (i < 2)
0159                 val = UNIPHIER_SBC_BASE_DUMMY;
0160             else
0161                 val = 0;
0162         } else {
0163             mask = base ^ (end - 1);
0164
0165             val = base & 0xfffe0000;
0166             val |= (~mask >> 16) & 0xfffe;
0167             val |= UNIPHIER_SBC_BASE_BE;
0168         }
0169         dev_dbg(priv->dev, "SBC_BASE[%d] = 0x%08x\n", i, val);
0170
0171         writel(val, base_reg + UNIPHIER_SBC_STRIDE * i);
0172     }
0173 }
0174
0175 static int uniphier_system_bus_probe(struct platform_device *pdev)
0176 {
0177     struct device *dev = &pdev->dev;
0178     struct uniphier_system_bus_priv *priv;
0179     const __be32 *ranges;
0180     u32 cells, addr, size;
0181     u64 paddr;
0182     int pna, bank, rlen, rone, ret;
0183
0184     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0185     if (!priv)
0186         return -ENOMEM;
0187
0188     priv->membase = devm_platform_ioremap_resource(pdev, 0);
0189     if (IS_ERR(priv->membase))
0190         return PTR_ERR(priv->membase);
0191
0192     priv->dev = dev;
0193
0194     pna = of_n_addr_cells(dev->of_node);
0195
0196     ret = of_property_read_u32(dev->of_node, "#address-cells", &cells);
0197     if (ret) {
0198         dev_err(dev, "failed to get #address-cells\n");
0199         return ret;
0200     }
0201     if (cells != 2) {
0202         dev_err(dev, "#address-cells must be 2\n");
0203         return -EINVAL;
0204     }
0205
0206     ret = of_property_read_u32(dev->of_node, "#size-cells", &cells);
0207     if (ret) {
0208         dev_err(dev, "failed to get #size-cells\n");
0209         return ret;
0210     }
0211     if (cells != 1) {
0212         dev_err(dev, "#size-cells must be 1\n");
0213         return -EINVAL;
0214     }
0215
0216     ranges = of_get_property(dev->of_node, "ranges", &rlen);
0217     if (!ranges) {
0218         dev_err(dev, "failed to get ranges property\n");
0219         return -ENOENT;
0220     }
0221
0222     rlen /= sizeof(*ranges);
0223     rone = pna + 2;
0224
0225     for (; rlen >= rone; rlen -= rone) {
0226         bank = be32_to_cpup(ranges++);
0227         addr = be32_to_cpup(ranges++);
0228         paddr = of_translate_address(dev->of_node, ranges);
0229         if (paddr == OF_BAD_ADDR)
0230             return -EINVAL;
0231         ranges += pna;
0232         size = be32_to_cpup(ranges++);
0233
0234         ret = uniphier_system_bus_add_bank(priv, bank, addr,
0235                            paddr, size);
0236         if (ret)
0237             return ret;
0238     }
0239
0240     ret = uniphier_system_bus_check_overlap(priv);
0241     if (ret)
0242         return ret;
0243
0244     uniphier_system_bus_check_boot_swap(priv);
0245
0246     uniphier_system_bus_set_reg(priv);
0247
0248     platform_set_drvdata(pdev, priv);
0249
0250     /* Now, the bus is configured.  Populate platform_devices below it */
0251     return of_platform_default_populate(dev->of_node, NULL, dev);
0252 }
0253
0254 static int __maybe_unused uniphier_system_bus_resume(struct device *dev)
0255 {
0256     uniphier_system_bus_set_reg(dev_get_drvdata(dev));
0257
0258     return 0;
0259 }
0260
0261 static const struct dev_pm_ops uniphier_system_bus_pm_ops = {
0262     SET_SYSTEM_SLEEP_PM_OPS(NULL, uniphier_system_bus_resume)
0263 };
0264
0265 static const struct of_device_id uniphier_system_bus_match[] = {
0266     { .compatible = "socionext,uniphier-system-bus" },
0267     { /* sentinel */ }
0268 };
0269 MODULE_DEVICE_TABLE(of, uniphier_system_bus_match);
0270
0271 static struct platform_driver uniphier_system_bus_driver = {
0272     .probe      = uniphier_system_bus_probe,
0273     .driver = {
0274         .name   = "uniphier-system-bus",
0275         .of_match_table = uniphier_system_bus_match,
0276         .pm = &uniphier_system_bus_pm_ops,
0277     },
0278 };
0279 module_platform_driver(uniphier_system_bus_driver);
0280
0281 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
0282 MODULE_DESCRIPTION("UniPhier System Bus driver");
0283 MODULE_LICENSE("GPL");