drivers/bus/tegra-gmi.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for NVIDIA Generic Memory Interface
0004  *
0005  * Copyright (C) 2016 Host Mobility AB. All rights reserved.
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/of_device.h>
0013 #include <linux/pm_runtime.h>
0014 #include <linux/reset.h>
0015
0016 #include <soc/tegra/common.h>
0017
0018 #define TEGRA_GMI_CONFIG        0x00
0019 #define TEGRA_GMI_CONFIG_GO     BIT(31)
0020 #define TEGRA_GMI_BUS_WIDTH_32BIT   BIT(30)
0021 #define TEGRA_GMI_MUX_MODE      BIT(28)
0022 #define TEGRA_GMI_RDY_BEFORE_DATA   BIT(24)
0023 #define TEGRA_GMI_RDY_ACTIVE_HIGH   BIT(23)
0024 #define TEGRA_GMI_ADV_ACTIVE_HIGH   BIT(22)
0025 #define TEGRA_GMI_OE_ACTIVE_HIGH    BIT(21)
0026 #define TEGRA_GMI_CS_ACTIVE_HIGH    BIT(20)
0027 #define TEGRA_GMI_CS_SELECT(x)      ((x & 0x7) << 4)
0028
0029 #define TEGRA_GMI_TIMING0       0x10
0030 #define TEGRA_GMI_MUXED_WIDTH(x)    ((x & 0xf) << 12)
0031 #define TEGRA_GMI_HOLD_WIDTH(x)     ((x & 0xf) << 8)
0032 #define TEGRA_GMI_ADV_WIDTH(x)      ((x & 0xf) << 4)
0033 #define TEGRA_GMI_CE_WIDTH(x)       (x & 0xf)
0034
0035 #define TEGRA_GMI_TIMING1       0x14
0036 #define TEGRA_GMI_WE_WIDTH(x)       ((x & 0xff) << 16)
0037 #define TEGRA_GMI_OE_WIDTH(x)       ((x & 0xff) << 8)
0038 #define TEGRA_GMI_WAIT_WIDTH(x)     (x & 0xff)
0039
0040 #define TEGRA_GMI_MAX_CHIP_SELECT   8
0041
0042 struct tegra_gmi {
0043     struct device *dev;
0044     void __iomem *base;
0045     struct clk *clk;
0046     struct reset_control *rst;
0047
0048     u32 snor_config;
0049     u32 snor_timing0;
0050     u32 snor_timing1;
0051 };
0052
0053 static int tegra_gmi_enable(struct tegra_gmi *gmi)
0054 {
0055     int err;
0056
0057     pm_runtime_enable(gmi->dev);
0058     err = pm_runtime_resume_and_get(gmi->dev);
0059     if (err) {
0060         pm_runtime_disable(gmi->dev);
0061         return err;
0062     }
0063
0064     reset_control_assert(gmi->rst);
0065     usleep_range(2000, 4000);
0066     reset_control_deassert(gmi->rst);
0067
0068     writel(gmi->snor_timing0, gmi->base + TEGRA_GMI_TIMING0);
0069     writel(gmi->snor_timing1, gmi->base + TEGRA_GMI_TIMING1);
0070
0071     gmi->snor_config |= TEGRA_GMI_CONFIG_GO;
0072     writel(gmi->snor_config, gmi->base + TEGRA_GMI_CONFIG);
0073
0074     return 0;
0075 }
0076
0077 static void tegra_gmi_disable(struct tegra_gmi *gmi)
0078 {
0079     u32 config;
0080
0081     /* stop GMI operation */
0082     config = readl(gmi->base + TEGRA_GMI_CONFIG);
0083     config &= ~TEGRA_GMI_CONFIG_GO;
0084     writel(config, gmi->base + TEGRA_GMI_CONFIG);
0085
0086     reset_control_assert(gmi->rst);
0087
0088     pm_runtime_put_sync_suspend(gmi->dev);
0089     pm_runtime_force_suspend(gmi->dev);
0090 }
0091
0092 static int tegra_gmi_parse_dt(struct tegra_gmi *gmi)
0093 {
0094     struct device_node *child;
0095     u32 property, ranges[4];
0096     int err;
0097
0098     child = of_get_next_available_child(gmi->dev->of_node, NULL);
0099     if (!child) {
0100         dev_err(gmi->dev, "no child nodes found\n");
0101         return -ENODEV;
0102     }
0103
0104     /*
0105      * We currently only support one child device due to lack of
0106      * chip-select address decoding. Which means that we only have one
0107      * chip-select line from the GMI controller.
0108      */
0109     if (of_get_child_count(gmi->dev->of_node) > 1)
0110         dev_warn(gmi->dev, "only one child device is supported.");
0111
0112     if (of_property_read_bool(child, "nvidia,snor-data-width-32bit"))
0113         gmi->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT;
0114
0115     if (of_property_read_bool(child, "nvidia,snor-mux-mode"))
0116         gmi->snor_config |= TEGRA_GMI_MUX_MODE;
0117
0118     if (of_property_read_bool(child, "nvidia,snor-rdy-active-before-data"))
0119         gmi->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA;
0120
0121     if (of_property_read_bool(child, "nvidia,snor-rdy-active-high"))
0122         gmi->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH;
0123
0124     if (of_property_read_bool(child, "nvidia,snor-adv-active-high"))
0125         gmi->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH;
0126
0127     if (of_property_read_bool(child, "nvidia,snor-oe-active-high"))
0128         gmi->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH;
0129
0130     if (of_property_read_bool(child, "nvidia,snor-cs-active-high"))
0131         gmi->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH;
0132
0133     /* Decode the CS# */
0134     err = of_property_read_u32_array(child, "ranges", ranges, 4);
0135     if (err < 0) {
0136         /* Invalid binding */
0137         if (err == -EOVERFLOW) {
0138             dev_err(gmi->dev,
0139                 "failed to decode CS: invalid ranges length\n");
0140             goto error_cs;
0141         }
0142
0143         /*
0144          * If we reach here it means that the child node has an empty
0145          * ranges or it does not exist at all. Attempt to decode the
0146          * CS# from the reg property instead.
0147          */
0148         err = of_property_read_u32(child, "reg", &property);
0149         if (err < 0) {
0150             dev_err(gmi->dev,
0151                 "failed to decode CS: no reg property found\n");
0152             goto error_cs;
0153         }
0154     } else {
0155         property = ranges[1];
0156     }
0157
0158     /* Valid chip selects are CS0-CS7 */
0159     if (property >= TEGRA_GMI_MAX_CHIP_SELECT) {
0160         dev_err(gmi->dev, "invalid chip select: %d", property);
0161         err = -EINVAL;
0162         goto error_cs;
0163     }
0164
0165     gmi->snor_config |= TEGRA_GMI_CS_SELECT(property);
0166
0167     /* The default values that are provided below are reset values */
0168     if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property))
0169         gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property);
0170     else
0171         gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1);
0172
0173     if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property))
0174         gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property);
0175     else
0176         gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1);
0177
0178     if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property))
0179         gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property);
0180     else
0181         gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1);
0182
0183     if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property))
0184         gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property);
0185     else
0186         gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4);
0187
0188     if (!of_property_read_u32(child, "nvidia,snor-we-width", &property))
0189         gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property);
0190     else
0191         gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1);
0192
0193     if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property))
0194         gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property);
0195     else
0196         gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1);
0197
0198     if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property))
0199         gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property);
0200     else
0201         gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3);
0202
0203 error_cs:
0204     of_node_put(child);
0205     return err;
0206 }
0207
0208 static int tegra_gmi_probe(struct platform_device *pdev)
0209 {
0210     struct device *dev = &pdev->dev;
0211     struct tegra_gmi *gmi;
0212     struct resource *res;
0213     int err;
0214
0215     gmi = devm_kzalloc(dev, sizeof(*gmi), GFP_KERNEL);
0216     if (!gmi)
0217         return -ENOMEM;
0218
0219     platform_set_drvdata(pdev, gmi);
0220     gmi->dev = dev;
0221
0222     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0223     gmi->base = devm_ioremap_resource(dev, res);
0224     if (IS_ERR(gmi->base))
0225         return PTR_ERR(gmi->base);
0226
0227     gmi->clk = devm_clk_get(dev, "gmi");
0228     if (IS_ERR(gmi->clk)) {
0229         dev_err(dev, "can not get clock\n");
0230         return PTR_ERR(gmi->clk);
0231     }
0232
0233     gmi->rst = devm_reset_control_get(dev, "gmi");
0234     if (IS_ERR(gmi->rst)) {
0235         dev_err(dev, "can not get reset\n");
0236         return PTR_ERR(gmi->rst);
0237     }
0238
0239     err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
0240     if (err)
0241         return err;
0242
0243     err = tegra_gmi_parse_dt(gmi);
0244     if (err)
0245         return err;
0246
0247     err = tegra_gmi_enable(gmi);
0248     if (err < 0)
0249         return err;
0250
0251     err = of_platform_default_populate(dev->of_node, NULL, dev);
0252     if (err < 0) {
0253         dev_err(dev, "fail to create devices.\n");
0254         tegra_gmi_disable(gmi);
0255         return err;
0256     }
0257
0258     return 0;
0259 }
0260
0261 static int tegra_gmi_remove(struct platform_device *pdev)
0262 {
0263     struct tegra_gmi *gmi = platform_get_drvdata(pdev);
0264
0265     of_platform_depopulate(gmi->dev);
0266     tegra_gmi_disable(gmi);
0267
0268     return 0;
0269 }
0270
0271 static int __maybe_unused tegra_gmi_runtime_resume(struct device *dev)
0272 {
0273     struct tegra_gmi *gmi = dev_get_drvdata(dev);
0274     int err;
0275
0276     err = clk_prepare_enable(gmi->clk);
0277     if (err < 0) {
0278         dev_err(gmi->dev, "failed to enable clock: %d\n", err);
0279         return err;
0280     }
0281
0282     return 0;
0283 }
0284
0285 static int __maybe_unused tegra_gmi_runtime_suspend(struct device *dev)
0286 {
0287     struct tegra_gmi *gmi = dev_get_drvdata(dev);
0288
0289     clk_disable_unprepare(gmi->clk);
0290
0291     return 0;
0292 }
0293
0294 static const struct dev_pm_ops tegra_gmi_pm = {
0295     SET_RUNTIME_PM_OPS(tegra_gmi_runtime_suspend, tegra_gmi_runtime_resume,
0296                NULL)
0297 };
0298
0299 static const struct of_device_id tegra_gmi_id_table[] = {
0300     { .compatible = "nvidia,tegra20-gmi", },
0301     { .compatible = "nvidia,tegra30-gmi", },
0302     { }
0303 };
0304 MODULE_DEVICE_TABLE(of, tegra_gmi_id_table);
0305
0306 static struct platform_driver tegra_gmi_driver = {
0307     .probe = tegra_gmi_probe,
0308     .remove = tegra_gmi_remove,
0309     .driver = {
0310         .name       = "tegra-gmi",
0311         .of_match_table = tegra_gmi_id_table,
0312         .pm = &tegra_gmi_pm,
0313     },
0314 };
0315 module_platform_driver(tegra_gmi_driver);
0316
0317 MODULE_AUTHOR("Mirza Krak <mirza.krak@gmail.com");
0318 MODULE_DESCRIPTION("NVIDIA Tegra GMI Bus Driver");
0319 MODULE_LICENSE("GPL v2");