drivers/bus/qcom-ebi2.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Qualcomm External Bus Interface 2 (EBI2) driver
0004  * an older version of the Qualcomm Parallel Interface Controller (QPIC)
0005  *
0006  * Copyright (C) 2016 Linaro Ltd.
0007  *
0008  * Author: Linus Walleij <linus.walleij@linaro.org>
0009  *
0010  * See the device tree bindings for this block for more details on the
0011  * hardware.
0012  */
0013
0014 #include <linux/module.h>
0015 #include <linux/clk.h>
0016 #include <linux/err.h>
0017 #include <linux/io.h>
0018 #include <linux/of.h>
0019 #include <linux/of_platform.h>
0020 #include <linux/init.h>
0021 #include <linux/slab.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/bitops.h>
0024
0025 /*
0026  * CS0, CS1, CS4 and CS5 are two bits wide, CS2 and CS3 are one bit.
0027  */
0028 #define EBI2_CS0_ENABLE_MASK BIT(0)|BIT(1)
0029 #define EBI2_CS1_ENABLE_MASK BIT(2)|BIT(3)
0030 #define EBI2_CS2_ENABLE_MASK BIT(4)
0031 #define EBI2_CS3_ENABLE_MASK BIT(5)
0032 #define EBI2_CS4_ENABLE_MASK BIT(6)|BIT(7)
0033 #define EBI2_CS5_ENABLE_MASK BIT(8)|BIT(9)
0034 #define EBI2_CSN_MASK GENMASK(9, 0)
0035
0036 #define EBI2_XMEM_CFG 0x0000 /* Power management etc */
0037
0038 /*
0039  * SLOW CSn CFG
0040  *
0041  * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
0042  *             memory continues to drive the data bus after OE is de-asserted.
0043  *             Inserted when reading one CS and switching to another CS or read
0044  *             followed by write on the same CS. Valid values 0 thru 15.
0045  * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
0046  *             every write minimum 1. The data out is driven from the time WE is
0047  *             asserted until CS is asserted. With a hold of 1, the CS stays
0048  *             active for 1 extra cycle etc. Valid values 0 thru 15.
0049  * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
0050  *             write to a page or burst memory
0051  * Bits 15-8:  RD_DELTA initial latency for read cycles inserted for the first
0052  *             read to a page or burst memory
0053  * Bits 7-4:   WR_WAIT number of wait cycles for every write access, 0=1 cycle
0054  *             so 1 thru 16 cycles.
0055  * Bits 3-0:   RD_WAIT number of wait cycles for every read access, 0=1 cycle
0056  *             so 1 thru 16 cycles.
0057  */
0058 #define EBI2_XMEM_CS0_SLOW_CFG 0x0008
0059 #define EBI2_XMEM_CS1_SLOW_CFG 0x000C
0060 #define EBI2_XMEM_CS2_SLOW_CFG 0x0010
0061 #define EBI2_XMEM_CS3_SLOW_CFG 0x0014
0062 #define EBI2_XMEM_CS4_SLOW_CFG 0x0018
0063 #define EBI2_XMEM_CS5_SLOW_CFG 0x001C
0064
0065 #define EBI2_XMEM_RECOVERY_SHIFT    28
0066 #define EBI2_XMEM_WR_HOLD_SHIFT     24
0067 #define EBI2_XMEM_WR_DELTA_SHIFT    16
0068 #define EBI2_XMEM_RD_DELTA_SHIFT    8
0069 #define EBI2_XMEM_WR_WAIT_SHIFT     4
0070 #define EBI2_XMEM_RD_WAIT_SHIFT     0
0071
0072 /*
0073  * FAST CSn CFG
0074  * Bits 31-28: ?
0075  * Bits 27-24: RD_HOLD: the length in cycles of the first segment of a read
0076  *             transfer. For a single read trandfer this will be the time
0077  *             from CS assertion to OE assertion.
0078  * Bits 18-24: ?
0079  * Bits 17-16: ADV_OE_RECOVERY, the number of cycles elapsed before an OE
0080  *             assertion, with respect to the cycle where ADV is asserted.
0081  *             2 means 2 cycles between ADV and OE. Values 0, 1, 2 or 3.
0082  * Bits 5:     ADDR_HOLD_ENA, The address is held for an extra cycle to meet
0083  *             hold time requirements with ADV assertion.
0084  *
0085  * The manual mentions "write precharge cycles" and "precharge cycles".
0086  * We have not been able to figure out which bit fields these correspond to
0087  * in the hardware, or what valid values exist. The current hypothesis is that
0088  * this is something just used on the FAST chip selects. There is also a "byte
0089  * device enable" flag somewhere for 8bit memories.
0090  */
0091 #define EBI2_XMEM_CS0_FAST_CFG 0x0028
0092 #define EBI2_XMEM_CS1_FAST_CFG 0x002C
0093 #define EBI2_XMEM_CS2_FAST_CFG 0x0030
0094 #define EBI2_XMEM_CS3_FAST_CFG 0x0034
0095 #define EBI2_XMEM_CS4_FAST_CFG 0x0038
0096 #define EBI2_XMEM_CS5_FAST_CFG 0x003C
0097
0098 #define EBI2_XMEM_RD_HOLD_SHIFT     24
0099 #define EBI2_XMEM_ADV_OE_RECOVERY_SHIFT 16
0100 #define EBI2_XMEM_ADDR_HOLD_ENA_SHIFT   5
0101
0102 /**
0103  * struct cs_data - struct with info on a chipselect setting
0104  * @enable_mask: mask to enable the chipselect in the EBI2 config
0105  * @slow_cfg: offset to XMEMC slow CS config
0106  * @fast_cfg: offset to XMEMC fast CS config
0107  */
0108 struct cs_data {
0109     u32 enable_mask;
0110     u16 slow_cfg;
0111     u16 fast_cfg;
0112 };
0113
0114 static const struct cs_data cs_info[] = {
0115     {
0116         /* CS0 */
0117         .enable_mask = EBI2_CS0_ENABLE_MASK,
0118         .slow_cfg = EBI2_XMEM_CS0_SLOW_CFG,
0119         .fast_cfg = EBI2_XMEM_CS0_FAST_CFG,
0120     },
0121     {
0122         /* CS1 */
0123         .enable_mask = EBI2_CS1_ENABLE_MASK,
0124         .slow_cfg = EBI2_XMEM_CS1_SLOW_CFG,
0125         .fast_cfg = EBI2_XMEM_CS1_FAST_CFG,
0126     },
0127     {
0128         /* CS2 */
0129         .enable_mask = EBI2_CS2_ENABLE_MASK,
0130         .slow_cfg = EBI2_XMEM_CS2_SLOW_CFG,
0131         .fast_cfg = EBI2_XMEM_CS2_FAST_CFG,
0132     },
0133     {
0134         /* CS3 */
0135         .enable_mask = EBI2_CS3_ENABLE_MASK,
0136         .slow_cfg = EBI2_XMEM_CS3_SLOW_CFG,
0137         .fast_cfg = EBI2_XMEM_CS3_FAST_CFG,
0138     },
0139     {
0140         /* CS4 */
0141         .enable_mask = EBI2_CS4_ENABLE_MASK,
0142         .slow_cfg = EBI2_XMEM_CS4_SLOW_CFG,
0143         .fast_cfg = EBI2_XMEM_CS4_FAST_CFG,
0144     },
0145     {
0146         /* CS5 */
0147         .enable_mask = EBI2_CS5_ENABLE_MASK,
0148         .slow_cfg = EBI2_XMEM_CS5_SLOW_CFG,
0149         .fast_cfg = EBI2_XMEM_CS5_FAST_CFG,
0150     },
0151 };
0152
0153 /**
0154  * struct ebi2_xmem_prop - describes an XMEM config property
0155  * @prop: the device tree binding name
0156  * @max: maximum value for the property
0157  * @slowreg: true if this property is in the SLOW CS config register
0158  * else it is assumed to be in the FAST config register
0159  * @shift: the bit field start in the SLOW or FAST register for this
0160  * property
0161  */
0162 struct ebi2_xmem_prop {
0163     const char *prop;
0164     u32 max;
0165     bool slowreg;
0166     u16 shift;
0167 };
0168
0169 static const struct ebi2_xmem_prop xmem_props[] = {
0170     {
0171         .prop = "qcom,xmem-recovery-cycles",
0172         .max = 15,
0173         .slowreg = true,
0174         .shift = EBI2_XMEM_RECOVERY_SHIFT,
0175     },
0176     {
0177         .prop = "qcom,xmem-write-hold-cycles",
0178         .max = 15,
0179         .slowreg = true,
0180         .shift = EBI2_XMEM_WR_HOLD_SHIFT,
0181     },
0182     {
0183         .prop = "qcom,xmem-write-delta-cycles",
0184         .max = 255,
0185         .slowreg = true,
0186         .shift = EBI2_XMEM_WR_DELTA_SHIFT,
0187     },
0188     {
0189         .prop = "qcom,xmem-read-delta-cycles",
0190         .max = 255,
0191         .slowreg = true,
0192         .shift = EBI2_XMEM_RD_DELTA_SHIFT,
0193     },
0194     {
0195         .prop = "qcom,xmem-write-wait-cycles",
0196         .max = 15,
0197         .slowreg = true,
0198         .shift = EBI2_XMEM_WR_WAIT_SHIFT,
0199     },
0200     {
0201         .prop = "qcom,xmem-read-wait-cycles",
0202         .max = 15,
0203         .slowreg = true,
0204         .shift = EBI2_XMEM_RD_WAIT_SHIFT,
0205     },
0206     {
0207         .prop = "qcom,xmem-address-hold-enable",
0208         .max = 1, /* boolean prop */
0209         .slowreg = false,
0210         .shift = EBI2_XMEM_ADDR_HOLD_ENA_SHIFT,
0211     },
0212     {
0213         .prop = "qcom,xmem-adv-to-oe-recovery-cycles",
0214         .max = 3,
0215         .slowreg = false,
0216         .shift = EBI2_XMEM_ADV_OE_RECOVERY_SHIFT,
0217     },
0218     {
0219         .prop = "qcom,xmem-read-hold-cycles",
0220         .max = 15,
0221         .slowreg = false,
0222         .shift = EBI2_XMEM_RD_HOLD_SHIFT,
0223     },
0224 };
0225
0226 static void qcom_ebi2_setup_chipselect(struct device_node *np,
0227                        struct device *dev,
0228                        void __iomem *ebi2_base,
0229                        void __iomem *ebi2_xmem,
0230                        u32 csindex)
0231 {
0232     const struct cs_data *csd;
0233     u32 slowcfg, fastcfg;
0234     u32 val;
0235     int ret;
0236     int i;
0237
0238     csd = &cs_info[csindex];
0239     val = readl(ebi2_base);
0240     val |= csd->enable_mask;
0241     writel(val, ebi2_base);
0242     dev_dbg(dev, "enabled CS%u\n", csindex);
0243
0244     /* Next set up the XMEMC */
0245     slowcfg = 0;
0246     fastcfg = 0;
0247
0248     for (i = 0; i < ARRAY_SIZE(xmem_props); i++) {
0249         const struct ebi2_xmem_prop *xp = &xmem_props[i];
0250
0251         /* All are regular u32 values */
0252         ret = of_property_read_u32(np, xp->prop, &val);
0253         if (ret) {
0254             dev_dbg(dev, "could not read %s for CS%d\n",
0255                 xp->prop, csindex);
0256             continue;
0257         }
0258
0259         /* First check boolean props */
0260         if (xp->max == 1 && val) {
0261             if (xp->slowreg)
0262                 slowcfg |= BIT(xp->shift);
0263             else
0264                 fastcfg |= BIT(xp->shift);
0265             dev_dbg(dev, "set %s flag\n", xp->prop);
0266             continue;
0267         }
0268
0269         /* We're dealing with an u32 */
0270         if (val > xp->max) {
0271             dev_err(dev,
0272                 "too high value for %s: %u, capped at %u\n",
0273                 xp->prop, val, xp->max);
0274             val = xp->max;
0275         }
0276         if (xp->slowreg)
0277             slowcfg |= (val << xp->shift);
0278         else
0279             fastcfg |= (val << xp->shift);
0280         dev_dbg(dev, "set %s to %u\n", xp->prop, val);
0281     }
0282
0283     dev_info(dev, "CS%u: SLOW CFG 0x%08x, FAST CFG 0x%08x\n",
0284          csindex, slowcfg, fastcfg);
0285
0286     if (slowcfg)
0287         writel(slowcfg, ebi2_xmem + csd->slow_cfg);
0288     if (fastcfg)
0289         writel(fastcfg, ebi2_xmem + csd->fast_cfg);
0290 }
0291
0292 static int qcom_ebi2_probe(struct platform_device *pdev)
0293 {
0294     struct device_node *np = pdev->dev.of_node;
0295     struct device_node *child;
0296     struct device *dev = &pdev->dev;
0297     struct resource *res;
0298     void __iomem *ebi2_base;
0299     void __iomem *ebi2_xmem;
0300     struct clk *ebi2xclk;
0301     struct clk *ebi2clk;
0302     bool have_children = false;
0303     u32 val;
0304     int ret;
0305
0306     ebi2xclk = devm_clk_get(dev, "ebi2x");
0307     if (IS_ERR(ebi2xclk))
0308         return PTR_ERR(ebi2xclk);
0309
0310     ret = clk_prepare_enable(ebi2xclk);
0311     if (ret) {
0312         dev_err(dev, "could not enable EBI2X clk (%d)\n", ret);
0313         return ret;
0314     }
0315
0316     ebi2clk = devm_clk_get(dev, "ebi2");
0317     if (IS_ERR(ebi2clk)) {
0318         ret = PTR_ERR(ebi2clk);
0319         goto err_disable_2x_clk;
0320     }
0321
0322     ret = clk_prepare_enable(ebi2clk);
0323     if (ret) {
0324         dev_err(dev, "could not enable EBI2 clk\n");
0325         goto err_disable_2x_clk;
0326     }
0327
0328     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0329     ebi2_base = devm_ioremap_resource(dev, res);
0330     if (IS_ERR(ebi2_base)) {
0331         ret = PTR_ERR(ebi2_base);
0332         goto err_disable_clk;
0333     }
0334
0335     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0336     ebi2_xmem = devm_ioremap_resource(dev, res);
0337     if (IS_ERR(ebi2_xmem)) {
0338         ret = PTR_ERR(ebi2_xmem);
0339         goto err_disable_clk;
0340     }
0341
0342     /* Allegedly this turns the power save mode off */
0343     writel(0UL, ebi2_xmem + EBI2_XMEM_CFG);
0344
0345     /* Disable all chipselects */
0346     val = readl(ebi2_base);
0347     val &= ~EBI2_CSN_MASK;
0348     writel(val, ebi2_base);
0349
0350     /* Walk over the child nodes and see what chipselects we use */
0351     for_each_available_child_of_node(np, child) {
0352         u32 csindex;
0353
0354         /* Figure out the chipselect */
0355         ret = of_property_read_u32(child, "reg", &csindex);
0356         if (ret) {
0357             of_node_put(child);
0358             return ret;
0359         }
0360
0361         if (csindex > 5) {
0362             dev_err(dev,
0363                 "invalid chipselect %u, we only support 0-5\n",
0364                 csindex);
0365             continue;
0366         }
0367
0368         qcom_ebi2_setup_chipselect(child,
0369                        dev,
0370                        ebi2_base,
0371                        ebi2_xmem,
0372                        csindex);
0373
0374         /* We have at least one child */
0375         have_children = true;
0376     }
0377
0378     if (have_children)
0379         return of_platform_default_populate(np, NULL, dev);
0380     return 0;
0381
0382 err_disable_clk:
0383     clk_disable_unprepare(ebi2clk);
0384 err_disable_2x_clk:
0385     clk_disable_unprepare(ebi2xclk);
0386
0387     return ret;
0388 }
0389
0390 static const struct of_device_id qcom_ebi2_of_match[] = {
0391     { .compatible = "qcom,msm8660-ebi2", },
0392     { .compatible = "qcom,apq8060-ebi2", },
0393     { }
0394 };
0395
0396 static struct platform_driver qcom_ebi2_driver = {
0397     .probe = qcom_ebi2_probe,
0398     .driver = {
0399         .name = "qcom-ebi2",
0400         .of_match_table = qcom_ebi2_of_match,
0401     },
0402 };
0403 module_platform_driver(qcom_ebi2_driver);
0404 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
0405 MODULE_DESCRIPTION("Qualcomm EBI2 driver");
0406 MODULE_LICENSE("GPL");