drivers/bus/omap_l3_smx.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * OMAP3XXX L3 Interconnect Driver header
0004  *
0005  * Copyright (C) 2011 Texas Corporation
0006  *  Felipe Balbi <balbi@ti.com>
0007  *  Santosh Shilimkar <santosh.shilimkar@ti.com>
0008  *  sricharan <r.sricharan@ti.com>
0009  */
0010 #ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
0011 #define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
0012
0013 /* Register definitions. All 64-bit wide */
0014 #define L3_COMPONENT            0x000
0015 #define L3_CORE             0x018
0016 #define L3_AGENT_CONTROL        0x020
0017 #define L3_AGENT_STATUS         0x028
0018 #define L3_ERROR_LOG            0x058
0019
0020 #define L3_ERROR_LOG_MULTI      (1 << 31)
0021 #define L3_ERROR_LOG_SECONDARY      (1 << 30)
0022
0023 #define L3_ERROR_LOG_ADDR       0x060
0024
0025 /* Register definitions for Sideband Interconnect */
0026 #define L3_SI_CONTROL           0x020
0027 #define L3_SI_FLAG_STATUS_0     0x510
0028
0029 static const u64 shift = 1;
0030
0031 #define L3_STATUS_0_MPUIA_BRST      (shift << 0)
0032 #define L3_STATUS_0_MPUIA_RSP       (shift << 1)
0033 #define L3_STATUS_0_MPUIA_INBAND    (shift << 2)
0034 #define L3_STATUS_0_IVAIA_BRST      (shift << 6)
0035 #define L3_STATUS_0_IVAIA_RSP       (shift << 7)
0036 #define L3_STATUS_0_IVAIA_INBAND    (shift << 8)
0037 #define L3_STATUS_0_SGXIA_BRST      (shift << 9)
0038 #define L3_STATUS_0_SGXIA_RSP       (shift << 10)
0039 #define L3_STATUS_0_SGXIA_MERROR    (shift << 11)
0040 #define L3_STATUS_0_CAMIA_BRST      (shift << 12)
0041 #define L3_STATUS_0_CAMIA_RSP       (shift << 13)
0042 #define L3_STATUS_0_CAMIA_INBAND    (shift << 14)
0043 #define L3_STATUS_0_DISPIA_BRST     (shift << 15)
0044 #define L3_STATUS_0_DISPIA_RSP      (shift << 16)
0045 #define L3_STATUS_0_DMARDIA_BRST    (shift << 18)
0046 #define L3_STATUS_0_DMARDIA_RSP     (shift << 19)
0047 #define L3_STATUS_0_DMAWRIA_BRST    (shift << 21)
0048 #define L3_STATUS_0_DMAWRIA_RSP     (shift << 22)
0049 #define L3_STATUS_0_USBOTGIA_BRST   (shift << 24)
0050 #define L3_STATUS_0_USBOTGIA_RSP    (shift << 25)
0051 #define L3_STATUS_0_USBOTGIA_INBAND (shift << 26)
0052 #define L3_STATUS_0_USBHOSTIA_BRST  (shift << 27)
0053 #define L3_STATUS_0_USBHOSTIA_INBAND    (shift << 28)
0054 #define L3_STATUS_0_SMSTA_REQ       (shift << 48)
0055 #define L3_STATUS_0_GPMCTA_REQ      (shift << 49)
0056 #define L3_STATUS_0_OCMRAMTA_REQ    (shift << 50)
0057 #define L3_STATUS_0_OCMROMTA_REQ    (shift << 51)
0058 #define L3_STATUS_0_IVATA_REQ       (shift << 54)
0059 #define L3_STATUS_0_SGXTA_REQ       (shift << 55)
0060 #define L3_STATUS_0_SGXTA_SERROR    (shift << 56)
0061 #define L3_STATUS_0_GPMCTA_SERROR   (shift << 57)
0062 #define L3_STATUS_0_L4CORETA_REQ    (shift << 58)
0063 #define L3_STATUS_0_L4PERTA_REQ     (shift << 59)
0064 #define L3_STATUS_0_L4EMUTA_REQ     (shift << 60)
0065 #define L3_STATUS_0_MAD2DTA_REQ     (shift << 61)
0066
0067 #define L3_STATUS_0_TIMEOUT_MASK    (L3_STATUS_0_MPUIA_BRST     \
0068                     | L3_STATUS_0_MPUIA_RSP     \
0069                     | L3_STATUS_0_IVAIA_BRST    \
0070                     | L3_STATUS_0_IVAIA_RSP     \
0071                     | L3_STATUS_0_SGXIA_BRST    \
0072                     | L3_STATUS_0_SGXIA_RSP     \
0073                     | L3_STATUS_0_CAMIA_BRST    \
0074                     | L3_STATUS_0_CAMIA_RSP     \
0075                     | L3_STATUS_0_DISPIA_BRST   \
0076                     | L3_STATUS_0_DISPIA_RSP    \
0077                     | L3_STATUS_0_DMARDIA_BRST  \
0078                     | L3_STATUS_0_DMARDIA_RSP   \
0079                     | L3_STATUS_0_DMAWRIA_BRST  \
0080                     | L3_STATUS_0_DMAWRIA_RSP   \
0081                     | L3_STATUS_0_USBOTGIA_BRST \
0082                     | L3_STATUS_0_USBOTGIA_RSP  \
0083                     | L3_STATUS_0_USBHOSTIA_BRST    \
0084                     | L3_STATUS_0_SMSTA_REQ     \
0085                     | L3_STATUS_0_GPMCTA_REQ    \
0086                     | L3_STATUS_0_OCMRAMTA_REQ  \
0087                     | L3_STATUS_0_OCMROMTA_REQ  \
0088                     | L3_STATUS_0_IVATA_REQ     \
0089                     | L3_STATUS_0_SGXTA_REQ     \
0090                     | L3_STATUS_0_L4CORETA_REQ  \
0091                     | L3_STATUS_0_L4PERTA_REQ   \
0092                     | L3_STATUS_0_L4EMUTA_REQ   \
0093                     | L3_STATUS_0_MAD2DTA_REQ)
0094
0095 #define L3_SI_FLAG_STATUS_1     0x530
0096
0097 #define L3_STATUS_1_MPU_DATAIA      (1 << 0)
0098 #define L3_STATUS_1_DAPIA0      (1 << 3)
0099 #define L3_STATUS_1_DAPIA1      (1 << 4)
0100 #define L3_STATUS_1_IVAIA       (1 << 6)
0101
0102 #define L3_PM_ERROR_LOG         0x020
0103 #define L3_PM_CONTROL           0x028
0104 #define L3_PM_ERROR_CLEAR_SINGLE    0x030
0105 #define L3_PM_ERROR_CLEAR_MULTI     0x038
0106 #define L3_PM_REQ_INFO_PERMISSION(n)    (0x048 + (0x020 * n))
0107 #define L3_PM_READ_PERMISSION(n)    (0x050 + (0x020 * n))
0108 #define L3_PM_WRITE_PERMISSION(n)   (0x058 + (0x020 * n))
0109 #define L3_PM_ADDR_MATCH(n)     (0x060 + (0x020 * n))
0110
0111 /* L3 error log bit fields. Common for IA and TA */
0112 #define L3_ERROR_LOG_CODE       24
0113 #define L3_ERROR_LOG_INITID     8
0114 #define L3_ERROR_LOG_CMD        0
0115
0116 /* L3 agent status bit fields. */
0117 #define L3_AGENT_STATUS_CLEAR_IA    0x10000000
0118 #define L3_AGENT_STATUS_CLEAR_TA    0x01000000
0119
0120 #define OMAP34xx_IRQ_L3_APP     10
0121 #define L3_APPLICATION_ERROR        0x0
0122 #define L3_DEBUG_ERROR          0x1
0123
0124 enum omap3_l3_initiator_id {
0125     /* LCD has 1 ID */
0126     OMAP_L3_LCD = 29,
0127     /* SAD2D has 1 ID */
0128     OMAP_L3_SAD2D = 28,
0129     /* MPU has 5 IDs */
0130     OMAP_L3_IA_MPU_SS_1 = 27,
0131     OMAP_L3_IA_MPU_SS_2 = 26,
0132     OMAP_L3_IA_MPU_SS_3 = 25,
0133     OMAP_L3_IA_MPU_SS_4 = 24,
0134     OMAP_L3_IA_MPU_SS_5 = 23,
0135     /* IVA2.2 SS has 3 IDs*/
0136     OMAP_L3_IA_IVA_SS_1 = 22,
0137     OMAP_L3_IA_IVA_SS_2 = 21,
0138     OMAP_L3_IA_IVA_SS_3 = 20,
0139     /* IVA 2.2 SS DMA has 6 IDS */
0140     OMAP_L3_IA_IVA_SS_DMA_1 = 19,
0141     OMAP_L3_IA_IVA_SS_DMA_2 = 18,
0142     OMAP_L3_IA_IVA_SS_DMA_3 = 17,
0143     OMAP_L3_IA_IVA_SS_DMA_4 = 16,
0144     OMAP_L3_IA_IVA_SS_DMA_5 = 15,
0145     OMAP_L3_IA_IVA_SS_DMA_6 = 14,
0146     /* SGX has 1 ID */
0147     OMAP_L3_IA_SGX = 13,
0148     /* CAM has 3 ID */
0149     OMAP_L3_IA_CAM_1 = 12,
0150     OMAP_L3_IA_CAM_2 = 11,
0151     OMAP_L3_IA_CAM_3 = 10,
0152     /* DAP has 1 ID */
0153     OMAP_L3_IA_DAP = 9,
0154     /* SDMA WR has 2 IDs */
0155     OMAP_L3_SDMA_WR_1 = 8,
0156     OMAP_L3_SDMA_WR_2 = 7,
0157     /* SDMA RD has 4 IDs */
0158     OMAP_L3_SDMA_RD_1 = 6,
0159     OMAP_L3_SDMA_RD_2 = 5,
0160     OMAP_L3_SDMA_RD_3 = 4,
0161     OMAP_L3_SDMA_RD_4 = 3,
0162     /* HSUSB OTG has 1 ID */
0163     OMAP_L3_USBOTG = 2,
0164     /* HSUSB HOST has 1 ID */
0165     OMAP_L3_USBHOST = 1,
0166 };
0167
0168 enum omap3_l3_code {
0169     OMAP_L3_CODE_NOERROR = 0,
0170     OMAP_L3_CODE_UNSUP_CMD = 1,
0171     OMAP_L3_CODE_ADDR_HOLE = 2,
0172     OMAP_L3_CODE_PROTECT_VIOLATION = 3,
0173     OMAP_L3_CODE_IN_BAND_ERR = 4,
0174     /* codes 5 and 6 are reserved */
0175     OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
0176     OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
0177     /* codes 9 - 15 are also reserved */
0178 };
0179
0180 struct omap3_l3 {
0181     struct device *dev;
0182     struct clk *ick;
0183
0184     /* memory base*/
0185     void __iomem *rt;
0186
0187     int debug_irq;
0188     int app_irq;
0189
0190     /* true when and inband functional error occurs */
0191     unsigned inband:1;
0192 };
0193
0194 /* offsets for l3 agents in order with the Flag status register */
0195 static unsigned int omap3_l3_app_bases[] = {
0196     /* MPU IA */
0197     0x1400,
0198     0x1400,
0199     0x1400,
0200     /* RESERVED */
0201     0,
0202     0,
0203     0,
0204     /* IVA 2.2 IA */
0205     0x1800,
0206     0x1800,
0207     0x1800,
0208     /* SGX IA */
0209     0x1c00,
0210     0x1c00,
0211     /* RESERVED */
0212     0,
0213     /* CAMERA IA */
0214     0x5800,
0215     0x5800,
0216     0x5800,
0217     /* DISPLAY IA */
0218     0x5400,
0219     0x5400,
0220     /* RESERVED */
0221     0,
0222     /*SDMA RD IA */
0223     0x4c00,
0224     0x4c00,
0225     /* RESERVED */
0226     0,
0227     /* SDMA WR IA */
0228     0x5000,
0229     0x5000,
0230     /* RESERVED */
0231     0,
0232     /* USB OTG IA */
0233     0x4400,
0234     0x4400,
0235     0x4400,
0236     /* USB HOST IA */
0237     0x4000,
0238     0x4000,
0239     /* RESERVED */
0240     0,
0241     0,
0242     0,
0243     0,
0244     /* SAD2D IA */
0245     0x3000,
0246     0x3000,
0247     0x3000,
0248     /* RESERVED */
0249     0,
0250     0,
0251     0,
0252     0,
0253     0,
0254     0,
0255     0,
0256     0,
0257     0,
0258     0,
0259     0,
0260     0,
0261     /* SMA TA */
0262     0x2000,
0263     /* GPMC TA */
0264     0x2400,
0265     /* OCM RAM TA */
0266     0x2800,
0267     /* OCM ROM TA */
0268     0x2C00,
0269     /* L4 CORE TA */
0270     0x6800,
0271     /* L4 PER TA */
0272     0x6c00,
0273     /* IVA 2.2 TA */
0274     0x6000,
0275     /* SGX TA */
0276     0x6400,
0277     /* L4 EMU TA */
0278     0x7000,
0279     /* GPMC TA */
0280     0x2400,
0281     /* L4 CORE TA */
0282     0x6800,
0283     /* L4 PER TA */
0284     0x6c00,
0285     /* L4 EMU TA */
0286     0x7000,
0287     /* MAD2D TA */
0288     0x3400,
0289     /* RESERVED */
0290     0,
0291     0,
0292 };
0293
0294 static unsigned int omap3_l3_debug_bases[] = {
0295     /* MPU DATA IA */
0296     0x1400,
0297     /* RESERVED */
0298     0,
0299     0,
0300     /* DAP IA */
0301     0x5c00,
0302     0x5c00,
0303     /* RESERVED */
0304     0,
0305     /* IVA 2.2 IA */
0306     0x1800,
0307     /* REST RESERVED */
0308 };
0309
0310 static u32 *omap3_l3_bases[] = {
0311     omap3_l3_app_bases,
0312     omap3_l3_debug_bases,
0313 };
0314
0315 /*
0316  * REVISIT define __raw_readll/__raw_writell here, but move them to
0317  * <asm/io.h> at some point
0318  */
0319 #define __raw_writell(v, a) (__chk_io_ptr(a), \
0320                 *(volatile u64 __force *)(a) = (v))
0321 #define __raw_readll(a)     (__chk_io_ptr(a), \
0322                 *(volatile u64 __force *)(a))
0323
0324 #endif