drivers/bus/omap_l3_noc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP L3 Interconnect  error handling driver header
0004  *
0005  * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
0006  *  Santosh Shilimkar <santosh.shilimkar@ti.com>
0007  *  sricharan <r.sricharan@ti.com>
0008  */
0009 #ifndef __OMAP_L3_NOC_H
0010 #define __OMAP_L3_NOC_H
0011
0012 #define MAX_L3_MODULES          3
0013 #define MAX_CLKDM_TARGETS       31
0014
0015 #define CLEAR_STDERR_LOG        (1 << 31)
0016 #define CUSTOM_ERROR            0x2
0017 #define STANDARD_ERROR          0x0
0018 #define INBAND_ERROR            0x0
0019 #define L3_APPLICATION_ERROR        0x0
0020 #define L3_DEBUG_ERROR          0x1
0021
0022 /* L3 TARG register offsets */
0023 #define L3_TARG_STDERRLOG_MAIN      0x48
0024 #define L3_TARG_STDERRLOG_HDR       0x4c
0025 #define L3_TARG_STDERRLOG_MSTADDR   0x50
0026 #define L3_TARG_STDERRLOG_INFO      0x58
0027 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
0028 #define L3_TARG_STDERRLOG_CINFO_INFO    0x64
0029 #define L3_TARG_STDERRLOG_CINFO_MSTADDR 0x68
0030 #define L3_TARG_STDERRLOG_CINFO_OPCODE  0x6c
0031 #define L3_FLAGMUX_REGERR0      0xc
0032 #define L3_FLAGMUX_MASK0        0x8
0033
0034 #define L3_TARGET_NOT_SUPPORTED     NULL
0035
0036 #define L3_BASE_IS_SUBMODULE        ((void __iomem *)(1 << 0))
0037
0038 static const char * const l3_transaction_type[] = {
0039     /* 0 0 0 */ "Idle",
0040     /* 0 0 1 */ "Write",
0041     /* 0 1 0 */ "Read",
0042     /* 0 1 1 */ "ReadEx",
0043     /* 1 0 0 */ "Read Link",
0044     /* 1 0 1 */ "Write Non-Posted",
0045     /* 1 1 0 */ "Write Conditional",
0046     /* 1 1 1 */ "Write Broadcast",
0047 };
0048
0049 /**
0050  * struct l3_masters_data - L3 Master information
0051  * @id:     ID of the L3 Master
0052  * @name:   master name
0053  */
0054 struct l3_masters_data {
0055     u32 id;
0056     char *name;
0057 };
0058
0059 /**
0060  * struct l3_target_data - L3 Target information
0061  * @offset: Offset from base for L3 Target
0062  * @name:   Target name
0063  *
0064  * Target information is organized indexed by bit field definitions.
0065  */
0066 struct l3_target_data {
0067     u32 offset;
0068     char *name;
0069 };
0070
0071 /**
0072  * struct l3_flagmux_data - Flag Mux information
0073  * @offset: offset from base for flagmux register
0074  * @l3_targ:    array indexed by flagmux index (bit offset) pointing to the
0075  *      target data. unsupported ones are marked with
0076  *      L3_TARGET_NOT_SUPPORTED
0077  * @num_targ_data: number of entries in target data
0078  * @mask_app_bits: ignore these from raw application irq status
0079  * @mask_dbg_bits: ignore these from raw debug irq status
0080  */
0081 struct l3_flagmux_data {
0082     u32 offset;
0083     struct l3_target_data *l3_targ;
0084     u8 num_targ_data;
0085     u32 mask_app_bits;
0086     u32 mask_dbg_bits;
0087 };
0088
0089
0090 /**
0091  * struct omap_l3 - Description of data relevant for L3 bus.
0092  * @dev:    device representing the bus (populated runtime)
0093  * @l3_base:    base addresses of modules (populated runtime if 0)
0094  *      if set to L3_BASE_IS_SUBMODULE, then uses previous
0095  *      module index as the base address
0096  * @l3_flag_mux: array containing flag mux data per module
0097  *       offset from corresponding module base indexed per
0098  *       module.
0099  * @num_modules: number of clock domains / modules.
0100  * @l3_masters: array pointing to master data containing name and register
0101  *      offset for the master.
0102  * @num_master: number of masters
0103  * @mst_addr_mask: Mask representing MSTADDR information of NTTP packet
0104  * @debug_irq:  irq number of the debug interrupt (populated runtime)
0105  * @app_irq:    irq number of the application interrupt (populated runtime)
0106  */
0107 struct omap_l3 {
0108     struct device *dev;
0109
0110     void __iomem *l3_base[MAX_L3_MODULES];
0111     struct l3_flagmux_data **l3_flagmux;
0112     int num_modules;
0113
0114     struct l3_masters_data *l3_masters;
0115     int num_masters;
0116     u32 mst_addr_mask;
0117
0118     int debug_irq;
0119     int app_irq;
0120 };
0121
0122 static struct l3_target_data omap_l3_target_data_clk1[] = {
0123     {0x100, "DMM1",},
0124     {0x200, "DMM2",},
0125     {0x300, "ABE",},
0126     {0x400, "L4CFG",},
0127     {0x600, "CLK2PWRDISC",},
0128     {0x0,   "HOSTCLK1",},
0129     {0x900, "L4WAKEUP",},
0130 };
0131
0132 static struct l3_flagmux_data omap_l3_flagmux_clk1 = {
0133     .offset = 0x500,
0134     .l3_targ = omap_l3_target_data_clk1,
0135     .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1),
0136 };
0137
0138
0139 static struct l3_target_data omap_l3_target_data_clk2[] = {
0140     {0x500, "CORTEXM3",},
0141     {0x300, "DSS",},
0142     {0x100, "GPMC",},
0143     {0x400, "ISS",},
0144     {0x700, "IVAHD",},
0145     {0xD00, "AES1",},
0146     {0x900, "L4PER0",},
0147     {0x200, "OCMRAM",},
0148     {0x100, "GPMCsERROR",},
0149     {0x600, "SGX",},
0150     {0x800, "SL2",},
0151     {0x1600, "C2C",},
0152     {0x1100, "PWRDISCCLK1",},
0153     {0xF00, "SHA1",},
0154     {0xE00, "AES2",},
0155     {0xC00, "L4PER3",},
0156     {0xA00, "L4PER1",},
0157     {0xB00, "L4PER2",},
0158     {0x0,   "HOSTCLK2",},
0159     {0x1800, "CAL",},
0160     {0x1700, "LLI",},
0161 };
0162
0163 static struct l3_flagmux_data omap_l3_flagmux_clk2 = {
0164     .offset = 0x1000,
0165     .l3_targ = omap_l3_target_data_clk2,
0166     .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2),
0167 };
0168
0169
0170 static struct l3_target_data omap4_l3_target_data_clk3[] = {
0171     {0x0100, "DEBUGSS",},
0172 };
0173
0174 static struct l3_flagmux_data omap4_l3_flagmux_clk3 = {
0175     .offset = 0x0200,
0176     .l3_targ = omap4_l3_target_data_clk3,
0177     .num_targ_data = ARRAY_SIZE(omap4_l3_target_data_clk3),
0178 };
0179
0180 static struct l3_masters_data omap_l3_masters[] = {
0181     { 0x00, "MPU"},
0182     { 0x04, "CS_ADP"},
0183     { 0x05, "xxx"},
0184     { 0x08, "DSP"},
0185     { 0x0C, "IVAHD"},
0186     { 0x10, "ISS"},
0187     { 0x11, "DucatiM3"},
0188     { 0x12, "FaceDetect"},
0189     { 0x14, "SDMA_Rd"},
0190     { 0x15, "SDMA_Wr"},
0191     { 0x16, "xxx"},
0192     { 0x17, "xxx"},
0193     { 0x18, "SGX"},
0194     { 0x1C, "DSS"},
0195     { 0x20, "C2C"},
0196     { 0x22, "xxx"},
0197     { 0x23, "xxx"},
0198     { 0x24, "HSI"},
0199     { 0x28, "MMC1"},
0200     { 0x29, "MMC2"},
0201     { 0x2A, "MMC6"},
0202     { 0x2C, "UNIPRO1"},
0203     { 0x30, "USBHOSTHS"},
0204     { 0x31, "USBOTGHS"},
0205     { 0x32, "USBHOSTFS"}
0206 };
0207
0208 static struct l3_flagmux_data *omap4_l3_flagmux[] = {
0209     &omap_l3_flagmux_clk1,
0210     &omap_l3_flagmux_clk2,
0211     &omap4_l3_flagmux_clk3,
0212 };
0213
0214 static const struct omap_l3 omap4_l3_data = {
0215     .l3_flagmux = omap4_l3_flagmux,
0216     .num_modules = ARRAY_SIZE(omap4_l3_flagmux),
0217     .l3_masters = omap_l3_masters,
0218     .num_masters = ARRAY_SIZE(omap_l3_masters),
0219     /* The 6 MSBs of register field used to distinguish initiator */
0220     .mst_addr_mask = 0xFC,
0221 };
0222
0223 /* OMAP5 data */
0224 static struct l3_target_data omap5_l3_target_data_clk3[] = {
0225     {0x0100, "L3INSTR",},
0226     {0x0300, "DEBUGSS",},
0227     {0x0,    "HOSTCLK3",},
0228 };
0229
0230 static struct l3_flagmux_data omap5_l3_flagmux_clk3 = {
0231     .offset = 0x0200,
0232     .l3_targ = omap5_l3_target_data_clk3,
0233     .num_targ_data = ARRAY_SIZE(omap5_l3_target_data_clk3),
0234 };
0235
0236 static struct l3_flagmux_data *omap5_l3_flagmux[] = {
0237     &omap_l3_flagmux_clk1,
0238     &omap_l3_flagmux_clk2,
0239     &omap5_l3_flagmux_clk3,
0240 };
0241
0242 static const struct omap_l3 omap5_l3_data = {
0243     .l3_flagmux = omap5_l3_flagmux,
0244     .num_modules = ARRAY_SIZE(omap5_l3_flagmux),
0245     .l3_masters = omap_l3_masters,
0246     .num_masters = ARRAY_SIZE(omap_l3_masters),
0247     /* The 6 MSBs of register field used to distinguish initiator */
0248     .mst_addr_mask = 0x7E0,
0249 };
0250
0251 /* DRA7 data */
0252 static struct l3_target_data dra_l3_target_data_clk1[] = {
0253     {0x2a00, "AES1",},
0254     {0x0200, "DMM_P1",},
0255     {0x0600, "DSP2_SDMA",},
0256     {0x0b00, "EVE2",},
0257     {0x1300, "DMM_P2",},
0258     {0x2c00, "AES2",},
0259     {0x0300, "DSP1_SDMA",},
0260     {0x0a00, "EVE1",},
0261     {0x0c00, "EVE3",},
0262     {0x0d00, "EVE4",},
0263     {0x2900, "DSS",},
0264     {0x0100, "GPMC",},
0265     {0x3700, "PCIE1",},
0266     {0x1600, "IVA_CONFIG",},
0267     {0x1800, "IVA_SL2IF",},
0268     {0x0500, "L4_CFG",},
0269     {0x1d00, "L4_WKUP",},
0270     {0x3800, "PCIE2",},
0271     {0x3300, "SHA2_1",},
0272     {0x1200, "GPU",},
0273     {0x1000, "IPU1",},
0274     {0x1100, "IPU2",},
0275     {0x2000, "TPCC_EDMA",},
0276     {0x2e00, "TPTC1_EDMA",},
0277     {0x2b00, "TPTC2_EDMA",},
0278     {0x0700, "VCP1",},
0279     {0x2500, "L4_PER2_P3",},
0280     {0x0e00, "L4_PER3_P3",},
0281     {0x2200, "MMU1",},
0282     {0x1400, "PRUSS1",},
0283     {0x1500, "PRUSS2"},
0284     {0x0800, "VCP1",},
0285 };
0286
0287 static struct l3_flagmux_data dra_l3_flagmux_clk1 = {
0288     .offset = 0x803500,
0289     .l3_targ = dra_l3_target_data_clk1,
0290     .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk1),
0291 };
0292
0293 static struct l3_target_data dra_l3_target_data_clk2[] = {
0294     {0x0,   "HOST CLK1",},
0295     {0x800000, "HOST CLK2",},
0296     {0xdead, L3_TARGET_NOT_SUPPORTED,},
0297     {0x3400, "SHA2_2",},
0298     {0x0900, "BB2D",},
0299     {0xdead, L3_TARGET_NOT_SUPPORTED,},
0300     {0x2100, "L4_PER1_P3",},
0301     {0x1c00, "L4_PER1_P1",},
0302     {0x1f00, "L4_PER1_P2",},
0303     {0x2300, "L4_PER2_P1",},
0304     {0x2400, "L4_PER2_P2",},
0305     {0x2600, "L4_PER3_P1",},
0306     {0x2700, "L4_PER3_P2",},
0307     {0x2f00, "MCASP1",},
0308     {0x3000, "MCASP2",},
0309     {0x3100, "MCASP3",},
0310     {0x2800, "MMU2",},
0311     {0x0f00, "OCMC_RAM1",},
0312     {0x1700, "OCMC_RAM2",},
0313     {0x1900, "OCMC_RAM3",},
0314     {0x1e00, "OCMC_ROM",},
0315     {0x3900, "QSPI",},
0316 };
0317
0318 static struct l3_flagmux_data dra_l3_flagmux_clk2 = {
0319     .offset = 0x803600,
0320     .l3_targ = dra_l3_target_data_clk2,
0321     .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk2),
0322 };
0323
0324 static struct l3_target_data dra_l3_target_data_clk3[] = {
0325     {0x0100, "L3_INSTR"},
0326     {0x0300, "DEBUGSS_CT_TBR"},
0327     {0x0,    "HOST CLK3"},
0328 };
0329
0330 static struct l3_flagmux_data dra_l3_flagmux_clk3 = {
0331     .offset = 0x200,
0332     .l3_targ = dra_l3_target_data_clk3,
0333     .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk3),
0334 };
0335
0336 static struct l3_masters_data dra_l3_masters[] = {
0337     { 0x0, "MPU" },
0338     { 0x4, "CS_DAP" },
0339     { 0x5, "IEEE1500_2_OCP" },
0340     { 0x8, "DSP1_MDMA" },
0341     { 0x9, "DSP1_CFG" },
0342     { 0xA, "DSP1_DMA" },
0343     { 0xB, "DSP2_MDMA" },
0344     { 0xC, "DSP2_CFG" },
0345     { 0xD, "DSP2_DMA" },
0346     { 0xE, "IVA" },
0347     { 0x10, "EVE1_P1" },
0348     { 0x11, "EVE2_P1" },
0349     { 0x12, "EVE3_P1" },
0350     { 0x13, "EVE4_P1" },
0351     { 0x14, "PRUSS1 PRU1" },
0352     { 0x15, "PRUSS1 PRU2" },
0353     { 0x16, "PRUSS2 PRU1" },
0354     { 0x17, "PRUSS2 PRU2" },
0355     { 0x18, "IPU1" },
0356     { 0x19, "IPU2" },
0357     { 0x1A, "SDMA" },
0358     { 0x1B, "CDMA" },
0359     { 0x1C, "TC1_EDMA" },
0360     { 0x1D, "TC2_EDMA" },
0361     { 0x20, "DSS" },
0362     { 0x21, "MMU1" },
0363     { 0x22, "PCIE1" },
0364     { 0x23, "MMU2" },
0365     { 0x24, "VIP1" },
0366     { 0x25, "VIP2" },
0367     { 0x26, "VIP3" },
0368     { 0x27, "VPE" },
0369     { 0x28, "GPU_P1" },
0370     { 0x29, "BB2D" },
0371     { 0x29, "GPU_P2" },
0372     { 0x2B, "GMAC_SW" },
0373     { 0x2C, "USB3" },
0374     { 0x2D, "USB2_SS" },
0375     { 0x2E, "USB2_ULPI_SS1" },
0376     { 0x2F, "USB2_ULPI_SS2" },
0377     { 0x30, "CSI2_1" },
0378     { 0x31, "CSI2_2" },
0379     { 0x33, "SATA" },
0380     { 0x34, "EVE1_P2" },
0381     { 0x35, "EVE2_P2" },
0382     { 0x36, "EVE3_P2" },
0383     { 0x37, "EVE4_P2" }
0384 };
0385
0386 static struct l3_flagmux_data *dra_l3_flagmux[] = {
0387     &dra_l3_flagmux_clk1,
0388     &dra_l3_flagmux_clk2,
0389     &dra_l3_flagmux_clk3,
0390 };
0391
0392 static const struct omap_l3 dra_l3_data = {
0393     .l3_base = { [1] = L3_BASE_IS_SUBMODULE },
0394     .l3_flagmux = dra_l3_flagmux,
0395     .num_modules = ARRAY_SIZE(dra_l3_flagmux),
0396     .l3_masters = dra_l3_masters,
0397     .num_masters = ARRAY_SIZE(dra_l3_masters),
0398     /* The 6 MSBs of register field used to distinguish initiator */
0399     .mst_addr_mask = 0xFC,
0400 };
0401
0402 /* AM4372 data */
0403 static struct l3_target_data am4372_l3_target_data_200f[] = {
0404     {0xf00,  "EMIF",},
0405     {0x1200, "DES",},
0406     {0x400,  "OCMCRAM",},
0407     {0x700,  "TPTC0",},
0408     {0x800,  "TPTC1",},
0409     {0x900,  "TPTC2"},
0410     {0xb00,  "TPCC",},
0411     {0xd00,  "DEBUGSS",},
0412     {0xdead, L3_TARGET_NOT_SUPPORTED,},
0413     {0x200,  "SHA",},
0414     {0xc00,  "SGX530",},
0415     {0x500,  "AES0",},
0416     {0xa00,  "L4_FAST",},
0417     {0x300,  "MPUSS_L2_RAM",},
0418     {0x100,  "ICSS",},
0419 };
0420
0421 static struct l3_flagmux_data am4372_l3_flagmux_200f = {
0422     .offset = 0x1000,
0423     .l3_targ = am4372_l3_target_data_200f,
0424     .num_targ_data = ARRAY_SIZE(am4372_l3_target_data_200f),
0425 };
0426
0427 static struct l3_target_data am4372_l3_target_data_100s[] = {
0428     {0x100, "L4_PER_0",},
0429     {0x200, "L4_PER_1",},
0430     {0x300, "L4_PER_2",},
0431     {0x400, "L4_PER_3",},
0432     {0x800, "McASP0",},
0433     {0x900, "McASP1",},
0434     {0xC00, "MMCHS2",},
0435     {0x700, "GPMC",},
0436     {0xD00, "L4_FW",},
0437     {0xdead, L3_TARGET_NOT_SUPPORTED,},
0438     {0x500, "ADCTSC",},
0439     {0xE00, "L4_WKUP",},
0440     {0xA00, "MAG_CARD",},
0441 };
0442
0443 static struct l3_flagmux_data am4372_l3_flagmux_100s = {
0444     .offset = 0x600,
0445     .l3_targ = am4372_l3_target_data_100s,
0446     .num_targ_data = ARRAY_SIZE(am4372_l3_target_data_100s),
0447 };
0448
0449 static struct l3_masters_data am4372_l3_masters[] = {
0450     { 0x0, "M1 (128-bit)"},
0451     { 0x1, "M2 (64-bit)"},
0452     { 0x4, "DAP"},
0453     { 0x5, "P1500"},
0454     { 0xC, "ICSS0"},
0455     { 0xD, "ICSS1"},
0456     { 0x14, "Wakeup Processor"},
0457     { 0x18, "TPTC0 Read"},
0458     { 0x19, "TPTC0 Write"},
0459     { 0x1A, "TPTC1 Read"},
0460     { 0x1B, "TPTC1 Write"},
0461     { 0x1C, "TPTC2 Read"},
0462     { 0x1D, "TPTC2 Write"},
0463     { 0x20, "SGX530"},
0464     { 0x21, "OCP WP Traffic Probe"},
0465     { 0x22, "OCP WP DMA Profiling"},
0466     { 0x23, "OCP WP Event Trace"},
0467     { 0x25, "DSS"},
0468     { 0x28, "Crypto DMA RD"},
0469     { 0x29, "Crypto DMA WR"},
0470     { 0x2C, "VPFE0"},
0471     { 0x2D, "VPFE1"},
0472     { 0x30, "GEMAC"},
0473     { 0x34, "USB0 RD"},
0474     { 0x35, "USB0 WR"},
0475     { 0x36, "USB1 RD"},
0476     { 0x37, "USB1 WR"},
0477 };
0478
0479 static struct l3_flagmux_data *am4372_l3_flagmux[] = {
0480     &am4372_l3_flagmux_200f,
0481     &am4372_l3_flagmux_100s,
0482 };
0483
0484 static const struct omap_l3 am4372_l3_data = {
0485     .l3_flagmux = am4372_l3_flagmux,
0486     .num_modules = ARRAY_SIZE(am4372_l3_flagmux),
0487     .l3_masters = am4372_l3_masters,
0488     .num_masters = ARRAY_SIZE(am4372_l3_masters),
0489     /* All 6 bits of register field used to distinguish initiator */
0490     .mst_addr_mask = 0x3F,
0491 };
0492
0493 #endif  /* __OMAP_L3_NOC_H */