bus/mhi/common.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2022, Linaro Ltd.
0004  *
0005  */
0006
0007 #ifndef _MHI_COMMON_H
0008 #define _MHI_COMMON_H
0009
0010 #include <linux/bitfield.h>
0011 #include <linux/mhi.h>
0012
0013 /* MHI registers */
0014 #define MHIREGLEN           0x00
0015 #define MHIVER              0x08
0016 #define MHICFG              0x10
0017 #define CHDBOFF             0x18
0018 #define ERDBOFF             0x20
0019 #define BHIOFF              0x28
0020 #define BHIEOFF             0x2c
0021 #define DEBUGOFF            0x30
0022 #define MHICTRL             0x38
0023 #define MHISTATUS           0x48
0024 #define CCABAP_LOWER            0x58
0025 #define CCABAP_HIGHER           0x5c
0026 #define ECABAP_LOWER            0x60
0027 #define ECABAP_HIGHER           0x64
0028 #define CRCBAP_LOWER            0x68
0029 #define CRCBAP_HIGHER           0x6c
0030 #define CRDB_LOWER          0x70
0031 #define CRDB_HIGHER         0x74
0032 #define MHICTRLBASE_LOWER       0x80
0033 #define MHICTRLBASE_HIGHER      0x84
0034 #define MHICTRLLIMIT_LOWER      0x88
0035 #define MHICTRLLIMIT_HIGHER     0x8c
0036 #define MHIDATABASE_LOWER       0x98
0037 #define MHIDATABASE_HIGHER      0x9c
0038 #define MHIDATALIMIT_LOWER      0xa0
0039 #define MHIDATALIMIT_HIGHER     0xa4
0040
0041 /* MHI BHI registers */
0042 #define BHI_BHIVERSION_MINOR        0x00
0043 #define BHI_BHIVERSION_MAJOR        0x04
0044 #define BHI_IMGADDR_LOW         0x08
0045 #define BHI_IMGADDR_HIGH        0x0c
0046 #define BHI_IMGSIZE         0x10
0047 #define BHI_RSVD1           0x14
0048 #define BHI_IMGTXDB         0x18
0049 #define BHI_RSVD2           0x1c
0050 #define BHI_INTVEC          0x20
0051 #define BHI_RSVD3           0x24
0052 #define BHI_EXECENV         0x28
0053 #define BHI_STATUS          0x2c
0054 #define BHI_ERRCODE         0x30
0055 #define BHI_ERRDBG1         0x34
0056 #define BHI_ERRDBG2         0x38
0057 #define BHI_ERRDBG3         0x3c
0058 #define BHI_SERIALNU            0x40
0059 #define BHI_SBLANTIROLLVER      0x44
0060 #define BHI_NUMSEG          0x48
0061 #define BHI_MSMHWID(n)          (0x4c + (0x4 * (n)))
0062 #define BHI_OEMPKHASH(n)        (0x64 + (0x4 * (n)))
0063 #define BHI_RSVD5           0xc4
0064
0065 /* BHI register bits */
0066 #define BHI_TXDB_SEQNUM_BMSK        GENMASK(29, 0)
0067 #define BHI_TXDB_SEQNUM_SHFT        0
0068 #define BHI_STATUS_MASK         GENMASK(31, 30)
0069 #define BHI_STATUS_ERROR        0x03
0070 #define BHI_STATUS_SUCCESS      0x02
0071 #define BHI_STATUS_RESET        0x00
0072
0073 /* MHI BHIE registers */
0074 #define BHIE_MSMSOCID_OFFS      0x00
0075 #define BHIE_TXVECADDR_LOW_OFFS     0x2c
0076 #define BHIE_TXVECADDR_HIGH_OFFS    0x30
0077 #define BHIE_TXVECSIZE_OFFS     0x34
0078 #define BHIE_TXVECDB_OFFS       0x3c
0079 #define BHIE_TXVECSTATUS_OFFS       0x44
0080 #define BHIE_RXVECADDR_LOW_OFFS     0x60
0081 #define BHIE_RXVECADDR_HIGH_OFFS    0x64
0082 #define BHIE_RXVECSIZE_OFFS     0x68
0083 #define BHIE_RXVECDB_OFFS       0x70
0084 #define BHIE_RXVECSTATUS_OFFS       0x78
0085
0086 /* BHIE register bits */
0087 #define BHIE_TXVECDB_SEQNUM_BMSK    GENMASK(29, 0)
0088 #define BHIE_TXVECDB_SEQNUM_SHFT    0
0089 #define BHIE_TXVECSTATUS_SEQNUM_BMSK    GENMASK(29, 0)
0090 #define BHIE_TXVECSTATUS_SEQNUM_SHFT    0
0091 #define BHIE_TXVECSTATUS_STATUS_BMSK    GENMASK(31, 30)
0092 #define BHIE_TXVECSTATUS_STATUS_SHFT    30
0093 #define BHIE_TXVECSTATUS_STATUS_RESET   0x00
0094 #define BHIE_TXVECSTATUS_STATUS_XFER_COMPL  0x02
0095 #define BHIE_TXVECSTATUS_STATUS_ERROR   0x03
0096 #define BHIE_RXVECDB_SEQNUM_BMSK    GENMASK(29, 0)
0097 #define BHIE_RXVECDB_SEQNUM_SHFT    0
0098 #define BHIE_RXVECSTATUS_SEQNUM_BMSK    GENMASK(29, 0)
0099 #define BHIE_RXVECSTATUS_SEQNUM_SHFT    0
0100 #define BHIE_RXVECSTATUS_STATUS_BMSK    GENMASK(31, 30)
0101 #define BHIE_RXVECSTATUS_STATUS_SHFT    30
0102 #define BHIE_RXVECSTATUS_STATUS_RESET   0x00
0103 #define BHIE_RXVECSTATUS_STATUS_XFER_COMPL  0x02
0104 #define BHIE_RXVECSTATUS_STATUS_ERROR   0x03
0105
0106 /* MHI register bits */
0107 #define MHICFG_NHWER_MASK       GENMASK(31, 24)
0108 #define MHICFG_NER_MASK         GENMASK(23, 16)
0109 #define MHICFG_NHWCH_MASK       GENMASK(15, 8)
0110 #define MHICFG_NCH_MASK         GENMASK(7, 0)
0111 #define MHICTRL_MHISTATE_MASK       GENMASK(15, 8)
0112 #define MHICTRL_RESET_MASK      BIT(1)
0113 #define MHISTATUS_MHISTATE_MASK     GENMASK(15, 8)
0114 #define MHISTATUS_SYSERR_MASK       BIT(2)
0115 #define MHISTATUS_READY_MASK        BIT(0)
0116
0117 /* Command Ring Element macros */
0118 /* No operation command */
0119 #define MHI_TRE_CMD_NOOP_PTR        0
0120 #define MHI_TRE_CMD_NOOP_DWORD0     0
0121 #define MHI_TRE_CMD_NOOP_DWORD1     cpu_to_le32(FIELD_PREP(GENMASK(23, 16), MHI_CMD_NOP))
0122
0123 /* Channel reset command */
0124 #define MHI_TRE_CMD_RESET_PTR       0
0125 #define MHI_TRE_CMD_RESET_DWORD0    0
0126 #define MHI_TRE_CMD_RESET_DWORD1(chid)  cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
0127                             FIELD_PREP(GENMASK(23, 16),         \
0128                                    MHI_CMD_RESET_CHAN))
0129
0130 /* Channel stop command */
0131 #define MHI_TRE_CMD_STOP_PTR        0
0132 #define MHI_TRE_CMD_STOP_DWORD0     0
0133 #define MHI_TRE_CMD_STOP_DWORD1(chid)   cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
0134                             FIELD_PREP(GENMASK(23, 16),         \
0135                                    MHI_CMD_STOP_CHAN))
0136
0137 /* Channel start command */
0138 #define MHI_TRE_CMD_START_PTR       0
0139 #define MHI_TRE_CMD_START_DWORD0    0
0140 #define MHI_TRE_CMD_START_DWORD1(chid)  cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
0141                             FIELD_PREP(GENMASK(23, 16),         \
0142                                    MHI_CMD_START_CHAN))
0143
0144 #define MHI_TRE_GET_DWORD(tre, word)    le32_to_cpu((tre)->dword[(word)])
0145 #define MHI_TRE_GET_CMD_CHID(tre)   FIELD_GET(GENMASK(31, 24), MHI_TRE_GET_DWORD(tre, 1))
0146 #define MHI_TRE_GET_CMD_TYPE(tre)   FIELD_GET(GENMASK(23, 16), MHI_TRE_GET_DWORD(tre, 1))
0147
0148 /* Event descriptor macros */
0149 #define MHI_TRE_EV_PTR(ptr)     cpu_to_le64(ptr)
0150 #define MHI_TRE_EV_DWORD0(code, len)    cpu_to_le32(FIELD_PREP(GENMASK(31, 24), code) | \
0151                             FIELD_PREP(GENMASK(15, 0), len))
0152 #define MHI_TRE_EV_DWORD1(chid, type)   cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
0153                             FIELD_PREP(GENMASK(23, 16), type))
0154 #define MHI_TRE_GET_EV_PTR(tre)     le64_to_cpu((tre)->ptr)
0155 #define MHI_TRE_GET_EV_CODE(tre)    FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))
0156 #define MHI_TRE_GET_EV_LEN(tre)     FIELD_GET(GENMASK(15, 0), (MHI_TRE_GET_DWORD(tre, 0)))
0157 #define MHI_TRE_GET_EV_CHID(tre)    FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1)))
0158 #define MHI_TRE_GET_EV_TYPE(tre)    FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 1)))
0159 #define MHI_TRE_GET_EV_STATE(tre)   FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))
0160 #define MHI_TRE_GET_EV_EXECENV(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))
0161 #define MHI_TRE_GET_EV_SEQ(tre)     MHI_TRE_GET_DWORD(tre, 0)
0162 #define MHI_TRE_GET_EV_TIME(tre)    MHI_TRE_GET_EV_PTR(tre)
0163 #define MHI_TRE_GET_EV_COOKIE(tre)  lower_32_bits(MHI_TRE_GET_EV_PTR(tre))
0164 #define MHI_TRE_GET_EV_VEID(tre)    FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 0)))
0165 #define MHI_TRE_GET_EV_LINKSPEED(tre)   FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1)))
0166 #define MHI_TRE_GET_EV_LINKWIDTH(tre)   FIELD_GET(GENMASK(7, 0), (MHI_TRE_GET_DWORD(tre, 0)))
0167
0168 /* State change event */
0169 #define MHI_SC_EV_PTR           0
0170 #define MHI_SC_EV_DWORD0(state)     cpu_to_le32(FIELD_PREP(GENMASK(31, 24), state))
0171 #define MHI_SC_EV_DWORD1(type)      cpu_to_le32(FIELD_PREP(GENMASK(23, 16), type))
0172
0173 /* EE event */
0174 #define MHI_EE_EV_PTR           0
0175 #define MHI_EE_EV_DWORD0(ee)        cpu_to_le32(FIELD_PREP(GENMASK(31, 24), ee))
0176 #define MHI_EE_EV_DWORD1(type)      cpu_to_le32(FIELD_PREP(GENMASK(23, 16), type))
0177
0178
0179 /* Command Completion event */
0180 #define MHI_CC_EV_PTR(ptr)      cpu_to_le64(ptr)
0181 #define MHI_CC_EV_DWORD0(code)      cpu_to_le32(FIELD_PREP(GENMASK(31, 24), code))
0182 #define MHI_CC_EV_DWORD1(type)      cpu_to_le32(FIELD_PREP(GENMASK(23, 16), type))
0183
0184 /* Transfer descriptor macros */
0185 #define MHI_TRE_DATA_PTR(ptr)       cpu_to_le64(ptr)
0186 #define MHI_TRE_DATA_DWORD0(len)    cpu_to_le32(FIELD_PREP(GENMASK(15, 0), len))
0187 #define MHI_TRE_TYPE_TRANSFER       2
0188 #define MHI_TRE_DATA_DWORD1(bei, ieot, ieob, chain) cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \
0189                                 MHI_TRE_TYPE_TRANSFER) |    \
0190                                 FIELD_PREP(BIT(10), bei) |  \
0191                                 FIELD_PREP(BIT(9), ieot) |  \
0192                                 FIELD_PREP(BIT(8), ieob) |  \
0193                                 FIELD_PREP(BIT(0), chain))
0194 #define MHI_TRE_DATA_GET_PTR(tre)   le64_to_cpu((tre)->ptr)
0195 #define MHI_TRE_DATA_GET_LEN(tre)   FIELD_GET(GENMASK(15, 0), MHI_TRE_GET_DWORD(tre, 0))
0196 #define MHI_TRE_DATA_GET_CHAIN(tre) (!!(FIELD_GET(BIT(0), MHI_TRE_GET_DWORD(tre, 1))))
0197 #define MHI_TRE_DATA_GET_IEOB(tre)  (!!(FIELD_GET(BIT(8), MHI_TRE_GET_DWORD(tre, 1))))
0198 #define MHI_TRE_DATA_GET_IEOT(tre)  (!!(FIELD_GET(BIT(9), MHI_TRE_GET_DWORD(tre, 1))))
0199 #define MHI_TRE_DATA_GET_BEI(tre)   (!!(FIELD_GET(BIT(10), MHI_TRE_GET_DWORD(tre, 1))))
0200
0201 /* RSC transfer descriptor macros */
0202 #define MHI_RSCTRE_DATA_PTR(ptr, len)   cpu_to_le64(FIELD_PREP(GENMASK(64, 48), len) | ptr)
0203 #define MHI_RSCTRE_DATA_DWORD0(cookie)  cpu_to_le32(cookie)
0204 #define MHI_RSCTRE_DATA_DWORD1      cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \
0205                                    MHI_PKT_TYPE_COALESCING))
0206
0207 enum mhi_pkt_type {
0208     MHI_PKT_TYPE_INVALID = 0x0,
0209     MHI_PKT_TYPE_NOOP_CMD = 0x1,
0210     MHI_PKT_TYPE_TRANSFER = 0x2,
0211     MHI_PKT_TYPE_COALESCING = 0x8,
0212     MHI_PKT_TYPE_RESET_CHAN_CMD = 0x10,
0213     MHI_PKT_TYPE_STOP_CHAN_CMD = 0x11,
0214     MHI_PKT_TYPE_START_CHAN_CMD = 0x12,
0215     MHI_PKT_TYPE_STATE_CHANGE_EVENT = 0x20,
0216     MHI_PKT_TYPE_CMD_COMPLETION_EVENT = 0x21,
0217     MHI_PKT_TYPE_TX_EVENT = 0x22,
0218     MHI_PKT_TYPE_RSC_TX_EVENT = 0x28,
0219     MHI_PKT_TYPE_EE_EVENT = 0x40,
0220     MHI_PKT_TYPE_TSYNC_EVENT = 0x48,
0221     MHI_PKT_TYPE_BW_REQ_EVENT = 0x50,
0222     MHI_PKT_TYPE_STALE_EVENT, /* internal event */
0223 };
0224
0225 /* MHI transfer completion events */
0226 enum mhi_ev_ccs {
0227     MHI_EV_CC_INVALID = 0x0,
0228     MHI_EV_CC_SUCCESS = 0x1,
0229     MHI_EV_CC_EOT = 0x2, /* End of transfer event */
0230     MHI_EV_CC_OVERFLOW = 0x3,
0231     MHI_EV_CC_EOB = 0x4, /* End of block event */
0232     MHI_EV_CC_OOB = 0x5, /* Out of block event */
0233     MHI_EV_CC_DB_MODE = 0x6,
0234     MHI_EV_CC_UNDEFINED_ERR = 0x10,
0235     MHI_EV_CC_BAD_TRE = 0x11,
0236 };
0237
0238 /* Channel state */
0239 enum mhi_ch_state {
0240     MHI_CH_STATE_DISABLED,
0241     MHI_CH_STATE_ENABLED,
0242     MHI_CH_STATE_RUNNING,
0243     MHI_CH_STATE_SUSPENDED,
0244     MHI_CH_STATE_STOP,
0245     MHI_CH_STATE_ERROR,
0246 };
0247
0248 enum mhi_cmd_type {
0249     MHI_CMD_NOP = 1,
0250     MHI_CMD_RESET_CHAN = 16,
0251     MHI_CMD_STOP_CHAN = 17,
0252     MHI_CMD_START_CHAN = 18,
0253 };
0254
0255 #define EV_CTX_RESERVED_MASK        GENMASK(7, 0)
0256 #define EV_CTX_INTMODC_MASK     GENMASK(15, 8)
0257 #define EV_CTX_INTMODT_MASK     GENMASK(31, 16)
0258 struct mhi_event_ctxt {
0259     __le32 intmod;
0260     __le32 ertype;
0261     __le32 msivec;
0262
0263     __le64 rbase __packed __aligned(4);
0264     __le64 rlen __packed __aligned(4);
0265     __le64 rp __packed __aligned(4);
0266     __le64 wp __packed __aligned(4);
0267 };
0268
0269 #define CHAN_CTX_CHSTATE_MASK       GENMASK(7, 0)
0270 #define CHAN_CTX_BRSTMODE_MASK      GENMASK(9, 8)
0271 #define CHAN_CTX_POLLCFG_MASK       GENMASK(15, 10)
0272 #define CHAN_CTX_RESERVED_MASK      GENMASK(31, 16)
0273 struct mhi_chan_ctxt {
0274     __le32 chcfg;
0275     __le32 chtype;
0276     __le32 erindex;
0277
0278     __le64 rbase __packed __aligned(4);
0279     __le64 rlen __packed __aligned(4);
0280     __le64 rp __packed __aligned(4);
0281     __le64 wp __packed __aligned(4);
0282 };
0283
0284 struct mhi_cmd_ctxt {
0285     __le32 reserved0;
0286     __le32 reserved1;
0287     __le32 reserved2;
0288
0289     __le64 rbase __packed __aligned(4);
0290     __le64 rlen __packed __aligned(4);
0291     __le64 rp __packed __aligned(4);
0292     __le64 wp __packed __aligned(4);
0293 };
0294
0295 struct mhi_ring_element {
0296     __le64 ptr;
0297     __le32 dword[2];
0298 };
0299
0300 static inline const char *mhi_state_str(enum mhi_state state)
0301 {
0302     switch (state) {
0303     case MHI_STATE_RESET:
0304         return "RESET";
0305     case MHI_STATE_READY:
0306         return "READY";
0307     case MHI_STATE_M0:
0308         return "M0";
0309     case MHI_STATE_M1:
0310         return "M1";
0311     case MHI_STATE_M2:
0312         return "M2";
0313     case MHI_STATE_M3:
0314         return "M3";
0315     case MHI_STATE_M3_FAST:
0316         return "M3 FAST";
0317     case MHI_STATE_BHI:
0318         return "BHI";
0319     case MHI_STATE_SYS_ERR:
0320         return "SYS ERROR";
0321     default:
0322         return "Unknown state";
0323     }
0324 };
0325
0326 #endif /* _MHI_COMMON_H */