drivers/bus/intel-ixp4xx-eb.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Intel IXP4xx Expansion Bus Controller
0004  * Copyright (C) 2021 Linaro Ltd.
0005  *
0006  * Author: Linus Walleij <linus.walleij@linaro.org>
0007  */
0008
0009 #include <linux/bitfield.h>
0010 #include <linux/bits.h>
0011 #include <linux/err.h>
0012 #include <linux/init.h>
0013 #include <linux/log2.h>
0014 #include <linux/mfd/syscon.h>
0015 #include <linux/module.h>
0016 #include <linux/of.h>
0017 #include <linux/of_platform.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/regmap.h>
0020
0021 #define IXP4XX_EXP_NUM_CS       8
0022
0023 #define IXP4XX_EXP_TIMING_CS0       0x00
0024 #define IXP4XX_EXP_TIMING_CS1       0x04
0025 #define IXP4XX_EXP_TIMING_CS2       0x08
0026 #define IXP4XX_EXP_TIMING_CS3       0x0c
0027 #define IXP4XX_EXP_TIMING_CS4       0x10
0028 #define IXP4XX_EXP_TIMING_CS5       0x14
0029 #define IXP4XX_EXP_TIMING_CS6       0x18
0030 #define IXP4XX_EXP_TIMING_CS7       0x1c
0031
0032 /* Bits inside each CS timing register */
0033 #define IXP4XX_EXP_TIMING_STRIDE    0x04
0034 #define IXP4XX_EXP_CS_EN        BIT(31)
0035 #define IXP456_EXP_PAR_EN       BIT(30) /* Only on IXP45x and IXP46x */
0036 #define IXP4XX_EXP_T1_MASK      GENMASK(28, 27)
0037 #define IXP4XX_EXP_T1_SHIFT     28
0038 #define IXP4XX_EXP_T2_MASK      GENMASK(27, 26)
0039 #define IXP4XX_EXP_T2_SHIFT     26
0040 #define IXP4XX_EXP_T3_MASK      GENMASK(25, 22)
0041 #define IXP4XX_EXP_T3_SHIFT     22
0042 #define IXP4XX_EXP_T4_MASK      GENMASK(21, 20)
0043 #define IXP4XX_EXP_T4_SHIFT     20
0044 #define IXP4XX_EXP_T5_MASK      GENMASK(19, 16)
0045 #define IXP4XX_EXP_T5_SHIFT     16
0046 #define IXP4XX_EXP_CYC_TYPE_MASK    GENMASK(15, 14)
0047 #define IXP4XX_EXP_CYC_TYPE_SHIFT   14
0048 #define IXP4XX_EXP_SIZE_MASK        GENMASK(13, 10)
0049 #define IXP4XX_EXP_SIZE_SHIFT       10
0050 #define IXP4XX_EXP_CNFG_0       BIT(9) /* Always zero */
0051 #define IXP43X_EXP_SYNC_INTEL       BIT(8) /* Only on IXP43x */
0052 #define IXP43X_EXP_EXP_CHIP     BIT(7) /* Only on IXP43x */
0053 #define IXP4XX_EXP_BYTE_RD16        BIT(6)
0054 #define IXP4XX_EXP_HRDY_POL     BIT(5) /* Only on IXP42x */
0055 #define IXP4XX_EXP_MUX_EN       BIT(4)
0056 #define IXP4XX_EXP_SPLT_EN      BIT(3)
0057 #define IXP4XX_EXP_WORD         BIT(2) /* Always zero */
0058 #define IXP4XX_EXP_WR_EN        BIT(1)
0059 #define IXP4XX_EXP_BYTE_EN      BIT(0)
0060 #define IXP42X_RESERVED         (BIT(30)|IXP4XX_EXP_CNFG_0|BIT(8)|BIT(7)|IXP4XX_EXP_WORD)
0061 #define IXP43X_RESERVED         (BIT(30)|IXP4XX_EXP_CNFG_0|BIT(5)|IXP4XX_EXP_WORD)
0062
0063 #define IXP4XX_EXP_CNFG0        0x20
0064 #define IXP4XX_EXP_CNFG0_MEM_MAP    BIT(31)
0065 #define IXP4XX_EXP_CNFG1        0x24
0066
0067 #define IXP4XX_EXP_BOOT_BASE        0x00000000
0068 #define IXP4XX_EXP_NORMAL_BASE      0x50000000
0069 #define IXP4XX_EXP_STRIDE       0x01000000
0070
0071 /* Fuses on the IXP43x */
0072 #define IXP43X_EXP_UNIT_FUSE_RESET  0x28
0073 #define IXP43x_EXP_FUSE_SPEED_MASK  GENMASK(23, 22)
0074
0075 /* Number of device tree values in "reg" */
0076 #define IXP4XX_OF_REG_SIZE      3
0077
0078 struct ixp4xx_eb {
0079     struct device *dev;
0080     struct regmap *rmap;
0081     u32 bus_base;
0082     bool is_42x;
0083     bool is_43x;
0084 };
0085
0086 struct ixp4xx_exp_tim_prop {
0087     const char *prop;
0088     u32 max;
0089     u32 mask;
0090     u16 shift;
0091 };
0092
0093 static const struct ixp4xx_exp_tim_prop ixp4xx_exp_tim_props[] = {
0094     {
0095         .prop = "intel,ixp4xx-eb-t1",
0096         .max = 3,
0097         .mask = IXP4XX_EXP_T1_MASK,
0098         .shift = IXP4XX_EXP_T1_SHIFT,
0099     },
0100     {
0101         .prop = "intel,ixp4xx-eb-t2",
0102         .max = 3,
0103         .mask = IXP4XX_EXP_T2_MASK,
0104         .shift = IXP4XX_EXP_T2_SHIFT,
0105     },
0106     {
0107         .prop = "intel,ixp4xx-eb-t3",
0108         .max = 15,
0109         .mask = IXP4XX_EXP_T3_MASK,
0110         .shift = IXP4XX_EXP_T3_SHIFT,
0111     },
0112     {
0113         .prop = "intel,ixp4xx-eb-t4",
0114         .max = 3,
0115         .mask = IXP4XX_EXP_T4_MASK,
0116         .shift = IXP4XX_EXP_T4_SHIFT,
0117     },
0118     {
0119         .prop = "intel,ixp4xx-eb-t5",
0120         .max = 15,
0121         .mask = IXP4XX_EXP_T5_MASK,
0122         .shift = IXP4XX_EXP_T5_SHIFT,
0123     },
0124     {
0125         .prop = "intel,ixp4xx-eb-byte-access-on-halfword",
0126         .max = 1,
0127         .mask = IXP4XX_EXP_BYTE_RD16,
0128     },
0129     {
0130         .prop = "intel,ixp4xx-eb-hpi-hrdy-pol-high",
0131         .max = 1,
0132         .mask = IXP4XX_EXP_HRDY_POL,
0133     },
0134     {
0135         .prop = "intel,ixp4xx-eb-mux-address-and-data",
0136         .max = 1,
0137         .mask = IXP4XX_EXP_MUX_EN,
0138     },
0139     {
0140         .prop = "intel,ixp4xx-eb-ahb-split-transfers",
0141         .max = 1,
0142         .mask = IXP4XX_EXP_SPLT_EN,
0143     },
0144     {
0145         .prop = "intel,ixp4xx-eb-write-enable",
0146         .max = 1,
0147         .mask = IXP4XX_EXP_WR_EN,
0148     },
0149     {
0150         .prop = "intel,ixp4xx-eb-byte-access",
0151         .max = 1,
0152         .mask = IXP4XX_EXP_BYTE_EN,
0153     },
0154 };
0155
0156 static void ixp4xx_exp_setup_chipselect(struct ixp4xx_eb *eb,
0157                     struct device_node *np,
0158                     u32 cs_index,
0159                     u32 cs_size)
0160 {
0161     u32 cs_cfg;
0162     u32 val;
0163     u32 cur_cssize;
0164     u32 cs_order;
0165     int ret;
0166     int i;
0167
0168     if (eb->is_42x && (cs_index > 7)) {
0169         dev_err(eb->dev,
0170             "invalid chipselect %u, we only support 0-7\n",
0171             cs_index);
0172         return;
0173     }
0174     if (eb->is_43x && (cs_index > 3)) {
0175         dev_err(eb->dev,
0176             "invalid chipselect %u, we only support 0-3\n",
0177             cs_index);
0178         return;
0179     }
0180
0181     /* Several chip selects can be joined into one device */
0182     if (cs_size > IXP4XX_EXP_STRIDE)
0183         cur_cssize = IXP4XX_EXP_STRIDE;
0184     else
0185         cur_cssize = cs_size;
0186
0187
0188     /*
0189      * The following will read/modify/write the configuration for one
0190      * chipselect, attempting to leave the boot defaults in place unless
0191      * something is explicitly defined.
0192      */
0193     regmap_read(eb->rmap, IXP4XX_EXP_TIMING_CS0 +
0194             IXP4XX_EXP_TIMING_STRIDE * cs_index, &cs_cfg);
0195     dev_info(eb->dev, "CS%d at %#08x, size %#08x, config before: %#08x\n",
0196          cs_index, eb->bus_base + IXP4XX_EXP_STRIDE * cs_index,
0197          cur_cssize, cs_cfg);
0198
0199     /* Size set-up first align to 2^9 .. 2^24 */
0200     cur_cssize = roundup_pow_of_two(cur_cssize);
0201     if (cur_cssize < 512)
0202         cur_cssize = 512;
0203     cs_order = ilog2(cur_cssize);
0204     if (cs_order < 9 || cs_order > 24) {
0205         dev_err(eb->dev, "illegal size order %d\n", cs_order);
0206         return;
0207     }
0208     dev_dbg(eb->dev, "CS%d size order: %d\n", cs_index, cs_order);
0209     cs_cfg &= ~(IXP4XX_EXP_SIZE_MASK);
0210     cs_cfg |= ((cs_order - 9) << IXP4XX_EXP_SIZE_SHIFT);
0211
0212     for (i = 0; i < ARRAY_SIZE(ixp4xx_exp_tim_props); i++) {
0213         const struct ixp4xx_exp_tim_prop *ip = &ixp4xx_exp_tim_props[i];
0214
0215         /* All are regular u32 values */
0216         ret = of_property_read_u32(np, ip->prop, &val);
0217         if (ret)
0218             continue;
0219
0220         /* Handle bools (single bits) first */
0221         if (ip->max == 1) {
0222             if (val)
0223                 cs_cfg |= ip->mask;
0224             else
0225                 cs_cfg &= ~ip->mask;
0226             dev_info(eb->dev, "CS%d %s %s\n", cs_index,
0227                  val ? "enabled" : "disabled",
0228                  ip->prop);
0229             continue;
0230         }
0231
0232         if (val > ip->max) {
0233             dev_err(eb->dev,
0234                 "CS%d too high value for %s: %u, capped at %u\n",
0235                 cs_index, ip->prop, val, ip->max);
0236             val = ip->max;
0237         }
0238         /* This assumes max value fills all the assigned bits (and it does) */
0239         cs_cfg &= ~ip->mask;
0240         cs_cfg |= (val << ip->shift);
0241         dev_info(eb->dev, "CS%d set %s to %u\n", cs_index, ip->prop, val);
0242     }
0243
0244     ret = of_property_read_u32(np, "intel,ixp4xx-eb-cycle-type", &val);
0245     if (!ret) {
0246         if (val > 3) {
0247             dev_err(eb->dev, "illegal cycle type %d\n", val);
0248             return;
0249         }
0250         dev_info(eb->dev, "CS%d set cycle type %d\n", cs_index, val);
0251         cs_cfg &= ~IXP4XX_EXP_CYC_TYPE_MASK;
0252         cs_cfg |= val << IXP4XX_EXP_CYC_TYPE_SHIFT;
0253     }
0254
0255     if (eb->is_42x)
0256         cs_cfg &= ~IXP42X_RESERVED;
0257     if (eb->is_43x) {
0258         cs_cfg &= ~IXP43X_RESERVED;
0259         /*
0260          * This bit for Intel strata flash is currently unused, but let's
0261          * report it if we find one.
0262          */
0263         if (cs_cfg & IXP43X_EXP_SYNC_INTEL)
0264             dev_info(eb->dev, "claims to be Intel strata flash\n");
0265     }
0266     cs_cfg |= IXP4XX_EXP_CS_EN;
0267
0268     regmap_write(eb->rmap,
0269              IXP4XX_EXP_TIMING_CS0 + IXP4XX_EXP_TIMING_STRIDE * cs_index,
0270              cs_cfg);
0271     dev_info(eb->dev, "CS%d wrote %#08x into CS config\n", cs_index, cs_cfg);
0272
0273     /*
0274      * If several chip selects are joined together into one big
0275      * device area, we call ourselves recursively for each successive
0276      * chip select. For a 32MB flash chip this results in two calls
0277      * for example.
0278      */
0279     if (cs_size > IXP4XX_EXP_STRIDE)
0280         ixp4xx_exp_setup_chipselect(eb, np,
0281                         cs_index + 1,
0282                         cs_size - IXP4XX_EXP_STRIDE);
0283 }
0284
0285 static void ixp4xx_exp_setup_child(struct ixp4xx_eb *eb,
0286                    struct device_node *np)
0287 {
0288     u32 cs_sizes[IXP4XX_EXP_NUM_CS];
0289     int num_regs;
0290     u32 csindex;
0291     u32 cssize;
0292     int ret;
0293     int i;
0294
0295     num_regs = of_property_count_elems_of_size(np, "reg", IXP4XX_OF_REG_SIZE);
0296     if (num_regs <= 0)
0297         return;
0298     dev_dbg(eb->dev, "child %s has %d register sets\n",
0299         of_node_full_name(np), num_regs);
0300
0301     for (csindex = 0; csindex < IXP4XX_EXP_NUM_CS; csindex++)
0302         cs_sizes[csindex] = 0;
0303
0304     for (i = 0; i < num_regs; i++) {
0305         u32 rbase, rsize;
0306
0307         ret = of_property_read_u32_index(np, "reg",
0308                          i * IXP4XX_OF_REG_SIZE, &csindex);
0309         if (ret)
0310             break;
0311         ret = of_property_read_u32_index(np, "reg",
0312                          i * IXP4XX_OF_REG_SIZE + 1, &rbase);
0313         if (ret)
0314             break;
0315         ret = of_property_read_u32_index(np, "reg",
0316                          i * IXP4XX_OF_REG_SIZE + 2, &rsize);
0317         if (ret)
0318             break;
0319
0320         if (csindex >= IXP4XX_EXP_NUM_CS) {
0321             dev_err(eb->dev, "illegal CS %d\n", csindex);
0322             continue;
0323         }
0324         /*
0325          * The memory window always starts from CS base so we need to add
0326          * the start and size to get to the size from the start of the CS
0327          * base. For example if CS0 is at 0x50000000 and the reg is
0328          * <0 0xe40000 0x40000> the size is e80000.
0329          *
0330          * Roof this if we have several regs setting the same CS.
0331          */
0332         cssize = rbase + rsize;
0333         dev_dbg(eb->dev, "CS%d size %#08x\n", csindex, cssize);
0334         if (cs_sizes[csindex] < cssize)
0335             cs_sizes[csindex] = cssize;
0336     }
0337
0338     for (csindex = 0; csindex < IXP4XX_EXP_NUM_CS; csindex++) {
0339         cssize = cs_sizes[csindex];
0340         if (!cssize)
0341             continue;
0342         /* Just this one, so set it up and return */
0343         ixp4xx_exp_setup_chipselect(eb, np, csindex, cssize);
0344     }
0345 }
0346
0347 static int ixp4xx_exp_probe(struct platform_device *pdev)
0348 {
0349     struct device *dev = &pdev->dev;
0350     struct device_node *np = dev->of_node;
0351     struct ixp4xx_eb *eb;
0352     struct device_node *child;
0353     bool have_children = false;
0354     u32 val;
0355     int ret;
0356
0357     eb = devm_kzalloc(dev, sizeof(*eb), GFP_KERNEL);
0358     if (!eb)
0359         return -ENOMEM;
0360
0361     eb->dev = dev;
0362     eb->is_42x = of_device_is_compatible(np, "intel,ixp42x-expansion-bus-controller");
0363     eb->is_43x = of_device_is_compatible(np, "intel,ixp43x-expansion-bus-controller");
0364
0365     eb->rmap = syscon_node_to_regmap(np);
0366     if (IS_ERR(eb->rmap))
0367         return dev_err_probe(dev, PTR_ERR(eb->rmap), "no regmap\n");
0368
0369     /* We check that the regmap work only on first read */
0370     ret = regmap_read(eb->rmap, IXP4XX_EXP_CNFG0, &val);
0371     if (ret)
0372         return dev_err_probe(dev, ret, "cannot read regmap\n");
0373     if (val & IXP4XX_EXP_CNFG0_MEM_MAP)
0374         eb->bus_base = IXP4XX_EXP_BOOT_BASE;
0375     else
0376         eb->bus_base = IXP4XX_EXP_NORMAL_BASE;
0377     dev_info(dev, "expansion bus at %08x\n", eb->bus_base);
0378
0379     if (eb->is_43x) {
0380         /* Check some fuses */
0381         regmap_read(eb->rmap, IXP43X_EXP_UNIT_FUSE_RESET, &val);
0382         switch (FIELD_GET(IXP43x_EXP_FUSE_SPEED_MASK, val)) {
0383         case 0:
0384             dev_info(dev, "IXP43x at 533 MHz\n");
0385             break;
0386         case 1:
0387             dev_info(dev, "IXP43x at 400 MHz\n");
0388             break;
0389         case 2:
0390             dev_info(dev, "IXP43x at 667 MHz\n");
0391             break;
0392         default:
0393             dev_info(dev, "IXP43x unknown speed\n");
0394             break;
0395         }
0396     }
0397
0398     /* Walk over the child nodes and see what chipselects we use */
0399     for_each_available_child_of_node(np, child) {
0400         ixp4xx_exp_setup_child(eb, child);
0401         /* We have at least one child */
0402         have_children = true;
0403     }
0404
0405     if (have_children)
0406         return of_platform_default_populate(np, NULL, dev);
0407
0408     return 0;
0409 }
0410
0411 static const struct of_device_id ixp4xx_exp_of_match[] = {
0412     { .compatible = "intel,ixp42x-expansion-bus-controller", },
0413     { .compatible = "intel,ixp43x-expansion-bus-controller", },
0414     { .compatible = "intel,ixp45x-expansion-bus-controller", },
0415     { .compatible = "intel,ixp46x-expansion-bus-controller", },
0416     { }
0417 };
0418
0419 static struct platform_driver ixp4xx_exp_driver = {
0420     .probe = ixp4xx_exp_probe,
0421     .driver = {
0422         .name = "intel-extbus",
0423         .of_match_table = ixp4xx_exp_of_match,
0424     },
0425 };
0426 module_platform_driver(ixp4xx_exp_driver);
0427 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
0428 MODULE_DESCRIPTION("Intel IXP4xx external bus driver");
0429 MODULE_LICENSE("GPL");