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0008 #define EDL_PATCH_CMD_OPCODE (0xFC00)
0009 #define EDL_NVM_ACCESS_OPCODE (0xFC0B)
0010 #define EDL_WRITE_BD_ADDR_OPCODE (0xFC14)
0011 #define EDL_PATCH_CMD_LEN (1)
0012 #define EDL_PATCH_VER_REQ_CMD (0x19)
0013 #define EDL_PATCH_TLV_REQ_CMD (0x1E)
0014 #define EDL_GET_BUILD_INFO_CMD (0x20)
0015 #define EDL_NVM_ACCESS_SET_REQ_CMD (0x01)
0016 #define EDL_PATCH_CONFIG_CMD (0x28)
0017 #define MAX_SIZE_PER_TLV_SEGMENT (243)
0018 #define QCA_PRE_SHUTDOWN_CMD (0xFC08)
0019 #define QCA_DISABLE_LOGGING (0xFC17)
0020
0021 #define EDL_CMD_REQ_RES_EVT (0x00)
0022 #define EDL_PATCH_VER_RES_EVT (0x19)
0023 #define EDL_APP_VER_RES_EVT (0x02)
0024 #define EDL_TVL_DNLD_RES_EVT (0x04)
0025 #define EDL_CMD_EXE_STATUS_EVT (0x00)
0026 #define EDL_SET_BAUDRATE_RSP_EVT (0x92)
0027 #define EDL_NVM_ACCESS_CODE_EVT (0x0B)
0028 #define EDL_PATCH_CONFIG_RES_EVT (0x00)
0029 #define QCA_DISABLE_LOGGING_SUB_OP (0x14)
0030
0031 #define EDL_TAG_ID_HCI (17)
0032 #define EDL_TAG_ID_DEEP_SLEEP (27)
0033
0034 #define QCA_WCN3990_POWERON_PULSE 0xFC
0035 #define QCA_WCN3990_POWEROFF_PULSE 0xC0
0036
0037 #define QCA_HCI_CC_OPCODE 0xFC00
0038 #define QCA_HCI_CC_SUCCESS 0x00
0039
0040 #define QCA_WCN3991_SOC_ID (0x40014320)
0041
0042
0043
0044
0045
0046 #define get_soc_ver(soc_id, rom_ver) \
0047 ((le32_to_cpu(soc_id) << 16) | (le16_to_cpu(rom_ver)))
0048
0049 #define QCA_FW_BUILD_VER_LEN 255
0050
0051
0052 enum qca_baudrate {
0053 QCA_BAUDRATE_115200 = 0,
0054 QCA_BAUDRATE_57600,
0055 QCA_BAUDRATE_38400,
0056 QCA_BAUDRATE_19200,
0057 QCA_BAUDRATE_9600,
0058 QCA_BAUDRATE_230400,
0059 QCA_BAUDRATE_250000,
0060 QCA_BAUDRATE_460800,
0061 QCA_BAUDRATE_500000,
0062 QCA_BAUDRATE_720000,
0063 QCA_BAUDRATE_921600,
0064 QCA_BAUDRATE_1000000,
0065 QCA_BAUDRATE_1250000,
0066 QCA_BAUDRATE_2000000,
0067 QCA_BAUDRATE_3000000,
0068 QCA_BAUDRATE_4000000,
0069 QCA_BAUDRATE_1600000,
0070 QCA_BAUDRATE_3200000,
0071 QCA_BAUDRATE_3500000,
0072 QCA_BAUDRATE_AUTO = 0xFE,
0073 QCA_BAUDRATE_RESERVED
0074 };
0075
0076 enum qca_tlv_dnld_mode {
0077 QCA_SKIP_EVT_NONE,
0078 QCA_SKIP_EVT_VSE,
0079 QCA_SKIP_EVT_CC,
0080 QCA_SKIP_EVT_VSE_CC
0081 };
0082
0083 enum qca_tlv_type {
0084 TLV_TYPE_PATCH = 1,
0085 TLV_TYPE_NVM,
0086 ELF_TYPE_PATCH,
0087 };
0088
0089 struct qca_fw_config {
0090 u8 type;
0091 char fwname[64];
0092 uint8_t user_baud_rate;
0093 enum qca_tlv_dnld_mode dnld_mode;
0094 enum qca_tlv_dnld_mode dnld_type;
0095 };
0096
0097 struct edl_event_hdr {
0098 __u8 cresp;
0099 __u8 rtype;
0100 __u8 data[];
0101 } __packed;
0102
0103 struct qca_btsoc_version {
0104 __le32 product_id;
0105 __le16 patch_ver;
0106 __le16 rom_ver;
0107 __le32 soc_id;
0108 } __packed;
0109
0110 struct tlv_seg_resp {
0111 __u8 result;
0112 } __packed;
0113
0114 struct tlv_type_patch {
0115 __le32 total_size;
0116 __le32 data_length;
0117 __u8 format_version;
0118 __u8 signature;
0119 __u8 download_mode;
0120 __u8 reserved1;
0121 __le16 product_id;
0122 __le16 rom_build;
0123 __le16 patch_version;
0124 __le16 reserved2;
0125 __le32 entry;
0126 } __packed;
0127
0128 struct tlv_type_nvm {
0129 __le16 tag_id;
0130 __le16 tag_len;
0131 __le32 reserve1;
0132 __le32 reserve2;
0133 __u8 data[];
0134 } __packed;
0135
0136 struct tlv_type_hdr {
0137 __le32 type_len;
0138 __u8 data[];
0139 } __packed;
0140
0141 enum qca_btsoc_type {
0142 QCA_INVALID = -1,
0143 QCA_AR3002,
0144 QCA_ROME,
0145 QCA_WCN3990,
0146 QCA_WCN3998,
0147 QCA_WCN3991,
0148 QCA_QCA6390,
0149 QCA_WCN6750,
0150 };
0151
0152 #if IS_ENABLED(CONFIG_BT_QCA)
0153
0154 int qca_set_bdaddr_rome(struct hci_dev *hdev, const bdaddr_t *bdaddr);
0155 int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,
0156 enum qca_btsoc_type soc_type, struct qca_btsoc_version ver,
0157 const char *firmware_name);
0158 int qca_read_soc_version(struct hci_dev *hdev, struct qca_btsoc_version *ver,
0159 enum qca_btsoc_type);
0160 int qca_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr);
0161 int qca_send_pre_shutdown_cmd(struct hci_dev *hdev);
0162 static inline bool qca_is_wcn399x(enum qca_btsoc_type soc_type)
0163 {
0164 return soc_type == QCA_WCN3990 || soc_type == QCA_WCN3991 ||
0165 soc_type == QCA_WCN3998;
0166 }
0167 static inline bool qca_is_wcn6750(enum qca_btsoc_type soc_type)
0168 {
0169 return soc_type == QCA_WCN6750;
0170 }
0171
0172 #else
0173
0174 static inline int qca_set_bdaddr_rome(struct hci_dev *hdev, const bdaddr_t *bdaddr)
0175 {
0176 return -EOPNOTSUPP;
0177 }
0178
0179 static inline int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,
0180 enum qca_btsoc_type soc_type,
0181 struct qca_btsoc_version ver,
0182 const char *firmware_name)
0183 {
0184 return -EOPNOTSUPP;
0185 }
0186
0187 static inline int qca_read_soc_version(struct hci_dev *hdev,
0188 struct qca_btsoc_version *ver,
0189 enum qca_btsoc_type)
0190 {
0191 return -EOPNOTSUPP;
0192 }
0193
0194 static inline int qca_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr)
0195 {
0196 return -EOPNOTSUPP;
0197 }
0198
0199 static inline bool qca_is_wcn399x(enum qca_btsoc_type soc_type)
0200 {
0201 return false;
0202 }
0203
0204 static inline bool qca_is_wcn6750(enum qca_btsoc_type soc_type)
0205 {
0206 return false;
0207 }
0208
0209 static inline int qca_send_pre_shutdown_cmd(struct hci_dev *hdev)
0210 {
0211 return -EOPNOTSUPP;
0212 }
0213 #endif