0001
0002
0003
0004 #define FIRMWARE_MT7622 "mediatek/mt7622pr2h.bin"
0005 #define FIRMWARE_MT7663 "mediatek/mt7663pr2h.bin"
0006 #define FIRMWARE_MT7668 "mediatek/mt7668pr2h.bin"
0007 #define FIRMWARE_MT7961 "mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin"
0008
0009 #define HCI_EV_WMT 0xe4
0010 #define HCI_WMT_MAX_EVENT_SIZE 64
0011
0012 #define BTMTK_WMT_REG_WRITE 0x1
0013 #define BTMTK_WMT_REG_READ 0x2
0014
0015 #define MT7921_BTSYS_RST 0x70002610
0016 #define MT7921_BTSYS_RST_WITH_GPIO BIT(7)
0017
0018 #define MT7921_PINMUX_0 0x70005050
0019 #define MT7921_PINMUX_1 0x70005054
0020
0021 #define MT7921_DLSTATUS 0x7c053c10
0022 #define BT_DL_STATE BIT(1)
0023
0024 enum {
0025 BTMTK_WMT_PATCH_DWNLD = 0x1,
0026 BTMTK_WMT_TEST = 0x2,
0027 BTMTK_WMT_WAKEUP = 0x3,
0028 BTMTK_WMT_HIF = 0x4,
0029 BTMTK_WMT_FUNC_CTRL = 0x6,
0030 BTMTK_WMT_RST = 0x7,
0031 BTMTK_WMT_REGISTER = 0x8,
0032 BTMTK_WMT_SEMAPHORE = 0x17,
0033 };
0034
0035 enum {
0036 BTMTK_WMT_INVALID,
0037 BTMTK_WMT_PATCH_UNDONE,
0038 BTMTK_WMT_PATCH_PROGRESS,
0039 BTMTK_WMT_PATCH_DONE,
0040 BTMTK_WMT_ON_UNDONE,
0041 BTMTK_WMT_ON_DONE,
0042 BTMTK_WMT_ON_PROGRESS,
0043 };
0044
0045 struct btmtk_wmt_hdr {
0046 u8 dir;
0047 u8 op;
0048 __le16 dlen;
0049 u8 flag;
0050 } __packed;
0051
0052 struct btmtk_hci_wmt_cmd {
0053 struct btmtk_wmt_hdr hdr;
0054 u8 data[];
0055 } __packed;
0056
0057 struct btmtk_hci_wmt_evt {
0058 struct hci_event_hdr hhdr;
0059 struct btmtk_wmt_hdr whdr;
0060 } __packed;
0061
0062 struct btmtk_hci_wmt_evt_funcc {
0063 struct btmtk_hci_wmt_evt hwhdr;
0064 __be16 status;
0065 } __packed;
0066
0067 struct btmtk_hci_wmt_evt_reg {
0068 struct btmtk_hci_wmt_evt hwhdr;
0069 u8 rsv[2];
0070 u8 num;
0071 __le32 addr;
0072 __le32 val;
0073 } __packed;
0074
0075 struct btmtk_tci_sleep {
0076 u8 mode;
0077 __le16 duration;
0078 __le16 host_duration;
0079 u8 host_wakeup_pin;
0080 u8 time_compensation;
0081 } __packed;
0082
0083 struct btmtk_wakeon {
0084 u8 mode;
0085 u8 gpo;
0086 u8 active_high;
0087 __le16 enable_delay;
0088 __le16 wakeup_delay;
0089 } __packed;
0090
0091 struct btmtk_sco {
0092 u8 clock_config;
0093 u8 transmit_format_config;
0094 u8 channel_format_config;
0095 u8 channel_select_config;
0096 } __packed;
0097
0098 struct reg_read_cmd {
0099 u8 type;
0100 u8 rsv;
0101 u8 num;
0102 __le32 addr;
0103 } __packed;
0104
0105 struct reg_write_cmd {
0106 u8 type;
0107 u8 rsv;
0108 u8 num;
0109 __le32 addr;
0110 __le32 data;
0111 __le32 mask;
0112 } __packed;
0113
0114 struct btmtk_hci_wmt_params {
0115 u8 op;
0116 u8 flag;
0117 u16 dlen;
0118 const void *data;
0119 u32 *status;
0120 };
0121
0122 typedef int (*wmt_cmd_sync_func_t)(struct hci_dev *,
0123 struct btmtk_hci_wmt_params *);
0124
0125 #if IS_ENABLED(CONFIG_BT_MTK)
0126
0127 int btmtk_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr);
0128
0129 int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname,
0130 wmt_cmd_sync_func_t wmt_cmd_sync);
0131
0132 int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname,
0133 wmt_cmd_sync_func_t wmt_cmd_sync);
0134 #else
0135
0136 static inline int btmtk_set_bdaddr(struct hci_dev *hdev,
0137 const bdaddr_t *bdaddr)
0138 {
0139 return -EOPNOTSUPP;
0140 }
0141
0142 static int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname,
0143 wmt_cmd_sync_func_t wmt_cmd_sync)
0144 {
0145 return -EOPNOTSUPP;
0146 }
0147
0148 static int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname,
0149 wmt_cmd_sync_func_t wmt_cmd_sync)
0150 {
0151 return -EOPNOTSUPP;
0152 }
0153
0154 #endif