Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for the SWIM3 (Super Woz Integrated Machine 3)
0004  * floppy controller found on Power Macintoshes.
0005  *
0006  * Copyright (C) 1996 Paul Mackerras.
0007  */
0008 
0009 /*
0010  * TODO:
0011  * handle 2 drives
0012  * handle GCR disks
0013  */
0014 
0015 #undef DEBUG
0016 
0017 #include <linux/stddef.h>
0018 #include <linux/kernel.h>
0019 #include <linux/sched/signal.h>
0020 #include <linux/timer.h>
0021 #include <linux/delay.h>
0022 #include <linux/fd.h>
0023 #include <linux/ioctl.h>
0024 #include <linux/blk-mq.h>
0025 #include <linux/interrupt.h>
0026 #include <linux/mutex.h>
0027 #include <linux/module.h>
0028 #include <linux/spinlock.h>
0029 #include <linux/wait.h>
0030 #include <linux/major.h>
0031 #include <asm/io.h>
0032 #include <asm/dbdma.h>
0033 #include <asm/prom.h>
0034 #include <linux/uaccess.h>
0035 #include <asm/mediabay.h>
0036 #include <asm/machdep.h>
0037 #include <asm/pmac_feature.h>
0038 
0039 #define MAX_FLOPPIES    2
0040 
0041 static DEFINE_MUTEX(swim3_mutex);
0042 static struct gendisk *disks[MAX_FLOPPIES];
0043 
0044 enum swim_state {
0045     idle,
0046     locating,
0047     seeking,
0048     settling,
0049     do_transfer,
0050     jogging,
0051     available,
0052     revalidating,
0053     ejecting
0054 };
0055 
0056 #define REG(x)  unsigned char x; char x ## _pad[15];
0057 
0058 /*
0059  * The names for these registers mostly represent speculation on my part.
0060  * It will be interesting to see how close they are to the names Apple uses.
0061  */
0062 struct swim3 {
0063     REG(data);
0064     REG(timer);     /* counts down at 1MHz */
0065     REG(error);
0066     REG(mode);
0067     REG(select);        /* controls CA0, CA1, CA2 and LSTRB signals */
0068     REG(setup);
0069     REG(control);       /* writing bits clears them */
0070     REG(status);        /* writing bits sets them in control */
0071     REG(intr);
0072     REG(nseek);     /* # tracks to seek */
0073     REG(ctrack);        /* current track number */
0074     REG(csect);     /* current sector number */
0075     REG(gap3);      /* size of gap 3 in track format */
0076     REG(sector);        /* sector # to read or write */
0077     REG(nsect);     /* # sectors to read or write */
0078     REG(intr_enable);
0079 };
0080 
0081 #define control_bic control
0082 #define control_bis status
0083 
0084 /* Bits in select register */
0085 #define CA_MASK     7
0086 #define LSTRB       8
0087 
0088 /* Bits in control register */
0089 #define DO_SEEK     0x80
0090 #define FORMAT      0x40
0091 #define SELECT      0x20
0092 #define WRITE_SECTORS   0x10
0093 #define DO_ACTION   0x08
0094 #define DRIVE2_ENABLE   0x04
0095 #define DRIVE_ENABLE    0x02
0096 #define INTR_ENABLE 0x01
0097 
0098 /* Bits in status register */
0099 #define FIFO_1BYTE  0x80
0100 #define FIFO_2BYTE  0x40
0101 #define ERROR       0x20
0102 #define DATA        0x08
0103 #define RDDATA      0x04
0104 #define INTR_PENDING    0x02
0105 #define MARK_BYTE   0x01
0106 
0107 /* Bits in intr and intr_enable registers */
0108 #define ERROR_INTR  0x20
0109 #define DATA_CHANGED    0x10
0110 #define TRANSFER_DONE   0x08
0111 #define SEEN_SECTOR 0x04
0112 #define SEEK_DONE   0x02
0113 #define TIMER_DONE  0x01
0114 
0115 /* Bits in error register */
0116 #define ERR_DATA_CRC    0x80
0117 #define ERR_ADDR_CRC    0x40
0118 #define ERR_OVERRUN 0x04
0119 #define ERR_UNDERRUN    0x01
0120 
0121 /* Bits in setup register */
0122 #define S_SW_RESET  0x80
0123 #define S_GCR_WRITE 0x40
0124 #define S_IBM_DRIVE 0x20
0125 #define S_TEST_MODE 0x10
0126 #define S_FCLK_DIV2 0x08
0127 #define S_GCR       0x04
0128 #define S_COPY_PROT 0x02
0129 #define S_INV_WDATA 0x01
0130 
0131 /* Select values for swim3_action */
0132 #define SEEK_POSITIVE   0
0133 #define SEEK_NEGATIVE   4
0134 #define STEP        1
0135 #define MOTOR_ON    2
0136 #define MOTOR_OFF   6
0137 #define INDEX       3
0138 #define EJECT       7
0139 #define SETMFM      9
0140 #define SETGCR      13
0141 
0142 /* Select values for swim3_select and swim3_readbit */
0143 #define STEP_DIR    0
0144 #define STEPPING    1
0145 #define MOTOR_ON    2
0146 #define RELAX       3   /* also eject in progress */
0147 #define READ_DATA_0 4
0148 #define ONEMEG_DRIVE    5
0149 #define SINGLE_SIDED    6   /* drive or diskette is 4MB type? */
0150 #define DRIVE_PRESENT   7
0151 #define DISK_IN     8
0152 #define WRITE_PROT  9
0153 #define TRACK_ZERO  10
0154 #define TACHO       11
0155 #define READ_DATA_1 12
0156 #define GCR_MODE    13
0157 #define SEEK_COMPLETE   14
0158 #define TWOMEG_MEDIA    15
0159 
0160 /* Definitions of values used in writing and formatting */
0161 #define DATA_ESCAPE 0x99
0162 #define GCR_SYNC_EXC    0x3f
0163 #define GCR_SYNC_CONV   0x80
0164 #define GCR_FIRST_MARK  0xd5
0165 #define GCR_SECOND_MARK 0xaa
0166 #define GCR_ADDR_MARK   "\xd5\xaa\x00"
0167 #define GCR_DATA_MARK   "\xd5\xaa\x0b"
0168 #define GCR_SLIP_BYTE   "\x27\xaa"
0169 #define GCR_SELF_SYNC   "\x3f\xbf\x1e\x34\x3c\x3f"
0170 
0171 #define DATA_99     "\x99\x99"
0172 #define MFM_ADDR_MARK   "\x99\xa1\x99\xa1\x99\xa1\x99\xfe"
0173 #define MFM_INDEX_MARK  "\x99\xc2\x99\xc2\x99\xc2\x99\xfc"
0174 #define MFM_GAP_LEN 12
0175 
0176 struct floppy_state {
0177     enum swim_state state;
0178     struct swim3 __iomem *swim3;    /* hardware registers */
0179     struct dbdma_regs __iomem *dma; /* DMA controller registers */
0180     int swim3_intr; /* interrupt number for SWIM3 */
0181     int dma_intr;   /* interrupt number for DMA channel */
0182     int cur_cyl;    /* cylinder head is on, or -1 */
0183     int cur_sector; /* last sector we saw go past */
0184     int req_cyl;    /* the cylinder for the current r/w request */
0185     int head;       /* head number ditto */
0186     int req_sector; /* sector number ditto */
0187     int scount;     /* # sectors we're transferring at present */
0188     int retries;
0189     int settle_time;
0190     int secpercyl;  /* disk geometry information */
0191     int secpertrack;
0192     int total_secs;
0193     int write_prot; /* 1 if write-protected, 0 if not, -1 dunno */
0194     struct dbdma_cmd *dma_cmd;
0195     int ref_count;
0196     int expect_cyl;
0197     struct timer_list timeout;
0198     int timeout_pending;
0199     int ejected;
0200     wait_queue_head_t wait;
0201     int wanted;
0202     struct macio_dev *mdev;
0203     char    dbdma_cmd_space[5 * sizeof(struct dbdma_cmd)];
0204     int index;
0205     struct request *cur_req;
0206     struct blk_mq_tag_set tag_set;
0207 };
0208 
0209 #define swim3_err(fmt, arg...)  dev_err(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
0210 #define swim3_warn(fmt, arg...) dev_warn(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
0211 #define swim3_info(fmt, arg...) dev_info(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
0212 
0213 #ifdef DEBUG
0214 #define swim3_dbg(fmt, arg...)  dev_dbg(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
0215 #else
0216 #define swim3_dbg(fmt, arg...)  do { } while(0)
0217 #endif
0218 
0219 static struct floppy_state floppy_states[MAX_FLOPPIES];
0220 static int floppy_count = 0;
0221 static DEFINE_SPINLOCK(swim3_lock);
0222 
0223 static unsigned short write_preamble[] = {
0224     0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, /* gap field */
0225     0, 0, 0, 0, 0, 0,           /* sync field */
0226     0x99a1, 0x99a1, 0x99a1, 0x99fb,     /* data address mark */
0227     0x990f                  /* no escape for 512 bytes */
0228 };
0229 
0230 static unsigned short write_postamble[] = {
0231     0x9904,                 /* insert CRC */
0232     0x4e4e, 0x4e4e,
0233     0x9908,                 /* stop writing */
0234     0, 0, 0, 0, 0, 0
0235 };
0236 
0237 static void seek_track(struct floppy_state *fs, int n);
0238 static void act(struct floppy_state *fs);
0239 static void scan_timeout(struct timer_list *t);
0240 static void seek_timeout(struct timer_list *t);
0241 static void settle_timeout(struct timer_list *t);
0242 static void xfer_timeout(struct timer_list *t);
0243 static irqreturn_t swim3_interrupt(int irq, void *dev_id);
0244 /*static void fd_dma_interrupt(int irq, void *dev_id);*/
0245 static int grab_drive(struct floppy_state *fs, enum swim_state state,
0246               int interruptible);
0247 static void release_drive(struct floppy_state *fs);
0248 static int fd_eject(struct floppy_state *fs);
0249 static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
0250             unsigned int cmd, unsigned long param);
0251 static int floppy_open(struct block_device *bdev, fmode_t mode);
0252 static void floppy_release(struct gendisk *disk, fmode_t mode);
0253 static unsigned int floppy_check_events(struct gendisk *disk,
0254                     unsigned int clearing);
0255 static int floppy_revalidate(struct gendisk *disk);
0256 
0257 static bool swim3_end_request(struct floppy_state *fs, blk_status_t err, unsigned int nr_bytes)
0258 {
0259     struct request *req = fs->cur_req;
0260 
0261     swim3_dbg("  end request, err=%d nr_bytes=%d, cur_req=%p\n",
0262           err, nr_bytes, req);
0263 
0264     if (err)
0265         nr_bytes = blk_rq_cur_bytes(req);
0266     if (blk_update_request(req, err, nr_bytes))
0267         return true;
0268     __blk_mq_end_request(req, err);
0269     fs->cur_req = NULL;
0270     return false;
0271 }
0272 
0273 static void swim3_select(struct floppy_state *fs, int sel)
0274 {
0275     struct swim3 __iomem *sw = fs->swim3;
0276 
0277     out_8(&sw->select, RELAX);
0278     if (sel & 8)
0279         out_8(&sw->control_bis, SELECT);
0280     else
0281         out_8(&sw->control_bic, SELECT);
0282     out_8(&sw->select, sel & CA_MASK);
0283 }
0284 
0285 static void swim3_action(struct floppy_state *fs, int action)
0286 {
0287     struct swim3 __iomem *sw = fs->swim3;
0288 
0289     swim3_select(fs, action);
0290     udelay(1);
0291     out_8(&sw->select, sw->select | LSTRB);
0292     udelay(2);
0293     out_8(&sw->select, sw->select & ~LSTRB);
0294     udelay(1);
0295 }
0296 
0297 static int swim3_readbit(struct floppy_state *fs, int bit)
0298 {
0299     struct swim3 __iomem *sw = fs->swim3;
0300     int stat;
0301 
0302     swim3_select(fs, bit);
0303     udelay(1);
0304     stat = in_8(&sw->status);
0305     return (stat & DATA) == 0;
0306 }
0307 
0308 static blk_status_t swim3_queue_rq(struct blk_mq_hw_ctx *hctx,
0309                    const struct blk_mq_queue_data *bd)
0310 {
0311     struct floppy_state *fs = hctx->queue->queuedata;
0312     struct request *req = bd->rq;
0313     unsigned long x;
0314 
0315     spin_lock_irq(&swim3_lock);
0316     if (fs->cur_req || fs->state != idle) {
0317         spin_unlock_irq(&swim3_lock);
0318         return BLK_STS_DEV_RESOURCE;
0319     }
0320     blk_mq_start_request(req);
0321     fs->cur_req = req;
0322     if (fs->mdev->media_bay &&
0323         check_media_bay(fs->mdev->media_bay) != MB_FD) {
0324         swim3_dbg("%s", "  media bay absent, dropping req\n");
0325         swim3_end_request(fs, BLK_STS_IOERR, 0);
0326         goto out;
0327     }
0328     if (fs->ejected) {
0329         swim3_dbg("%s", "  disk ejected\n");
0330         swim3_end_request(fs, BLK_STS_IOERR, 0);
0331         goto out;
0332     }
0333     if (rq_data_dir(req) == WRITE) {
0334         if (fs->write_prot < 0)
0335             fs->write_prot = swim3_readbit(fs, WRITE_PROT);
0336         if (fs->write_prot) {
0337             swim3_dbg("%s", "  try to write, disk write protected\n");
0338             swim3_end_request(fs, BLK_STS_IOERR, 0);
0339             goto out;
0340         }
0341     }
0342 
0343     /*
0344      * Do not remove the cast. blk_rq_pos(req) is now a sector_t and can be
0345      * 64 bits, but it will never go past 32 bits for this driver anyway, so
0346      * we can safely cast it down and not have to do a 64/32 division
0347      */
0348     fs->req_cyl = ((long)blk_rq_pos(req)) / fs->secpercyl;
0349     x = ((long)blk_rq_pos(req)) % fs->secpercyl;
0350     fs->head = x / fs->secpertrack;
0351     fs->req_sector = x % fs->secpertrack + 1;
0352     fs->state = do_transfer;
0353     fs->retries = 0;
0354 
0355     act(fs);
0356 
0357 out:
0358     spin_unlock_irq(&swim3_lock);
0359     return BLK_STS_OK;
0360 }
0361 
0362 static void set_timeout(struct floppy_state *fs, int nticks,
0363             void (*proc)(struct timer_list *t))
0364 {
0365     if (fs->timeout_pending)
0366         del_timer(&fs->timeout);
0367     fs->timeout.expires = jiffies + nticks;
0368     fs->timeout.function = proc;
0369     add_timer(&fs->timeout);
0370     fs->timeout_pending = 1;
0371 }
0372 
0373 static inline void scan_track(struct floppy_state *fs)
0374 {
0375     struct swim3 __iomem *sw = fs->swim3;
0376 
0377     swim3_select(fs, READ_DATA_0);
0378     in_8(&sw->intr);        /* clear SEEN_SECTOR bit */
0379     in_8(&sw->error);
0380     out_8(&sw->intr_enable, SEEN_SECTOR);
0381     out_8(&sw->control_bis, DO_ACTION);
0382     /* enable intr when track found */
0383     set_timeout(fs, HZ, scan_timeout);  /* enable timeout */
0384 }
0385 
0386 static inline void seek_track(struct floppy_state *fs, int n)
0387 {
0388     struct swim3 __iomem *sw = fs->swim3;
0389 
0390     if (n >= 0) {
0391         swim3_action(fs, SEEK_POSITIVE);
0392         sw->nseek = n;
0393     } else {
0394         swim3_action(fs, SEEK_NEGATIVE);
0395         sw->nseek = -n;
0396     }
0397     fs->expect_cyl = (fs->cur_cyl >= 0)? fs->cur_cyl + n: -1;
0398     swim3_select(fs, STEP);
0399     in_8(&sw->error);
0400     /* enable intr when seek finished */
0401     out_8(&sw->intr_enable, SEEK_DONE);
0402     out_8(&sw->control_bis, DO_SEEK);
0403     set_timeout(fs, 3*HZ, seek_timeout);    /* enable timeout */
0404     fs->settle_time = 0;
0405 }
0406 
0407 /*
0408  * XXX: this is a horrible hack, but at least allows ppc32 to get
0409  * out of defining virt_to_bus, and this driver out of using the
0410  * deprecated block layer bounce buffering for highmem addresses
0411  * for no good reason.
0412  */
0413 static unsigned long swim3_phys_to_bus(phys_addr_t paddr)
0414 {
0415     return paddr + PCI_DRAM_OFFSET;
0416 }
0417 
0418 static phys_addr_t swim3_bio_phys(struct bio *bio)
0419 {
0420     return page_to_phys(bio_page(bio)) + bio_offset(bio);
0421 }
0422 
0423 static inline void init_dma(struct dbdma_cmd *cp, int cmd,
0424                 phys_addr_t paddr, int count)
0425 {
0426     cp->req_count = cpu_to_le16(count);
0427     cp->command = cpu_to_le16(cmd);
0428     cp->phy_addr = cpu_to_le32(swim3_phys_to_bus(paddr));
0429     cp->xfer_status = 0;
0430 }
0431 
0432 static inline void setup_transfer(struct floppy_state *fs)
0433 {
0434     int n;
0435     struct swim3 __iomem *sw = fs->swim3;
0436     struct dbdma_cmd *cp = fs->dma_cmd;
0437     struct dbdma_regs __iomem *dr = fs->dma;
0438     struct request *req = fs->cur_req;
0439 
0440     if (blk_rq_cur_sectors(req) <= 0) {
0441         swim3_warn("%s", "Transfer 0 sectors ?\n");
0442         return;
0443     }
0444     if (rq_data_dir(req) == WRITE)
0445         n = 1;
0446     else {
0447         n = fs->secpertrack - fs->req_sector + 1;
0448         if (n > blk_rq_cur_sectors(req))
0449             n = blk_rq_cur_sectors(req);
0450     }
0451 
0452     swim3_dbg("  setup xfer at sect %d (of %d) head %d for %d\n",
0453           fs->req_sector, fs->secpertrack, fs->head, n);
0454 
0455     fs->scount = n;
0456     swim3_select(fs, fs->head? READ_DATA_1: READ_DATA_0);
0457     out_8(&sw->sector, fs->req_sector);
0458     out_8(&sw->nsect, n);
0459     out_8(&sw->gap3, 0);
0460     out_le32(&dr->cmdptr, swim3_phys_to_bus(virt_to_phys(cp)));
0461     if (rq_data_dir(req) == WRITE) {
0462         /* Set up 3 dma commands: write preamble, data, postamble */
0463         init_dma(cp, OUTPUT_MORE, virt_to_phys(write_preamble),
0464              sizeof(write_preamble));
0465         ++cp;
0466         init_dma(cp, OUTPUT_MORE, swim3_bio_phys(req->bio), 512);
0467         ++cp;
0468         init_dma(cp, OUTPUT_LAST, virt_to_phys(write_postamble),
0469             sizeof(write_postamble));
0470     } else {
0471         init_dma(cp, INPUT_LAST, swim3_bio_phys(req->bio), n * 512);
0472     }
0473     ++cp;
0474     out_le16(&cp->command, DBDMA_STOP);
0475     out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
0476     in_8(&sw->error);
0477     out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
0478     if (rq_data_dir(req) == WRITE)
0479         out_8(&sw->control_bis, WRITE_SECTORS);
0480     in_8(&sw->intr);
0481     out_le32(&dr->control, (RUN << 16) | RUN);
0482     /* enable intr when transfer complete */
0483     out_8(&sw->intr_enable, TRANSFER_DONE);
0484     out_8(&sw->control_bis, DO_ACTION);
0485     set_timeout(fs, 2*HZ, xfer_timeout);    /* enable timeout */
0486 }
0487 
0488 static void act(struct floppy_state *fs)
0489 {
0490     for (;;) {
0491         swim3_dbg("  act loop, state=%d, req_cyl=%d, cur_cyl=%d\n",
0492               fs->state, fs->req_cyl, fs->cur_cyl);
0493 
0494         switch (fs->state) {
0495         case idle:
0496             return;     /* XXX shouldn't get here */
0497 
0498         case locating:
0499             if (swim3_readbit(fs, TRACK_ZERO)) {
0500                 swim3_dbg("%s", "    locate track 0\n");
0501                 fs->cur_cyl = 0;
0502                 if (fs->req_cyl == 0)
0503                     fs->state = do_transfer;
0504                 else
0505                     fs->state = seeking;
0506                 break;
0507             }
0508             scan_track(fs);
0509             return;
0510 
0511         case seeking:
0512             if (fs->cur_cyl < 0) {
0513                 fs->expect_cyl = -1;
0514                 fs->state = locating;
0515                 break;
0516             }
0517             if (fs->req_cyl == fs->cur_cyl) {
0518                 swim3_warn("%s", "Whoops, seeking 0\n");
0519                 fs->state = do_transfer;
0520                 break;
0521             }
0522             seek_track(fs, fs->req_cyl - fs->cur_cyl);
0523             return;
0524 
0525         case settling:
0526             /* check for SEEK_COMPLETE after 30ms */
0527             fs->settle_time = (HZ + 32) / 33;
0528             set_timeout(fs, fs->settle_time, settle_timeout);
0529             return;
0530 
0531         case do_transfer:
0532             if (fs->cur_cyl != fs->req_cyl) {
0533                 if (fs->retries > 5) {
0534                     swim3_err("Wrong cylinder in transfer, want: %d got %d\n",
0535                           fs->req_cyl, fs->cur_cyl);
0536                     swim3_end_request(fs, BLK_STS_IOERR, 0);
0537                     fs->state = idle;
0538                     return;
0539                 }
0540                 fs->state = seeking;
0541                 break;
0542             }
0543             setup_transfer(fs);
0544             return;
0545 
0546         case jogging:
0547             seek_track(fs, -5);
0548             return;
0549 
0550         default:
0551             swim3_err("Unknown state %d\n", fs->state);
0552             return;
0553         }
0554     }
0555 }
0556 
0557 static void scan_timeout(struct timer_list *t)
0558 {
0559     struct floppy_state *fs = from_timer(fs, t, timeout);
0560     struct swim3 __iomem *sw = fs->swim3;
0561     unsigned long flags;
0562 
0563     swim3_dbg("* scan timeout, state=%d\n", fs->state);
0564 
0565     spin_lock_irqsave(&swim3_lock, flags);
0566     fs->timeout_pending = 0;
0567     out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
0568     out_8(&sw->select, RELAX);
0569     out_8(&sw->intr_enable, 0);
0570     fs->cur_cyl = -1;
0571     if (fs->retries > 5) {
0572         swim3_end_request(fs, BLK_STS_IOERR, 0);
0573         fs->state = idle;
0574     } else {
0575         fs->state = jogging;
0576         act(fs);
0577     }
0578     spin_unlock_irqrestore(&swim3_lock, flags);
0579 }
0580 
0581 static void seek_timeout(struct timer_list *t)
0582 {
0583     struct floppy_state *fs = from_timer(fs, t, timeout);
0584     struct swim3 __iomem *sw = fs->swim3;
0585     unsigned long flags;
0586 
0587     swim3_dbg("* seek timeout, state=%d\n", fs->state);
0588 
0589     spin_lock_irqsave(&swim3_lock, flags);
0590     fs->timeout_pending = 0;
0591     out_8(&sw->control_bic, DO_SEEK);
0592     out_8(&sw->select, RELAX);
0593     out_8(&sw->intr_enable, 0);
0594     swim3_err("%s", "Seek timeout\n");
0595     swim3_end_request(fs, BLK_STS_IOERR, 0);
0596     fs->state = idle;
0597     spin_unlock_irqrestore(&swim3_lock, flags);
0598 }
0599 
0600 static void settle_timeout(struct timer_list *t)
0601 {
0602     struct floppy_state *fs = from_timer(fs, t, timeout);
0603     struct swim3 __iomem *sw = fs->swim3;
0604     unsigned long flags;
0605 
0606     swim3_dbg("* settle timeout, state=%d\n", fs->state);
0607 
0608     spin_lock_irqsave(&swim3_lock, flags);
0609     fs->timeout_pending = 0;
0610     if (swim3_readbit(fs, SEEK_COMPLETE)) {
0611         out_8(&sw->select, RELAX);
0612         fs->state = locating;
0613         act(fs);
0614         goto unlock;
0615     }
0616     out_8(&sw->select, RELAX);
0617     if (fs->settle_time < 2*HZ) {
0618         ++fs->settle_time;
0619         set_timeout(fs, 1, settle_timeout);
0620         goto unlock;
0621     }
0622     swim3_err("%s", "Seek settle timeout\n");
0623     swim3_end_request(fs, BLK_STS_IOERR, 0);
0624     fs->state = idle;
0625  unlock:
0626     spin_unlock_irqrestore(&swim3_lock, flags);
0627 }
0628 
0629 static void xfer_timeout(struct timer_list *t)
0630 {
0631     struct floppy_state *fs = from_timer(fs, t, timeout);
0632     struct swim3 __iomem *sw = fs->swim3;
0633     struct dbdma_regs __iomem *dr = fs->dma;
0634     unsigned long flags;
0635     int n;
0636 
0637     swim3_dbg("* xfer timeout, state=%d\n", fs->state);
0638 
0639     spin_lock_irqsave(&swim3_lock, flags);
0640     fs->timeout_pending = 0;
0641     out_le32(&dr->control, RUN << 16);
0642     /* We must wait a bit for dbdma to stop */
0643     for (n = 0; (in_le32(&dr->status) & ACTIVE) && n < 1000; n++)
0644         udelay(1);
0645     out_8(&sw->intr_enable, 0);
0646     out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION);
0647     out_8(&sw->select, RELAX);
0648     swim3_err("Timeout %sing sector %ld\n",
0649            (rq_data_dir(fs->cur_req)==WRITE? "writ": "read"),
0650            (long)blk_rq_pos(fs->cur_req));
0651     swim3_end_request(fs, BLK_STS_IOERR, 0);
0652     fs->state = idle;
0653     spin_unlock_irqrestore(&swim3_lock, flags);
0654 }
0655 
0656 static irqreturn_t swim3_interrupt(int irq, void *dev_id)
0657 {
0658     struct floppy_state *fs = (struct floppy_state *) dev_id;
0659     struct swim3 __iomem *sw = fs->swim3;
0660     int intr, err, n;
0661     int stat, resid;
0662     struct dbdma_regs __iomem *dr;
0663     struct dbdma_cmd *cp;
0664     unsigned long flags;
0665     struct request *req = fs->cur_req;
0666 
0667     swim3_dbg("* interrupt, state=%d\n", fs->state);
0668 
0669     spin_lock_irqsave(&swim3_lock, flags);
0670     intr = in_8(&sw->intr);
0671     err = (intr & ERROR_INTR)? in_8(&sw->error): 0;
0672     if ((intr & ERROR_INTR) && fs->state != do_transfer)
0673         swim3_err("Non-transfer error interrupt: state=%d, dir=%x, intr=%x, err=%x\n",
0674               fs->state, rq_data_dir(req), intr, err);
0675     switch (fs->state) {
0676     case locating:
0677         if (intr & SEEN_SECTOR) {
0678             out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
0679             out_8(&sw->select, RELAX);
0680             out_8(&sw->intr_enable, 0);
0681             del_timer(&fs->timeout);
0682             fs->timeout_pending = 0;
0683             if (sw->ctrack == 0xff) {
0684                 swim3_err("%s", "Seen sector but cyl=ff?\n");
0685                 fs->cur_cyl = -1;
0686                 if (fs->retries > 5) {
0687                     swim3_end_request(fs, BLK_STS_IOERR, 0);
0688                     fs->state = idle;
0689                 } else {
0690                     fs->state = jogging;
0691                     act(fs);
0692                 }
0693                 break;
0694             }
0695             fs->cur_cyl = sw->ctrack;
0696             fs->cur_sector = sw->csect;
0697             if (fs->expect_cyl != -1 && fs->expect_cyl != fs->cur_cyl)
0698                 swim3_err("Expected cyl %d, got %d\n",
0699                       fs->expect_cyl, fs->cur_cyl);
0700             fs->state = do_transfer;
0701             act(fs);
0702         }
0703         break;
0704     case seeking:
0705     case jogging:
0706         if (sw->nseek == 0) {
0707             out_8(&sw->control_bic, DO_SEEK);
0708             out_8(&sw->select, RELAX);
0709             out_8(&sw->intr_enable, 0);
0710             del_timer(&fs->timeout);
0711             fs->timeout_pending = 0;
0712             if (fs->state == seeking)
0713                 ++fs->retries;
0714             fs->state = settling;
0715             act(fs);
0716         }
0717         break;
0718     case settling:
0719         out_8(&sw->intr_enable, 0);
0720         del_timer(&fs->timeout);
0721         fs->timeout_pending = 0;
0722         act(fs);
0723         break;
0724     case do_transfer:
0725         if ((intr & (ERROR_INTR | TRANSFER_DONE)) == 0)
0726             break;
0727         out_8(&sw->intr_enable, 0);
0728         out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION);
0729         out_8(&sw->select, RELAX);
0730         del_timer(&fs->timeout);
0731         fs->timeout_pending = 0;
0732         dr = fs->dma;
0733         cp = fs->dma_cmd;
0734         if (rq_data_dir(req) == WRITE)
0735             ++cp;
0736         /*
0737          * Check that the main data transfer has finished.
0738          * On writing, the swim3 sometimes doesn't use
0739          * up all the bytes of the postamble, so we can still
0740          * see DMA active here.  That doesn't matter as long
0741          * as all the sector data has been transferred.
0742          */
0743         if ((intr & ERROR_INTR) == 0 && cp->xfer_status == 0) {
0744             /* wait a little while for DMA to complete */
0745             for (n = 0; n < 100; ++n) {
0746                 if (cp->xfer_status != 0)
0747                     break;
0748                 udelay(1);
0749                 barrier();
0750             }
0751         }
0752         /* turn off DMA */
0753         out_le32(&dr->control, (RUN | PAUSE) << 16);
0754         stat = le16_to_cpu(cp->xfer_status);
0755         resid = le16_to_cpu(cp->res_count);
0756         if (intr & ERROR_INTR) {
0757             n = fs->scount - 1 - resid / 512;
0758             if (n > 0) {
0759                 blk_update_request(req, 0, n << 9);
0760                 fs->req_sector += n;
0761             }
0762             if (fs->retries < 5) {
0763                 ++fs->retries;
0764                 act(fs);
0765             } else {
0766                 swim3_err("Error %sing block %ld (err=%x)\n",
0767                        rq_data_dir(req) == WRITE? "writ": "read",
0768                        (long)blk_rq_pos(req), err);
0769                 swim3_end_request(fs, BLK_STS_IOERR, 0);
0770                 fs->state = idle;
0771             }
0772         } else {
0773             if ((stat & ACTIVE) == 0 || resid != 0) {
0774                 /* musta been an error */
0775                 swim3_err("fd dma error: stat=%x resid=%d\n", stat, resid);
0776                 swim3_err("  state=%d, dir=%x, intr=%x, err=%x\n",
0777                       fs->state, rq_data_dir(req), intr, err);
0778                 swim3_end_request(fs, BLK_STS_IOERR, 0);
0779                 fs->state = idle;
0780                 break;
0781             }
0782             fs->retries = 0;
0783             if (swim3_end_request(fs, 0, fs->scount << 9)) {
0784                 fs->req_sector += fs->scount;
0785                 if (fs->req_sector > fs->secpertrack) {
0786                     fs->req_sector -= fs->secpertrack;
0787                     if (++fs->head > 1) {
0788                         fs->head = 0;
0789                         ++fs->req_cyl;
0790                     }
0791                 }
0792                 act(fs);
0793             } else
0794                 fs->state = idle;
0795         }
0796         break;
0797     default:
0798         swim3_err("Don't know what to do in state %d\n", fs->state);
0799     }
0800     spin_unlock_irqrestore(&swim3_lock, flags);
0801     return IRQ_HANDLED;
0802 }
0803 
0804 /*
0805 static void fd_dma_interrupt(int irq, void *dev_id)
0806 {
0807 }
0808 */
0809 
0810 /* Called under the mutex to grab exclusive access to a drive */
0811 static int grab_drive(struct floppy_state *fs, enum swim_state state,
0812               int interruptible)
0813 {
0814     unsigned long flags;
0815 
0816     swim3_dbg("%s", "-> grab drive\n");
0817 
0818     spin_lock_irqsave(&swim3_lock, flags);
0819     if (fs->state != idle && fs->state != available) {
0820         ++fs->wanted;
0821         /* this will enable irqs in order to sleep */
0822         if (!interruptible)
0823             wait_event_lock_irq(fs->wait,
0824                                         fs->state == available,
0825                                         swim3_lock);
0826         else if (wait_event_interruptible_lock_irq(fs->wait,
0827                     fs->state == available,
0828                     swim3_lock)) {
0829             --fs->wanted;
0830             spin_unlock_irqrestore(&swim3_lock, flags);
0831             return -EINTR;
0832         }
0833         --fs->wanted;
0834     }
0835     fs->state = state;
0836     spin_unlock_irqrestore(&swim3_lock, flags);
0837 
0838     return 0;
0839 }
0840 
0841 static void release_drive(struct floppy_state *fs)
0842 {
0843     struct request_queue *q = disks[fs->index]->queue;
0844     unsigned long flags;
0845 
0846     swim3_dbg("%s", "-> release drive\n");
0847 
0848     spin_lock_irqsave(&swim3_lock, flags);
0849     fs->state = idle;
0850     spin_unlock_irqrestore(&swim3_lock, flags);
0851 
0852     blk_mq_freeze_queue(q);
0853     blk_mq_quiesce_queue(q);
0854     blk_mq_unquiesce_queue(q);
0855     blk_mq_unfreeze_queue(q);
0856 }
0857 
0858 static int fd_eject(struct floppy_state *fs)
0859 {
0860     int err, n;
0861 
0862     err = grab_drive(fs, ejecting, 1);
0863     if (err)
0864         return err;
0865     swim3_action(fs, EJECT);
0866     for (n = 20; n > 0; --n) {
0867         if (signal_pending(current)) {
0868             err = -EINTR;
0869             break;
0870         }
0871         swim3_select(fs, RELAX);
0872         schedule_timeout_interruptible(1);
0873         if (swim3_readbit(fs, DISK_IN) == 0)
0874             break;
0875     }
0876     swim3_select(fs, RELAX);
0877     udelay(150);
0878     fs->ejected = 1;
0879     release_drive(fs);
0880     return err;
0881 }
0882 
0883 static struct floppy_struct floppy_type =
0884     { 2880,18,2,80,0,0x1B,0x00,0xCF,0x6C,NULL };    /*  7 1.44MB 3.5"   */
0885 
0886 static int floppy_locked_ioctl(struct block_device *bdev, fmode_t mode,
0887             unsigned int cmd, unsigned long param)
0888 {
0889     struct floppy_state *fs = bdev->bd_disk->private_data;
0890     int err;
0891         
0892     if ((cmd & 0x80) && !capable(CAP_SYS_ADMIN))
0893         return -EPERM;
0894 
0895     if (fs->mdev->media_bay &&
0896         check_media_bay(fs->mdev->media_bay) != MB_FD)
0897         return -ENXIO;
0898 
0899     switch (cmd) {
0900     case FDEJECT:
0901         if (fs->ref_count != 1)
0902             return -EBUSY;
0903         err = fd_eject(fs);
0904         return err;
0905     case FDGETPRM:
0906             if (copy_to_user((void __user *) param, &floppy_type,
0907                  sizeof(struct floppy_struct)))
0908             return -EFAULT;
0909         return 0;
0910     }
0911     return -ENOTTY;
0912 }
0913 
0914 static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
0915                  unsigned int cmd, unsigned long param)
0916 {
0917     int ret;
0918 
0919     mutex_lock(&swim3_mutex);
0920     ret = floppy_locked_ioctl(bdev, mode, cmd, param);
0921     mutex_unlock(&swim3_mutex);
0922 
0923     return ret;
0924 }
0925 
0926 static int floppy_open(struct block_device *bdev, fmode_t mode)
0927 {
0928     struct floppy_state *fs = bdev->bd_disk->private_data;
0929     struct swim3 __iomem *sw = fs->swim3;
0930     int n, err = 0;
0931 
0932     if (fs->ref_count == 0) {
0933         if (fs->mdev->media_bay &&
0934             check_media_bay(fs->mdev->media_bay) != MB_FD)
0935             return -ENXIO;
0936         out_8(&sw->setup, S_IBM_DRIVE | S_FCLK_DIV2);
0937         out_8(&sw->control_bic, 0xff);
0938         out_8(&sw->mode, 0x95);
0939         udelay(10);
0940         out_8(&sw->intr_enable, 0);
0941         out_8(&sw->control_bis, DRIVE_ENABLE | INTR_ENABLE);
0942         swim3_action(fs, MOTOR_ON);
0943         fs->write_prot = -1;
0944         fs->cur_cyl = -1;
0945         for (n = 0; n < 2 * HZ; ++n) {
0946             if (n >= HZ/30 && swim3_readbit(fs, SEEK_COMPLETE))
0947                 break;
0948             if (signal_pending(current)) {
0949                 err = -EINTR;
0950                 break;
0951             }
0952             swim3_select(fs, RELAX);
0953             schedule_timeout_interruptible(1);
0954         }
0955         if (err == 0 && (swim3_readbit(fs, SEEK_COMPLETE) == 0
0956                  || swim3_readbit(fs, DISK_IN) == 0))
0957             err = -ENXIO;
0958         swim3_action(fs, SETMFM);
0959         swim3_select(fs, RELAX);
0960 
0961     } else if (fs->ref_count == -1 || mode & FMODE_EXCL)
0962         return -EBUSY;
0963 
0964     if (err == 0 && (mode & FMODE_NDELAY) == 0
0965         && (mode & (FMODE_READ|FMODE_WRITE))) {
0966         if (bdev_check_media_change(bdev))
0967             floppy_revalidate(bdev->bd_disk);
0968         if (fs->ejected)
0969             err = -ENXIO;
0970     }
0971 
0972     if (err == 0 && (mode & FMODE_WRITE)) {
0973         if (fs->write_prot < 0)
0974             fs->write_prot = swim3_readbit(fs, WRITE_PROT);
0975         if (fs->write_prot)
0976             err = -EROFS;
0977     }
0978 
0979     if (err) {
0980         if (fs->ref_count == 0) {
0981             swim3_action(fs, MOTOR_OFF);
0982             out_8(&sw->control_bic, DRIVE_ENABLE | INTR_ENABLE);
0983             swim3_select(fs, RELAX);
0984         }
0985         return err;
0986     }
0987 
0988     if (mode & FMODE_EXCL)
0989         fs->ref_count = -1;
0990     else
0991         ++fs->ref_count;
0992 
0993     return 0;
0994 }
0995 
0996 static int floppy_unlocked_open(struct block_device *bdev, fmode_t mode)
0997 {
0998     int ret;
0999 
1000     mutex_lock(&swim3_mutex);
1001     ret = floppy_open(bdev, mode);
1002     mutex_unlock(&swim3_mutex);
1003 
1004     return ret;
1005 }
1006 
1007 static void floppy_release(struct gendisk *disk, fmode_t mode)
1008 {
1009     struct floppy_state *fs = disk->private_data;
1010     struct swim3 __iomem *sw = fs->swim3;
1011 
1012     mutex_lock(&swim3_mutex);
1013     if (fs->ref_count > 0)
1014         --fs->ref_count;
1015     else if (fs->ref_count == -1)
1016         fs->ref_count = 0;
1017     if (fs->ref_count == 0) {
1018         swim3_action(fs, MOTOR_OFF);
1019         out_8(&sw->control_bic, 0xff);
1020         swim3_select(fs, RELAX);
1021     }
1022     mutex_unlock(&swim3_mutex);
1023 }
1024 
1025 static unsigned int floppy_check_events(struct gendisk *disk,
1026                     unsigned int clearing)
1027 {
1028     struct floppy_state *fs = disk->private_data;
1029     return fs->ejected ? DISK_EVENT_MEDIA_CHANGE : 0;
1030 }
1031 
1032 static int floppy_revalidate(struct gendisk *disk)
1033 {
1034     struct floppy_state *fs = disk->private_data;
1035     struct swim3 __iomem *sw;
1036     int ret, n;
1037 
1038     if (fs->mdev->media_bay &&
1039         check_media_bay(fs->mdev->media_bay) != MB_FD)
1040         return -ENXIO;
1041 
1042     sw = fs->swim3;
1043     grab_drive(fs, revalidating, 0);
1044     out_8(&sw->intr_enable, 0);
1045     out_8(&sw->control_bis, DRIVE_ENABLE);
1046     swim3_action(fs, MOTOR_ON); /* necessary? */
1047     fs->write_prot = -1;
1048     fs->cur_cyl = -1;
1049     mdelay(1);
1050     for (n = HZ; n > 0; --n) {
1051         if (swim3_readbit(fs, SEEK_COMPLETE))
1052             break;
1053         if (signal_pending(current))
1054             break;
1055         swim3_select(fs, RELAX);
1056         schedule_timeout_interruptible(1);
1057     }
1058     ret = swim3_readbit(fs, SEEK_COMPLETE) == 0
1059         || swim3_readbit(fs, DISK_IN) == 0;
1060     if (ret)
1061         swim3_action(fs, MOTOR_OFF);
1062     else {
1063         fs->ejected = 0;
1064         swim3_action(fs, SETMFM);
1065     }
1066     swim3_select(fs, RELAX);
1067 
1068     release_drive(fs);
1069     return ret;
1070 }
1071 
1072 static const struct block_device_operations floppy_fops = {
1073     .open       = floppy_unlocked_open,
1074     .release    = floppy_release,
1075     .ioctl      = floppy_ioctl,
1076     .check_events   = floppy_check_events,
1077 };
1078 
1079 static const struct blk_mq_ops swim3_mq_ops = {
1080     .queue_rq = swim3_queue_rq,
1081 };
1082 
1083 static void swim3_mb_event(struct macio_dev* mdev, int mb_state)
1084 {
1085     struct floppy_state *fs = macio_get_drvdata(mdev);
1086     struct swim3 __iomem *sw;
1087 
1088     if (!fs)
1089         return;
1090 
1091     sw = fs->swim3;
1092 
1093     if (mb_state != MB_FD)
1094         return;
1095 
1096     /* Clear state */
1097     out_8(&sw->intr_enable, 0);
1098     in_8(&sw->intr);
1099     in_8(&sw->error);
1100 }
1101 
1102 static int swim3_add_device(struct macio_dev *mdev, int index)
1103 {
1104     struct device_node *swim = mdev->ofdev.dev.of_node;
1105     struct floppy_state *fs = &floppy_states[index];
1106     int rc = -EBUSY;
1107 
1108     fs->mdev = mdev;
1109     fs->index = index;
1110 
1111     /* Check & Request resources */
1112     if (macio_resource_count(mdev) < 2) {
1113         swim3_err("%s", "No address in device-tree\n");
1114         return -ENXIO;
1115     }
1116     if (macio_irq_count(mdev) < 1) {
1117         swim3_err("%s", "No interrupt in device-tree\n");
1118         return -ENXIO;
1119     }
1120     if (macio_request_resource(mdev, 0, "swim3 (mmio)")) {
1121         swim3_err("%s", "Can't request mmio resource\n");
1122         return -EBUSY;
1123     }
1124     if (macio_request_resource(mdev, 1, "swim3 (dma)")) {
1125         swim3_err("%s", "Can't request dma resource\n");
1126         macio_release_resource(mdev, 0);
1127         return -EBUSY;
1128     }
1129     dev_set_drvdata(&mdev->ofdev.dev, fs);
1130 
1131     if (mdev->media_bay == NULL)
1132         pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 1);
1133     
1134     fs->state = idle;
1135     fs->swim3 = (struct swim3 __iomem *)
1136         ioremap(macio_resource_start(mdev, 0), 0x200);
1137     if (fs->swim3 == NULL) {
1138         swim3_err("%s", "Couldn't map mmio registers\n");
1139         rc = -ENOMEM;
1140         goto out_release;
1141     }
1142     fs->dma = (struct dbdma_regs __iomem *)
1143         ioremap(macio_resource_start(mdev, 1), 0x200);
1144     if (fs->dma == NULL) {
1145         swim3_err("%s", "Couldn't map dma registers\n");
1146         iounmap(fs->swim3);
1147         rc = -ENOMEM;
1148         goto out_release;
1149     }
1150     fs->swim3_intr = macio_irq(mdev, 0);
1151     fs->dma_intr = macio_irq(mdev, 1);
1152     fs->cur_cyl = -1;
1153     fs->cur_sector = -1;
1154     fs->secpercyl = 36;
1155     fs->secpertrack = 18;
1156     fs->total_secs = 2880;
1157     init_waitqueue_head(&fs->wait);
1158 
1159     fs->dma_cmd = (struct dbdma_cmd *) DBDMA_ALIGN(fs->dbdma_cmd_space);
1160     memset(fs->dma_cmd, 0, 2 * sizeof(struct dbdma_cmd));
1161     fs->dma_cmd[1].command = cpu_to_le16(DBDMA_STOP);
1162 
1163     if (mdev->media_bay == NULL || check_media_bay(mdev->media_bay) == MB_FD)
1164         swim3_mb_event(mdev, MB_FD);
1165 
1166     if (request_irq(fs->swim3_intr, swim3_interrupt, 0, "SWIM3", fs)) {
1167         swim3_err("%s", "Couldn't request interrupt\n");
1168         pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 0);
1169         goto out_unmap;
1170     }
1171 
1172     timer_setup(&fs->timeout, NULL, 0);
1173 
1174     swim3_info("SWIM3 floppy controller %s\n",
1175         mdev->media_bay ? "in media bay" : "");
1176 
1177     return 0;
1178 
1179  out_unmap:
1180     iounmap(fs->dma);
1181     iounmap(fs->swim3);
1182 
1183  out_release:
1184     macio_release_resource(mdev, 0);
1185     macio_release_resource(mdev, 1);
1186 
1187     return rc;
1188 }
1189 
1190 static int swim3_attach(struct macio_dev *mdev,
1191             const struct of_device_id *match)
1192 {
1193     struct floppy_state *fs;
1194     struct gendisk *disk;
1195     int rc;
1196 
1197     if (floppy_count >= MAX_FLOPPIES)
1198         return -ENXIO;
1199 
1200     if (floppy_count == 0) {
1201         rc = register_blkdev(FLOPPY_MAJOR, "fd");
1202         if (rc)
1203             return rc;
1204     }
1205 
1206     fs = &floppy_states[floppy_count];
1207     memset(fs, 0, sizeof(*fs));
1208 
1209     rc = blk_mq_alloc_sq_tag_set(&fs->tag_set, &swim3_mq_ops, 2,
1210             BLK_MQ_F_SHOULD_MERGE);
1211     if (rc)
1212         goto out_unregister;
1213 
1214     disk = blk_mq_alloc_disk(&fs->tag_set, fs);
1215     if (IS_ERR(disk)) {
1216         rc = PTR_ERR(disk);
1217         goto out_free_tag_set;
1218     }
1219 
1220     rc = swim3_add_device(mdev, floppy_count);
1221     if (rc)
1222         goto out_cleanup_disk;
1223 
1224     disk->major = FLOPPY_MAJOR;
1225     disk->first_minor = floppy_count;
1226     disk->minors = 1;
1227     disk->fops = &floppy_fops;
1228     disk->private_data = fs;
1229     disk->events = DISK_EVENT_MEDIA_CHANGE;
1230     disk->flags |= GENHD_FL_REMOVABLE | GENHD_FL_NO_PART;
1231     sprintf(disk->disk_name, "fd%d", floppy_count);
1232     set_capacity(disk, 2880);
1233     rc = add_disk(disk);
1234     if (rc)
1235         goto out_cleanup_disk;
1236 
1237     disks[floppy_count++] = disk;
1238     return 0;
1239 
1240 out_cleanup_disk:
1241     put_disk(disk);
1242 out_free_tag_set:
1243     blk_mq_free_tag_set(&fs->tag_set);
1244 out_unregister:
1245     if (floppy_count == 0)
1246         unregister_blkdev(FLOPPY_MAJOR, "fd");
1247     return rc;
1248 }
1249 
1250 static const struct of_device_id swim3_match[] =
1251 {
1252     {
1253     .name       = "swim3",
1254     },
1255     {
1256     .compatible = "ohare-swim3"
1257     },
1258     {
1259     .compatible = "swim3"
1260     },
1261     { /* end of list */ }
1262 };
1263 
1264 static struct macio_driver swim3_driver =
1265 {
1266     .driver = {
1267         .name       = "swim3",
1268         .of_match_table = swim3_match,
1269     },
1270     .probe      = swim3_attach,
1271 #ifdef CONFIG_PMAC_MEDIABAY
1272     .mediabay_event = swim3_mb_event,
1273 #endif
1274 #if 0
1275     .suspend    = swim3_suspend,
1276     .resume     = swim3_resume,
1277 #endif
1278 };
1279 
1280 
1281 int swim3_init(void)
1282 {
1283     macio_register_driver(&swim3_driver);
1284     return 0;
1285 }
1286 
1287 module_init(swim3_init)
1288 
1289 MODULE_LICENSE("GPL");
1290 MODULE_AUTHOR("Paul Mackerras");
1291 MODULE_ALIAS_BLOCKDEV_MAJOR(FLOPPY_MAJOR);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!