block/paride/on26.c

0001 /*
0002         on26.c    (c) 1997-8  Grant R. Guenther <grant@torque.net>
0003                               Under the terms of the GNU General Public License.
0004
0005         on26.c is a low-level protocol driver for the
0006         OnSpec 90c26 parallel to IDE adapter chip.
0007
0008 */
0009
0010 /* Changes:
0011
0012         1.01    GRG 1998.05.06 init_proto, release_proto
0013     1.02    GRG 1998.09.23 updates for the -E rev chip
0014     1.03    GRG 1998.12.14 fix for slave drives
0015     1.04    GRG 1998.12.20 yet another bug fix
0016
0017 */
0018
0019 #define ON26_VERSION      "1.04"
0020
0021 #include <linux/module.h>
0022 #include <linux/init.h>
0023 #include <linux/delay.h>
0024 #include <linux/kernel.h>
0025 #include <linux/types.h>
0026 #include <linux/wait.h>
0027 #include <asm/io.h>
0028
0029 #include "paride.h"
0030
0031 /* mode codes:  0  nybble reads, 8-bit writes
0032                 1  8-bit reads and writes
0033                 2  8-bit EPP mode
0034         3  EPP-16
0035         4  EPP-32
0036 */
0037
0038 #define j44(a,b)  (((a>>4)&0x0f)|(b&0xf0))
0039
0040 #define P1  w2(5);w2(0xd);w2(5);w2(0xd);w2(5);w2(4);
0041 #define P2  w2(5);w2(7);w2(5);w2(4);
0042
0043 /* cont = 0 - access the IDE register file
0044    cont = 1 - access the IDE command set
0045 */
0046
0047 static int on26_read_regr( PIA *pi, int cont, int regr )
0048
0049 {       int     a, b, r;
0050
0051     r = (regr<<2) + 1 + cont;
0052
0053         switch (pi->mode)  {
0054
0055         case 0: w0(1); P1; w0(r); P2; w0(0); P1;
0056         w2(6); a = r1(); w2(4);
0057         w2(6); b = r1(); w2(4);
0058         w2(6); w2(4); w2(6); w2(4);
0059                 return j44(a,b);
0060
0061         case 1: w0(1); P1; w0(r); P2; w0(0); P1;
0062         w2(0x26); a = r0(); w2(4); w2(0x26); w2(4);
0063                 return a;
0064
0065     case 2:
0066     case 3:
0067         case 4: w3(1); w3(1); w2(5); w4(r); w2(4);
0068         w3(0); w3(0); w2(0x24); a = r4(); w2(4);
0069         w2(0x24); (void)r4(); w2(4);
0070                 return a;
0071
0072         }
0073         return -1;
0074 }
0075
0076 static void on26_write_regr( PIA *pi, int cont, int regr, int val )
0077
0078 {       int  r;
0079
0080         r = (regr<<2) + 1 + cont;
0081
0082         switch (pi->mode)  {
0083
0084         case 0:
0085         case 1: w0(1); P1; w0(r); P2; w0(0); P1;
0086         w0(val); P2; w0(val); P2;
0087         break;
0088
0089     case 2:
0090     case 3:
0091         case 4: w3(1); w3(1); w2(5); w4(r); w2(4);
0092         w3(0); w3(0);
0093         w2(5); w4(val); w2(4);
0094         w2(5); w4(val); w2(4);
0095                 break;
0096         }
0097 }
0098
0099 #define  CCP(x)  w0(0xfe);w0(0xaa);w0(0x55);w0(0);w0(0xff);\
0100          w0(0x87);w0(0x78);w0(x);w2(4);w2(5);w2(4);w0(0xff);
0101
0102 static void on26_connect ( PIA *pi )
0103
0104 {       int x;
0105
0106     pi->saved_r0 = r0();
0107         pi->saved_r2 = r2();
0108
0109         CCP(0x20);
0110     x = 8; if (pi->mode) x = 9;
0111
0112     w0(2); P1; w0(8); P2;
0113     w0(2); P1; w0(x); P2;
0114 }
0115
0116 static void on26_disconnect ( PIA *pi )
0117
0118 {       if (pi->mode >= 2) { w3(4); w3(4); w3(4); w3(4); }
0119                   else { w0(4); P1; w0(4); P1; }
0120     CCP(0x30);
0121         w0(pi->saved_r0);
0122         w2(pi->saved_r2);
0123 }
0124
0125 #define RESET_WAIT  200
0126
0127 static int on26_test_port( PIA *pi)  /* hard reset */
0128
0129 {       int     i, m, d, x=0, y=0;
0130
0131         pi->saved_r0 = r0();
0132         pi->saved_r2 = r2();
0133
0134         d = pi->delay;
0135         m = pi->mode;
0136         pi->delay = 5;
0137         pi->mode = 0;
0138
0139         w2(0xc);
0140
0141         CCP(0x30); CCP(0);
0142
0143         w0(0xfe);w0(0xaa);w0(0x55);w0(0);w0(0xff);
0144         i = ((r1() & 0xf0) << 4); w0(0x87);
0145         i |= (r1() & 0xf0); w0(0x78);
0146         w0(0x20);w2(4);w2(5);
0147         i |= ((r1() & 0xf0) >> 4);
0148         w2(4);w0(0xff);
0149
0150         if (i == 0xb5f) {
0151
0152             w0(2); P1; w0(0);   P2;
0153             w0(3); P1; w0(0);   P2;
0154             w0(2); P1; w0(8);   P2; udelay(100);
0155             w0(2); P1; w0(0xa); P2; udelay(100);
0156             w0(2); P1; w0(8);   P2; udelay(1000);
0157
0158             on26_write_regr(pi,0,6,0xa0);
0159
0160             for (i=0;i<RESET_WAIT;i++) {
0161                 on26_write_regr(pi,0,6,0xa0);
0162                 x = on26_read_regr(pi,0,7);
0163                 on26_write_regr(pi,0,6,0xb0);
0164                 y = on26_read_regr(pi,0,7);
0165                 if (!((x&0x80)||(y&0x80))) break;
0166                 mdelay(100);
0167             }
0168
0169         if (i == RESET_WAIT)
0170         printk("on26: Device reset failed (%x,%x)\n",x,y);
0171
0172             w0(4); P1; w0(4); P1;
0173         }
0174
0175         CCP(0x30);
0176
0177         pi->delay = d;
0178         pi->mode = m;
0179         w0(pi->saved_r0);
0180         w2(pi->saved_r2);
0181
0182         return 5;
0183 }
0184
0185
0186 static void on26_read_block( PIA *pi, char * buf, int count )
0187
0188 {       int     k, a, b;
0189
0190         switch (pi->mode) {
0191
0192         case 0: w0(1); P1; w0(1); P2; w0(2); P1; w0(0x18); P2; w0(0); P1;
0193         udelay(10);
0194         for (k=0;k<count;k++) {
0195                         w2(6); a = r1();
0196                         w2(4); b = r1();
0197                         buf[k] = j44(a,b);
0198                 }
0199         w0(2); P1; w0(8); P2;
0200                 break;
0201
0202         case 1: w0(1); P1; w0(1); P2; w0(2); P1; w0(0x19); P2; w0(0); P1;
0203         udelay(10);
0204                 for (k=0;k<count/2;k++) {
0205                         w2(0x26); buf[2*k] = r0();
0206             w2(0x24); buf[2*k+1] = r0();
0207                 }
0208                 w0(2); P1; w0(9); P2;
0209                 break;
0210
0211         case 2: w3(1); w3(1); w2(5); w4(1); w2(4);
0212         w3(0); w3(0); w2(0x24);
0213         udelay(10);
0214                 for (k=0;k<count;k++) buf[k] = r4();
0215                 w2(4);
0216                 break;
0217
0218         case 3: w3(1); w3(1); w2(5); w4(1); w2(4);
0219                 w3(0); w3(0); w2(0x24);
0220                 udelay(10);
0221                 for (k=0;k<count/2;k++) ((u16 *)buf)[k] = r4w();
0222                 w2(4);
0223                 break;
0224
0225         case 4: w3(1); w3(1); w2(5); w4(1); w2(4);
0226                 w3(0); w3(0); w2(0x24);
0227                 udelay(10);
0228                 for (k=0;k<count/4;k++) ((u32 *)buf)[k] = r4l();
0229                 w2(4);
0230                 break;
0231
0232         }
0233 }
0234
0235 static void on26_write_block( PIA *pi, char * buf, int count )
0236
0237 {       int k;
0238
0239         switch (pi->mode) {
0240
0241         case 0:
0242         case 1: w0(1); P1; w0(1); P2;
0243         w0(2); P1; w0(0x18+pi->mode); P2; w0(0); P1;
0244         udelay(10);
0245         for (k=0;k<count/2;k++) {
0246                         w2(5); w0(buf[2*k]);
0247             w2(7); w0(buf[2*k+1]);
0248                 }
0249                 w2(5); w2(4);
0250         w0(2); P1; w0(8+pi->mode); P2;
0251                 break;
0252
0253         case 2: w3(1); w3(1); w2(5); w4(1); w2(4);
0254         w3(0); w3(0); w2(0xc5);
0255         udelay(10);
0256                 for (k=0;k<count;k++) w4(buf[k]);
0257         w2(0xc4);
0258                 break;
0259
0260         case 3: w3(1); w3(1); w2(5); w4(1); w2(4);
0261                 w3(0); w3(0); w2(0xc5);
0262                 udelay(10);
0263                 for (k=0;k<count/2;k++) w4w(((u16 *)buf)[k]);
0264                 w2(0xc4);
0265                 break;
0266
0267         case 4: w3(1); w3(1); w2(5); w4(1); w2(4);
0268                 w3(0); w3(0); w2(0xc5);
0269                 udelay(10);
0270                 for (k=0;k<count/4;k++) w4l(((u32 *)buf)[k]);
0271                 w2(0xc4);
0272                 break;
0273
0274         }
0275
0276 }
0277
0278 static void on26_log_adapter( PIA *pi, char * scratch, int verbose )
0279
0280 {       char    *mode_string[5] = {"4-bit","8-bit","EPP-8",
0281                    "EPP-16","EPP-32"};
0282
0283         printk("%s: on26 %s, OnSpec 90c26 at 0x%x, ",
0284                 pi->device,ON26_VERSION,pi->port);
0285         printk("mode %d (%s), delay %d\n",pi->mode,
0286         mode_string[pi->mode],pi->delay);
0287
0288 }
0289
0290 static struct pi_protocol on26 = {
0291     .owner      = THIS_MODULE,
0292     .name       = "on26",
0293     .max_mode   = 5,
0294     .epp_first  = 2,
0295     .default_delay  = 1,
0296     .max_units  = 1,
0297     .write_regr = on26_write_regr,
0298     .read_regr  = on26_read_regr,
0299     .write_block    = on26_write_block,
0300     .read_block = on26_read_block,
0301     .connect    = on26_connect,
0302     .disconnect = on26_disconnect,
0303     .test_port  = on26_test_port,
0304     .log_adapter    = on26_log_adapter,
0305 };
0306
0307 static int __init on26_init(void)
0308 {
0309     return paride_register(&on26);
0310 }
0311
0312 static void __exit on26_exit(void)
0313 {
0314     paride_unregister(&on26);
0315 }
0316
0317 MODULE_LICENSE("GPL");
0318 module_init(on26_init)
0319 module_exit(on26_exit)