drivers/bcma/driver_pcie2.c

0001 /*
0002  * Broadcom specific AMBA
0003  * PCIe Gen 2 Core
0004  *
0005  * Copyright 2014, Broadcom Corporation
0006  * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
0007  *
0008  * Licensed under the GNU/GPL. See COPYING for details.
0009  */
0010
0011 #include "bcma_private.h"
0012 #include <linux/bcma/bcma.h>
0013 #include <linux/pci.h>
0014
0015 /**************************************************
0016  * R/W ops.
0017  **************************************************/
0018
0019 #if 0
0020 static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
0021 {
0022     pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
0023     pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
0024     return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
0025 }
0026 #endif
0027
0028 static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
0029                       u32 val)
0030 {
0031     pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
0032     pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
0033 }
0034
0035 /**************************************************
0036  * Init.
0037  **************************************************/
0038
0039 static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
0040                         bool enable)
0041 {
0042     u32 val;
0043
0044     /* restore back to default */
0045     val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
0046     val |= PCIE2_CLKC_DLYPERST;
0047     val &= ~PCIE2_CLKC_DISSPROMLD;
0048     if (enable) {
0049         val &= ~PCIE2_CLKC_DLYPERST;
0050         val |= PCIE2_CLKC_DISSPROMLD;
0051     }
0052     pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
0053     /* flush */
0054     return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
0055 }
0056
0057 static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
0058 {
0059     /* LTR0 */
0060     pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
0061     pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
0062     /* LTR1 */
0063     pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
0064     pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
0065     /* LTR2 */
0066     pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
0067     pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
0068 }
0069
0070 static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
0071 {
0072     u8 core_rev = pcie2->core->id.rev;
0073     u32 devstsctr2;
0074
0075     if (core_rev < 2 || core_rev == 10 || core_rev > 13)
0076         return;
0077
0078     pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
0079               PCIE2_CAP_DEVSTSCTRL2_OFFSET);
0080     devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
0081     if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
0082         /* force the right LTR values */
0083         bcma_core_pcie2_set_ltr_vals(pcie2);
0084
0085         /* TODO:
0086          *si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0);
0087          */
0088
0089         /* enable the LTR */
0090         devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
0091         pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
0092                   PCIE2_CAP_DEVSTSCTRL2_OFFSET);
0093         pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
0094
0095         /* set the LTR state to be active */
0096         pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
0097                   PCIE2_LTR_ACTIVE);
0098         usleep_range(1000, 2000);
0099
0100         /* set the LTR state to be sleep */
0101         pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
0102                   PCIE2_LTR_SLEEP);
0103         usleep_range(1000, 2000);
0104     }
0105 }
0106
0107 static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
0108 {
0109     u8 core_rev = pcie2->core->id.rev;
0110     bool pciewar160, pciewar162;
0111
0112     pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
0113     pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
0114              core_rev == 9 || core_rev == 11;
0115
0116     if (!pciewar160 && !pciewar162)
0117         return;
0118
0119 /* TODO */
0120 #if 0
0121     pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
0122             PCIE_DISABLE_L1CLK_GATING);
0123 #if 0
0124     pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
0125               PCIEGEN2_COE_PVT_TL_CTRL_0);
0126     pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
0127              ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
0128 #endif
0129 #endif
0130 }
0131
0132 static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
0133 {
0134     pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
0135     pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
0136 }
0137
0138 static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
0139 {
0140     pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
0141     pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
0142 }
0143
0144 static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
0145 {
0146     struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
0147     u8 core_rev = pcie2->core->id.rev;
0148     u32 alp_khz, pm_value;
0149
0150     if (core_rev <= 13) {
0151         alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
0152         pm_value = (1000000 * 2) / alp_khz;
0153         pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
0154                   PCIE2_PVT_REG_PM_CLK_PERIOD);
0155         pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
0156     }
0157 }
0158
0159 void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
0160 {
0161     struct bcma_bus *bus = pcie2->core->bus;
0162     struct bcma_chipinfo *ci = &bus->chipinfo;
0163     u32 tmp;
0164
0165     tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
0166     if ((tmp & 0xe) >> 1 == 2)
0167         bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
0168
0169     switch (bus->chipinfo.id) {
0170     case BCMA_CHIP_ID_BCM4360:
0171     case BCMA_CHIP_ID_BCM4352:
0172         pcie2->reqsize = 1024;
0173         break;
0174     default:
0175         pcie2->reqsize = 128;
0176         break;
0177     }
0178
0179     if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
0180         bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
0181     bcma_core_pcie2_hw_ltr_war(pcie2);
0182     pciedev_crwlpciegen2(pcie2);
0183     pciedev_reg_pm_clk_period(pcie2);
0184     pciedev_crwlpciegen2_180(pcie2);
0185     pciedev_crwlpciegen2_182(pcie2);
0186 }
0187
0188 /**************************************************
0189  * Runtime ops.
0190  **************************************************/
0191
0192 void bcma_core_pcie2_up(struct bcma_drv_pcie2 *pcie2)
0193 {
0194     struct bcma_bus *bus = pcie2->core->bus;
0195     struct pci_dev *dev = bus->host_pci;
0196     int err;
0197
0198     err = pcie_set_readrq(dev, pcie2->reqsize);
0199     if (err)
0200         bcma_err(bus, "Error setting PCI_EXP_DEVCTL_READRQ: %d\n", err);
0201 }