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0001 /*
0002  * Broadcom specific AMBA
0003  * PCI Core in hostmode
0004  *
0005  * Copyright 2005 - 2011, Broadcom Corporation
0006  * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
0007  * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
0008  *
0009  * Licensed under the GNU/GPL. See COPYING for details.
0010  */
0011 
0012 #include "bcma_private.h"
0013 #include <linux/pci.h>
0014 #include <linux/slab.h>
0015 #include <linux/export.h>
0016 #include <linux/bcma/bcma.h>
0017 #include <asm/paccess.h>
0018 
0019 /* Probe a 32bit value on the bus and catch bus exceptions.
0020  * Returns nonzero on a bus exception.
0021  * This is MIPS specific */
0022 #define mips_busprobe32(val, addr)  get_dbe((val), ((u32 *)(addr)))
0023 
0024 /* Assume one-hot slot wiring */
0025 #define BCMA_PCI_SLOT_MAX   16
0026 #define PCI_CONFIG_SPACE_SIZE   256
0027 
0028 bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
0029 {
0030     struct bcma_bus *bus = pc->core->bus;
0031     u16 chipid_top;
0032     u32 tmp;
0033 
0034     chipid_top = (bus->chipinfo.id & 0xFF00);
0035     if (chipid_top != 0x4700 &&
0036         chipid_top != 0x5300)
0037         return false;
0038 
0039     bcma_core_enable(pc->core, 0);
0040 
0041     return !mips_busprobe32(tmp, pc->core->io_addr);
0042 }
0043 
0044 static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
0045 {
0046     pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
0047     pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
0048     return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
0049 }
0050 
0051 static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
0052                    u32 data)
0053 {
0054     pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
0055     pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
0056     pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
0057 }
0058 
0059 static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
0060                  unsigned int func, unsigned int off)
0061 {
0062     u32 addr = 0;
0063 
0064     /* Issue config commands only when the data link is up (at least
0065      * one external pcie device is present).
0066      */
0067     if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
0068               & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
0069         goto out;
0070 
0071     /* Type 0 transaction */
0072     /* Slide the PCI window to the appropriate slot */
0073     pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
0074     /* Calculate the address */
0075     addr = pc->host_controller->host_cfg_addr;
0076     addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
0077     addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
0078     addr |= (off & ~3);
0079 
0080 out:
0081     return addr;
0082 }
0083 
0084 static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
0085                   unsigned int func, unsigned int off,
0086                   void *buf, int len)
0087 {
0088     int err = -EINVAL;
0089     u32 addr, val;
0090     void __iomem *mmio = 0;
0091 
0092     WARN_ON(!pc->hostmode);
0093     if (unlikely(len != 1 && len != 2 && len != 4))
0094         goto out;
0095     if (dev == 0) {
0096         /* we support only two functions on device 0 */
0097         if (func > 1)
0098             goto out;
0099 
0100         /* accesses to config registers with offsets >= 256
0101          * requires indirect access.
0102          */
0103         if (off >= PCI_CONFIG_SPACE_SIZE) {
0104             addr = (func << 12);
0105             addr |= (off & 0x0FFC);
0106             val = bcma_pcie_read_config(pc, addr);
0107         } else {
0108             addr = BCMA_CORE_PCI_PCICFG0;
0109             addr |= (func << 8);
0110             addr |= (off & 0xFC);
0111             val = pcicore_read32(pc, addr);
0112         }
0113     } else {
0114         addr = bcma_get_cfgspace_addr(pc, dev, func, off);
0115         if (unlikely(!addr))
0116             goto out;
0117         err = -ENOMEM;
0118         mmio = ioremap(addr, sizeof(val));
0119         if (!mmio)
0120             goto out;
0121 
0122         if (mips_busprobe32(val, mmio)) {
0123             val = 0xFFFFFFFF;
0124             goto unmap;
0125         }
0126     }
0127     val >>= (8 * (off & 3));
0128 
0129     switch (len) {
0130     case 1:
0131         *((u8 *)buf) = (u8)val;
0132         break;
0133     case 2:
0134         *((u16 *)buf) = (u16)val;
0135         break;
0136     case 4:
0137         *((u32 *)buf) = (u32)val;
0138         break;
0139     }
0140     err = 0;
0141 unmap:
0142     if (mmio)
0143         iounmap(mmio);
0144 out:
0145     return err;
0146 }
0147 
0148 static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
0149                    unsigned int func, unsigned int off,
0150                    const void *buf, int len)
0151 {
0152     int err = -EINVAL;
0153     u32 addr, val;
0154     void __iomem *mmio = 0;
0155     u16 chipid = pc->core->bus->chipinfo.id;
0156 
0157     WARN_ON(!pc->hostmode);
0158     if (unlikely(len != 1 && len != 2 && len != 4))
0159         goto out;
0160     if (dev == 0) {
0161         /* we support only two functions on device 0 */
0162         if (func > 1)
0163             goto out;
0164 
0165         /* accesses to config registers with offsets >= 256
0166          * requires indirect access.
0167          */
0168         if (off >= PCI_CONFIG_SPACE_SIZE) {
0169             addr = (func << 12);
0170             addr |= (off & 0x0FFC);
0171             val = bcma_pcie_read_config(pc, addr);
0172         } else {
0173             addr = BCMA_CORE_PCI_PCICFG0;
0174             addr |= (func << 8);
0175             addr |= (off & 0xFC);
0176             val = pcicore_read32(pc, addr);
0177         }
0178     } else {
0179         addr = bcma_get_cfgspace_addr(pc, dev, func, off);
0180         if (unlikely(!addr))
0181             goto out;
0182         err = -ENOMEM;
0183         mmio = ioremap(addr, sizeof(val));
0184         if (!mmio)
0185             goto out;
0186 
0187         if (mips_busprobe32(val, mmio)) {
0188             val = 0xFFFFFFFF;
0189             goto unmap;
0190         }
0191     }
0192 
0193     switch (len) {
0194     case 1:
0195         val &= ~(0xFF << (8 * (off & 3)));
0196         val |= *((const u8 *)buf) << (8 * (off & 3));
0197         break;
0198     case 2:
0199         val &= ~(0xFFFF << (8 * (off & 3)));
0200         val |= *((const u16 *)buf) << (8 * (off & 3));
0201         break;
0202     case 4:
0203         val = *((const u32 *)buf);
0204         break;
0205     }
0206     if (dev == 0) {
0207         /* accesses to config registers with offsets >= 256
0208          * requires indirect access.
0209          */
0210         if (off >= PCI_CONFIG_SPACE_SIZE)
0211             bcma_pcie_write_config(pc, addr, val);
0212         else
0213             pcicore_write32(pc, addr, val);
0214     } else {
0215         writel(val, mmio);
0216 
0217         if (chipid == BCMA_CHIP_ID_BCM4716 ||
0218             chipid == BCMA_CHIP_ID_BCM4748)
0219             readl(mmio);
0220     }
0221 
0222     err = 0;
0223 unmap:
0224     if (mmio)
0225         iounmap(mmio);
0226 out:
0227     return err;
0228 }
0229 
0230 static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
0231                           unsigned int devfn,
0232                           int reg, int size, u32 *val)
0233 {
0234     unsigned long flags;
0235     int err;
0236     struct bcma_drv_pci *pc;
0237     struct bcma_drv_pci_host *pc_host;
0238 
0239     pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
0240     pc = pc_host->pdev;
0241 
0242     spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
0243     err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
0244                      PCI_FUNC(devfn), reg, val, size);
0245     spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
0246 
0247     return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
0248 }
0249 
0250 static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
0251                            unsigned int devfn,
0252                            int reg, int size, u32 val)
0253 {
0254     unsigned long flags;
0255     int err;
0256     struct bcma_drv_pci *pc;
0257     struct bcma_drv_pci_host *pc_host;
0258 
0259     pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
0260     pc = pc_host->pdev;
0261 
0262     spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
0263     err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
0264                       PCI_FUNC(devfn), reg, &val, size);
0265     spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
0266 
0267     return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
0268 }
0269 
0270 /* return cap_offset if requested capability exists in the PCI config space */
0271 static u8 bcma_find_pci_capability(struct bcma_drv_pci *pc, unsigned int dev,
0272                    unsigned int func, u8 req_cap_id,
0273                    unsigned char *buf, u32 *buflen)
0274 {
0275     u8 cap_id;
0276     u8 cap_ptr = 0;
0277     u32 bufsize;
0278     u8 byte_val;
0279 
0280     /* check for Header type 0 */
0281     bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
0282                 sizeof(u8));
0283     if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
0284         return cap_ptr;
0285 
0286     /* check if the capability pointer field exists */
0287     bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
0288                 sizeof(u8));
0289     if (!(byte_val & PCI_STATUS_CAP_LIST))
0290         return cap_ptr;
0291 
0292     /* check if the capability pointer is 0x00 */
0293     bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
0294                 sizeof(u8));
0295     if (cap_ptr == 0x00)
0296         return cap_ptr;
0297 
0298     /* loop through the capability list and see if the requested capability
0299      * exists */
0300     bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
0301     while (cap_id != req_cap_id) {
0302         bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
0303                     sizeof(u8));
0304         if (cap_ptr == 0x00)
0305             return cap_ptr;
0306         bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
0307                     sizeof(u8));
0308     }
0309 
0310     /* found the caller requested capability */
0311     if ((buf != NULL) && (buflen != NULL)) {
0312         u8 cap_data;
0313 
0314         bufsize = *buflen;
0315         if (!bufsize)
0316             return cap_ptr;
0317 
0318         *buflen = 0;
0319 
0320         /* copy the capability data excluding cap ID and next ptr */
0321         cap_data = cap_ptr + 2;
0322         if ((bufsize + cap_data)  > PCI_CONFIG_SPACE_SIZE)
0323             bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
0324         *buflen = bufsize;
0325         while (bufsize--) {
0326             bcma_extpci_read_config(pc, dev, func, cap_data, buf,
0327                         sizeof(u8));
0328             cap_data++;
0329             buf++;
0330         }
0331     }
0332 
0333     return cap_ptr;
0334 }
0335 
0336 /* If the root port is capable of returning Config Request
0337  * Retry Status (CRS) Completion Status to software then
0338  * enable the feature.
0339  */
0340 static void bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
0341 {
0342     struct bcma_bus *bus = pc->core->bus;
0343     u8 cap_ptr, root_ctrl, root_cap, dev;
0344     u16 val16;
0345     int i;
0346 
0347     cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
0348                        NULL);
0349     root_cap = cap_ptr + PCI_EXP_RTCAP;
0350     bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
0351     if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
0352         /* Enable CRS software visibility */
0353         root_ctrl = cap_ptr + PCI_EXP_RTCTL;
0354         val16 = PCI_EXP_RTCTL_CRSSVE;
0355         bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
0356                     sizeof(u16));
0357 
0358         /* Initiate a configuration request to read the vendor id
0359          * field of the device function's config space header after
0360          * 100 ms wait time from the end of Reset. If the device is
0361          * not done with its internal initialization, it must at
0362          * least return a completion TLP, with a completion status
0363          * of "Configuration Request Retry Status (CRS)". The root
0364          * complex must complete the request to the host by returning
0365          * a read-data value of 0001h for the Vendor ID field and
0366          * all 1s for any additional bytes included in the request.
0367          * Poll using the config reads for max wait time of 1 sec or
0368          * until we receive the successful completion status. Repeat
0369          * the procedure for all the devices.
0370          */
0371         for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
0372             for (i = 0; i < 100000; i++) {
0373                 bcma_extpci_read_config(pc, dev, 0,
0374                             PCI_VENDOR_ID, &val16,
0375                             sizeof(val16));
0376                 if (val16 != 0x1)
0377                     break;
0378                 udelay(10);
0379             }
0380             if (val16 == 0x1)
0381                 bcma_err(bus, "PCI: Broken device in slot %d\n",
0382                      dev);
0383         }
0384     }
0385 }
0386 
0387 void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
0388 {
0389     struct bcma_bus *bus = pc->core->bus;
0390     struct bcma_drv_pci_host *pc_host;
0391     u32 tmp;
0392     u32 pci_membase_1G;
0393     unsigned long io_map_base;
0394 
0395     bcma_info(bus, "PCIEcore in host mode found\n");
0396 
0397     if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
0398         bcma_info(bus, "This PCIE core is disabled and not working\n");
0399         return;
0400     }
0401 
0402     pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
0403     if (!pc_host)  {
0404         bcma_err(bus, "can not allocate memory");
0405         return;
0406     }
0407 
0408     spin_lock_init(&pc_host->cfgspace_lock);
0409 
0410     pc->host_controller = pc_host;
0411     pc_host->pci_controller.io_resource = &pc_host->io_resource;
0412     pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
0413     pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
0414     pc_host->pdev = pc;
0415 
0416     pci_membase_1G = BCMA_SOC_PCI_DMA;
0417     pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
0418 
0419     pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
0420     pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
0421 
0422     pc_host->mem_resource.name = "BCMA PCIcore external memory";
0423     pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
0424     pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
0425     pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
0426 
0427     pc_host->io_resource.name = "BCMA PCIcore external I/O";
0428     pc_host->io_resource.start = 0x100;
0429     pc_host->io_resource.end = 0x7FF;
0430     pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
0431 
0432     /* Reset RC */
0433     usleep_range(3000, 5000);
0434     pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
0435     msleep(50);
0436     pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
0437             BCMA_CORE_PCI_CTL_RST_OE);
0438 
0439     /* 64 MB I/O access window. On 4716, use
0440      * sbtopcie0 to access the device registers. We
0441      * can't use address match 2 (1 GB window) region
0442      * as mips can't generate 64-bit address on the
0443      * backplane.
0444      */
0445     if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 ||
0446         bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
0447         pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
0448         pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
0449                         BCMA_SOC_PCI_MEM_SZ - 1;
0450         pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
0451                 BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
0452     } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
0453         tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
0454         tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
0455         tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
0456         if (pc->core->core_unit == 0) {
0457             pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
0458             pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
0459                             BCMA_SOC_PCI_MEM_SZ - 1;
0460             pc_host->io_resource.start = 0x100;
0461             pc_host->io_resource.end = 0x47F;
0462             pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
0463             pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
0464                     tmp | BCMA_SOC_PCI_MEM);
0465         } else if (pc->core->core_unit == 1) {
0466             pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
0467             pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
0468                             BCMA_SOC_PCI_MEM_SZ - 1;
0469             pc_host->io_resource.start = 0x480;
0470             pc_host->io_resource.end = 0x7FF;
0471             pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
0472             pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
0473             pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
0474                     tmp | BCMA_SOC_PCI1_MEM);
0475         }
0476     } else
0477         pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
0478                 BCMA_CORE_PCI_SBTOPCI_IO);
0479 
0480     /* 64 MB configuration access window */
0481     pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
0482 
0483     /* 1 GB memory access window */
0484     pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
0485             BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
0486 
0487 
0488     /* As per PCI Express Base Spec 1.1 we need to wait for
0489      * at least 100 ms from the end of a reset (cold/warm/hot)
0490      * before issuing configuration requests to PCI Express
0491      * devices.
0492      */
0493     msleep(100);
0494 
0495     bcma_core_pci_enable_crs(pc);
0496 
0497     if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
0498         bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
0499         u16 val16;
0500         bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
0501                     &val16, sizeof(val16));
0502         val16 |= (2 << 5);  /* Max payload size of 512 */
0503         val16 |= (2 << 12); /* MRRS 512 */
0504         bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
0505                      &val16, sizeof(val16));
0506     }
0507 
0508     /* Enable PCI bridge BAR0 memory & master access */
0509     tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
0510     bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
0511 
0512     /* Enable PCI interrupts */
0513     pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
0514 
0515     /* Ok, ready to run, register it to the system.
0516      * The following needs change, if we want to port hostmode
0517      * to non-MIPS platform. */
0518     io_map_base = (unsigned long)ioremap(pc_host->mem_resource.start,
0519                              resource_size(&pc_host->mem_resource));
0520     pc_host->pci_controller.io_map_base = io_map_base;
0521     set_io_port_base(pc_host->pci_controller.io_map_base);
0522     /* Give some time to the PCI controller to configure itself with the new
0523      * values. Not waiting at this point causes crashes of the machine. */
0524     usleep_range(10000, 15000);
0525     register_pci_controller(&pc_host->pci_controller);
0526     return;
0527 }
0528 
0529 /* Early PCI fixup for a device on the PCI-core bridge. */
0530 static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
0531 {
0532     if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
0533         /* This is not a device on the PCI-core bridge. */
0534         return;
0535     }
0536     if (PCI_SLOT(dev->devfn) != 0)
0537         return;
0538 
0539     pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
0540 
0541     /* Enable PCI bridge bus mastering and memory space */
0542     pci_set_master(dev);
0543     if (pcibios_enable_device(dev, ~0) < 0) {
0544         pr_err("PCI: BCMA bridge enable failed\n");
0545         return;
0546     }
0547 
0548     /* Enable PCI bridge BAR1 prefetch and burst */
0549     pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
0550 }
0551 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
0552 
0553 /* Early PCI fixup for all PCI-cores to set the correct memory address. */
0554 static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
0555 {
0556     struct resource *res;
0557     int pos, err;
0558 
0559     if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
0560         /* This is not a device on the PCI-core bridge. */
0561         return;
0562     }
0563     if (PCI_SLOT(dev->devfn) == 0)
0564         return;
0565 
0566     pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
0567 
0568     for (pos = 0; pos < 6; pos++) {
0569         res = &dev->resource[pos];
0570         if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
0571             err = pci_assign_resource(dev, pos);
0572             if (err)
0573                 pr_err("PCI: Problem fixing up the addresses on %s\n",
0574                        pci_name(dev));
0575         }
0576     }
0577 }
0578 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
0579 
0580 /* This function is called when doing a pci_enable_device().
0581  * We must first check if the device is a device on the PCI-core bridge. */
0582 int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
0583 {
0584     struct bcma_drv_pci_host *pc_host;
0585     int readrq;
0586 
0587     if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
0588         /* This is not a device on the PCI-core bridge. */
0589         return -ENODEV;
0590     }
0591     pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
0592                    pci_ops);
0593 
0594     pr_info("PCI: Fixing up device %s\n", pci_name(dev));
0595 
0596     /* Fix up interrupt lines */
0597     dev->irq = bcma_core_irq(pc_host->pdev->core, 0);
0598     pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
0599 
0600     readrq = pcie_get_readrq(dev);
0601     if (readrq > 128) {
0602         pr_info("change PCIe max read request size from %i to 128\n", readrq);
0603         pcie_set_readrq(dev, 128);
0604     }
0605     return 0;
0606 }
0607 EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
0608 
0609 /* PCI device IRQ mapping. */
0610 int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
0611 {
0612     struct bcma_drv_pci_host *pc_host;
0613 
0614     if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
0615         /* This is not a device on the PCI-core bridge. */
0616         return -ENODEV;
0617     }
0618 
0619     pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
0620                    pci_ops);
0621     return bcma_core_irq(pc_host->pdev->core, 0);
0622 }
0623 EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
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