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0001 /*
0002  * Broadcom specific AMBA
0003  * ChipCommon Power Management Unit driver
0004  *
0005  * Copyright 2009, Michael Buesch <m@bues.ch>
0006  * Copyright 2007, 2011, Broadcom Corporation
0007  * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
0008  *
0009  * Licensed under the GNU/GPL. See COPYING for details.
0010  */
0011 
0012 #include "bcma_private.h"
0013 #include <linux/export.h>
0014 #include <linux/bcma/bcma.h>
0015 
0016 u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
0017 {
0018     bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
0019     bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
0020     return bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
0021 }
0022 EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
0023 
0024 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
0025 {
0026     bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
0027     bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
0028     bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
0029 }
0030 EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
0031 
0032 void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
0033                  u32 set)
0034 {
0035     bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
0036     bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
0037     bcma_pmu_maskset32(cc, BCMA_CC_PMU_PLLCTL_DATA, mask, set);
0038 }
0039 EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
0040 
0041 void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
0042                  u32 offset, u32 mask, u32 set)
0043 {
0044     bcma_pmu_write32(cc, BCMA_CC_PMU_CHIPCTL_ADDR, offset);
0045     bcma_pmu_read32(cc, BCMA_CC_PMU_CHIPCTL_ADDR);
0046     bcma_pmu_maskset32(cc, BCMA_CC_PMU_CHIPCTL_DATA, mask, set);
0047 }
0048 EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
0049 
0050 void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
0051                 u32 set)
0052 {
0053     bcma_pmu_write32(cc, BCMA_CC_PMU_REGCTL_ADDR, offset);
0054     bcma_pmu_read32(cc, BCMA_CC_PMU_REGCTL_ADDR);
0055     bcma_pmu_maskset32(cc, BCMA_CC_PMU_REGCTL_DATA, mask, set);
0056 }
0057 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
0058 
0059 static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
0060 {
0061     u32 ilp_ctl, alp_hz;
0062 
0063     if (!(bcma_pmu_read32(cc, BCMA_CC_PMU_STAT) &
0064           BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
0065         return 0;
0066 
0067     bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
0068              BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
0069     usleep_range(1000, 2000);
0070 
0071     ilp_ctl = bcma_pmu_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
0072     ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
0073 
0074     bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
0075 
0076     alp_hz = ilp_ctl * 32768 / 4;
0077     return (alp_hz + 50000) / 100000 * 100;
0078 }
0079 
0080 static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
0081 {
0082     struct bcma_bus *bus = cc->core->bus;
0083     u32 freq_tgt_target = 0, freq_tgt_current;
0084     u32 pll0, mask;
0085 
0086     switch (bus->chipinfo.id) {
0087     case BCMA_CHIP_ID_BCM43142:
0088         /* pmu2_xtaltab0_adfll_485 */
0089         switch (xtalfreq) {
0090         case 12000:
0091             freq_tgt_target = 0x50D52;
0092             break;
0093         case 20000:
0094             freq_tgt_target = 0x307FE;
0095             break;
0096         case 26000:
0097             freq_tgt_target = 0x254EA;
0098             break;
0099         case 37400:
0100             freq_tgt_target = 0x19EF8;
0101             break;
0102         case 52000:
0103             freq_tgt_target = 0x12A75;
0104             break;
0105         }
0106         break;
0107     }
0108 
0109     if (!freq_tgt_target) {
0110         bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
0111              xtalfreq);
0112         return;
0113     }
0114 
0115     pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
0116     freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
0117         BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
0118 
0119     if (freq_tgt_current == freq_tgt_target) {
0120         bcma_debug(bus, "Target TGT frequency already set\n");
0121         return;
0122     }
0123 
0124     /* Turn off PLL */
0125     switch (bus->chipinfo.id) {
0126     case BCMA_CHIP_ID_BCM43142:
0127         mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
0128                   BCMA_RES_4314_MACPHY_CLK_AVAIL);
0129 
0130         bcma_pmu_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
0131         bcma_pmu_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
0132         bcma_wait_value(cc->core, BCMA_CLKCTLST,
0133                 BCMA_CLKCTLST_HAVEHT, 0, 20000);
0134         break;
0135     }
0136 
0137     pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
0138     pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
0139     bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
0140 
0141     /* Flush */
0142     if (cc->pmu.rev >= 2)
0143         bcma_pmu_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
0144 
0145     /* TODO: Do we need to update OTP? */
0146 }
0147 
0148 static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
0149 {
0150     struct bcma_bus *bus = cc->core->bus;
0151     u32 xtalfreq = bcma_pmu_xtalfreq(cc);
0152 
0153     switch (bus->chipinfo.id) {
0154     case BCMA_CHIP_ID_BCM43142:
0155         if (xtalfreq == 0)
0156             xtalfreq = 20000;
0157         bcma_pmu2_pll_init0(cc, xtalfreq);
0158         break;
0159     }
0160 }
0161 
0162 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
0163 {
0164     struct bcma_bus *bus = cc->core->bus;
0165     u32 min_msk = 0, max_msk = 0;
0166 
0167     switch (bus->chipinfo.id) {
0168     case BCMA_CHIP_ID_BCM4313:
0169         min_msk = 0x200D;
0170         max_msk = 0xFFFF;
0171         break;
0172     case BCMA_CHIP_ID_BCM43142:
0173         min_msk = BCMA_RES_4314_LPLDO_PU |
0174               BCMA_RES_4314_PMU_SLEEP_DIS |
0175               BCMA_RES_4314_PMU_BG_PU |
0176               BCMA_RES_4314_CBUCK_LPOM_PU |
0177               BCMA_RES_4314_CBUCK_PFM_PU |
0178               BCMA_RES_4314_CLDO_PU |
0179               BCMA_RES_4314_LPLDO2_LVM |
0180               BCMA_RES_4314_WL_PMU_PU |
0181               BCMA_RES_4314_LDO3P3_PU |
0182               BCMA_RES_4314_OTP_PU |
0183               BCMA_RES_4314_WL_PWRSW_PU |
0184               BCMA_RES_4314_LQ_AVAIL |
0185               BCMA_RES_4314_LOGIC_RET |
0186               BCMA_RES_4314_MEM_SLEEP |
0187               BCMA_RES_4314_MACPHY_RET |
0188               BCMA_RES_4314_WL_CORE_READY;
0189         max_msk = 0x3FFFFFFF;
0190         break;
0191     default:
0192         bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
0193                bus->chipinfo.id);
0194     }
0195 
0196     /* Set the resource masks. */
0197     if (min_msk)
0198         bcma_pmu_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
0199     if (max_msk)
0200         bcma_pmu_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
0201 
0202     /*
0203      * Add some delay; allow resources to come up and settle.
0204      * Delay is required for SoC (early init).
0205      */
0206     usleep_range(2000, 2500);
0207 }
0208 
0209 /* Disable to allow reading SPROM. Don't know the advantages of enabling it. */
0210 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
0211 {
0212     struct bcma_bus *bus = cc->core->bus;
0213     u32 val;
0214 
0215     val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
0216     if (enable) {
0217         val |= BCMA_CHIPCTL_4331_EXTPA_EN;
0218         if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
0219             val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
0220         else if (bus->chipinfo.rev > 0)
0221             val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
0222     } else {
0223         val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
0224         val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
0225         val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
0226     }
0227     bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
0228 }
0229 
0230 static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
0231 {
0232     struct bcma_bus *bus = cc->core->bus;
0233 
0234     switch (bus->chipinfo.id) {
0235     case BCMA_CHIP_ID_BCM4313:
0236         /*
0237          * enable 12 mA drive strength for 4313 and set chipControl
0238          * register bit 1
0239          */
0240         bcma_chipco_chipctl_maskset(cc, 0,
0241                         ~BCMA_CCTRL_4313_12MA_LED_DRIVE,
0242                         BCMA_CCTRL_4313_12MA_LED_DRIVE);
0243         break;
0244     case BCMA_CHIP_ID_BCM4331:
0245     case BCMA_CHIP_ID_BCM43431:
0246         /* Ext PA lines must be enabled for tx on BCM4331 */
0247         bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
0248         break;
0249     case BCMA_CHIP_ID_BCM43224:
0250     case BCMA_CHIP_ID_BCM43421:
0251         /*
0252          * enable 12 mA drive strength for 43224 and set chipControl
0253          * register bit 15
0254          */
0255         if (bus->chipinfo.rev == 0) {
0256             bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
0257                       ~BCMA_CCTRL_43224_GPIO_TOGGLE,
0258                       BCMA_CCTRL_43224_GPIO_TOGGLE);
0259             bcma_chipco_chipctl_maskset(cc, 0,
0260                             ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
0261                             BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
0262         } else {
0263             bcma_chipco_chipctl_maskset(cc, 0,
0264                             ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
0265                             BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
0266         }
0267         break;
0268     default:
0269         bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
0270                bus->chipinfo.id);
0271     }
0272 }
0273 
0274 void bcma_pmu_early_init(struct bcma_drv_cc *cc)
0275 {
0276     struct bcma_bus *bus = cc->core->bus;
0277     u32 pmucap;
0278 
0279     if (cc->core->id.rev >= 35 &&
0280         cc->capabilities_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
0281         cc->pmu.core = bcma_find_core(bus, BCMA_CORE_PMU);
0282         if (!cc->pmu.core)
0283             bcma_warn(bus, "Couldn't find expected PMU core");
0284     }
0285     if (!cc->pmu.core)
0286         cc->pmu.core = cc->core;
0287 
0288     pmucap = bcma_pmu_read32(cc, BCMA_CC_PMU_CAP);
0289     cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
0290 
0291     bcma_debug(bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
0292            pmucap);
0293 }
0294 
0295 void bcma_pmu_init(struct bcma_drv_cc *cc)
0296 {
0297     if (cc->pmu.rev == 1)
0298         bcma_pmu_mask32(cc, BCMA_CC_PMU_CTL,
0299                 ~BCMA_CC_PMU_CTL_NOILPONW);
0300     else
0301         bcma_pmu_set32(cc, BCMA_CC_PMU_CTL,
0302                    BCMA_CC_PMU_CTL_NOILPONW);
0303 
0304     bcma_pmu_pll_init(cc);
0305     bcma_pmu_resources_init(cc);
0306     bcma_pmu_workarounds(cc);
0307 }
0308 
0309 u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
0310 {
0311     struct bcma_bus *bus = cc->core->bus;
0312 
0313     switch (bus->chipinfo.id) {
0314     case BCMA_CHIP_ID_BCM4313:
0315     case BCMA_CHIP_ID_BCM43224:
0316     case BCMA_CHIP_ID_BCM43225:
0317     case BCMA_CHIP_ID_BCM43227:
0318     case BCMA_CHIP_ID_BCM43228:
0319     case BCMA_CHIP_ID_BCM4331:
0320     case BCMA_CHIP_ID_BCM43421:
0321     case BCMA_CHIP_ID_BCM43428:
0322     case BCMA_CHIP_ID_BCM43431:
0323     case BCMA_CHIP_ID_BCM4716:
0324     case BCMA_CHIP_ID_BCM47162:
0325     case BCMA_CHIP_ID_BCM4748:
0326     case BCMA_CHIP_ID_BCM4749:
0327     case BCMA_CHIP_ID_BCM5357:
0328     case BCMA_CHIP_ID_BCM53572:
0329     case BCMA_CHIP_ID_BCM6362:
0330         /* always 20Mhz */
0331         return 20000 * 1000;
0332     case BCMA_CHIP_ID_BCM4706:
0333     case BCMA_CHIP_ID_BCM5356:
0334         /* always 25Mhz */
0335         return 25000 * 1000;
0336     case BCMA_CHIP_ID_BCM43460:
0337     case BCMA_CHIP_ID_BCM4352:
0338     case BCMA_CHIP_ID_BCM4360:
0339         if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
0340             return 40000 * 1000;
0341         else
0342             return 20000 * 1000;
0343     default:
0344         bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
0345               bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
0346     }
0347     return BCMA_CC_PMU_ALP_CLOCK;
0348 }
0349 
0350 /* Find the output of the "m" pll divider given pll controls that start with
0351  * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
0352  */
0353 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
0354 {
0355     u32 tmp, div, ndiv, p1, p2, fc;
0356     struct bcma_bus *bus = cc->core->bus;
0357 
0358     BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
0359 
0360     BUG_ON(!m || m > 4);
0361 
0362     if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
0363         bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
0364         /* Detect failure in clock setting */
0365         tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
0366         if (tmp & 0x40000)
0367             return 133 * 1000000;
0368     }
0369 
0370     tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
0371     p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
0372     p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
0373 
0374     tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
0375     div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
0376         BCMA_CC_PPL_MDIV_MASK;
0377 
0378     tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
0379     ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
0380 
0381     /* Do calculation in Mhz */
0382     fc = bcma_pmu_get_alp_clock(cc) / 1000000;
0383     fc = (p1 * ndiv * fc) / p2;
0384 
0385     /* Return clock in Hertz */
0386     return (fc / div) * 1000000;
0387 }
0388 
0389 static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
0390 {
0391     u32 tmp, ndiv, p1div, p2div;
0392     u32 clock;
0393 
0394     BUG_ON(!m || m > 4);
0395 
0396     /* Get N, P1 and P2 dividers to determine CPU clock */
0397     tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
0398     ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
0399         >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
0400     p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
0401         >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
0402     p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
0403         >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
0404 
0405     tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
0406     if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
0407         /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
0408         clock = (25000000 / 4) * ndiv * p2div / p1div;
0409     else
0410         /* Fixed reference clock 25MHz and m = 2 */
0411         clock = (25000000 / 2) * ndiv * p2div / p1div;
0412 
0413     if (m == BCMA_CC_PMU5_MAINPLL_SSB)
0414         clock = clock / 4;
0415 
0416     return clock;
0417 }
0418 
0419 /* query bus clock frequency for PMU-enabled chipcommon */
0420 u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
0421 {
0422     struct bcma_bus *bus = cc->core->bus;
0423 
0424     switch (bus->chipinfo.id) {
0425     case BCMA_CHIP_ID_BCM4716:
0426     case BCMA_CHIP_ID_BCM4748:
0427     case BCMA_CHIP_ID_BCM47162:
0428         return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
0429                       BCMA_CC_PMU5_MAINPLL_SSB);
0430     case BCMA_CHIP_ID_BCM5356:
0431         return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
0432                       BCMA_CC_PMU5_MAINPLL_SSB);
0433     case BCMA_CHIP_ID_BCM5357:
0434     case BCMA_CHIP_ID_BCM4749:
0435         return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
0436                       BCMA_CC_PMU5_MAINPLL_SSB);
0437     case BCMA_CHIP_ID_BCM4706:
0438         return bcma_pmu_pll_clock_bcm4706(cc,
0439                           BCMA_CC_PMU4706_MAINPLL_PLL0,
0440                           BCMA_CC_PMU5_MAINPLL_SSB);
0441     case BCMA_CHIP_ID_BCM53572:
0442         return 75000000;
0443     default:
0444         bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
0445               bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
0446     }
0447     return BCMA_CC_PMU_HT_CLOCK;
0448 }
0449 EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
0450 
0451 /* query cpu clock frequency for PMU-enabled chipcommon */
0452 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
0453 {
0454     struct bcma_bus *bus = cc->core->bus;
0455 
0456     if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
0457         return 300000000;
0458 
0459     /* New PMUs can have different clock for bus and CPU */
0460     if (cc->pmu.rev >= 5) {
0461         u32 pll;
0462         switch (bus->chipinfo.id) {
0463         case BCMA_CHIP_ID_BCM4706:
0464             return bcma_pmu_pll_clock_bcm4706(cc,
0465                         BCMA_CC_PMU4706_MAINPLL_PLL0,
0466                         BCMA_CC_PMU5_MAINPLL_CPU);
0467         case BCMA_CHIP_ID_BCM5356:
0468             pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
0469             break;
0470         case BCMA_CHIP_ID_BCM5357:
0471         case BCMA_CHIP_ID_BCM4749:
0472             pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
0473             break;
0474         default:
0475             pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
0476             break;
0477         }
0478 
0479         return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
0480     }
0481 
0482     /* On old PMUs CPU has the same clock as the bus */
0483     return bcma_pmu_get_bus_clock(cc);
0484 }
0485 
0486 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
0487                      u32 value)
0488 {
0489     bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
0490     bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
0491 }
0492 
0493 void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
0494 {
0495     u32 tmp = 0;
0496     u8 phypll_offset = 0;
0497     u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
0498     u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
0499     struct bcma_bus *bus = cc->core->bus;
0500 
0501     switch (bus->chipinfo.id) {
0502     case BCMA_CHIP_ID_BCM5357:
0503     case BCMA_CHIP_ID_BCM4749:
0504     case BCMA_CHIP_ID_BCM53572:
0505         /* 5357[ab]0, 43236[ab]0, and 6362b0 */
0506 
0507         /*
0508          * BCM5357 needs to touch PLL1_PLLCTL[02],
0509          * so offset PLL0_PLLCTL[02] by 6
0510          */
0511         phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
0512                bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
0513                bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
0514 
0515         /* RMW only the P1 divider */
0516         bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
0517                 BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
0518         tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
0519         tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
0520         tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
0521         bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
0522 
0523         /* RMW only the int feedback divider */
0524         bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
0525                 BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
0526         tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
0527         tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
0528         tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
0529         bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
0530 
0531         tmp = BCMA_CC_PMU_CTL_PLL_UPD;
0532         break;
0533 
0534     case BCMA_CHIP_ID_BCM4331:
0535     case BCMA_CHIP_ID_BCM43431:
0536         if (spuravoid == 2) {
0537             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0538                              0x11500014);
0539             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0540                              0x0FC00a08);
0541         } else if (spuravoid == 1) {
0542             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0543                              0x11500014);
0544             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0545                              0x0F600a08);
0546         } else {
0547             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0548                              0x11100014);
0549             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0550                              0x03000a08);
0551         }
0552         tmp = BCMA_CC_PMU_CTL_PLL_UPD;
0553         break;
0554 
0555     case BCMA_CHIP_ID_BCM43224:
0556     case BCMA_CHIP_ID_BCM43225:
0557     case BCMA_CHIP_ID_BCM43421:
0558         if (spuravoid == 1) {
0559             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0560                              0x11500010);
0561             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
0562                              0x000C0C06);
0563             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0564                              0x0F600a08);
0565             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
0566                              0x00000000);
0567             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
0568                              0x2001E920);
0569             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
0570                              0x88888815);
0571         } else {
0572             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0573                              0x11100010);
0574             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
0575                              0x000c0c06);
0576             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0577                              0x03000a08);
0578             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
0579                              0x00000000);
0580             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
0581                              0x200005c0);
0582             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
0583                              0x88888815);
0584         }
0585         tmp = BCMA_CC_PMU_CTL_PLL_UPD;
0586         break;
0587 
0588     case BCMA_CHIP_ID_BCM4716:
0589     case BCMA_CHIP_ID_BCM4748:
0590     case BCMA_CHIP_ID_BCM47162:
0591         if (spuravoid == 1) {
0592             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0593                              0x11500060);
0594             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
0595                              0x080C0C06);
0596             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0597                              0x0F600000);
0598             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
0599                              0x00000000);
0600             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
0601                              0x2001E924);
0602             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
0603                              0x88888815);
0604         } else {
0605             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0606                              0x11100060);
0607             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
0608                              0x080c0c06);
0609             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0610                              0x03000000);
0611             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
0612                              0x00000000);
0613             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
0614                              0x200005c0);
0615             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
0616                              0x88888815);
0617         }
0618 
0619         tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
0620         break;
0621 
0622     case BCMA_CHIP_ID_BCM43131:
0623     case BCMA_CHIP_ID_BCM43217:
0624     case BCMA_CHIP_ID_BCM43227:
0625     case BCMA_CHIP_ID_BCM43228:
0626     case BCMA_CHIP_ID_BCM43428:
0627         /* LCNXN */
0628         /*
0629          * PLL Settings for spur avoidance on/off mode,
0630          * no on2 support for 43228A0
0631          */
0632         if (spuravoid == 1) {
0633             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0634                              0x01100014);
0635             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
0636                              0x040C0C06);
0637             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0638                              0x03140A08);
0639             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
0640                              0x00333333);
0641             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
0642                              0x202C2820);
0643             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
0644                              0x88888815);
0645         } else {
0646             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0647                              0x11100014);
0648             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
0649                              0x040c0c06);
0650             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0651                              0x03000a08);
0652             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
0653                              0x00000000);
0654             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
0655                              0x200005c0);
0656             bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
0657                              0x88888815);
0658         }
0659         tmp = BCMA_CC_PMU_CTL_PLL_UPD;
0660         break;
0661     default:
0662         bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
0663              bus->chipinfo.id);
0664         break;
0665     }
0666 
0667     tmp |= bcma_pmu_read32(cc, BCMA_CC_PMU_CTL);
0668     bcma_pmu_write32(cc, BCMA_CC_PMU_CTL, tmp);
0669 }
0670 EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
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