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0001 /******************************************************************* 
0002  *
0003  * Copyright (c) 2000 ATecoM GmbH 
0004  *
0005  * The author may be reached at ecd@atecom.com.
0006  *
0007  * This program is free software; you can redistribute  it and/or modify it
0008  * under  the terms of  the GNU General  Public License as published by the
0009  * Free Software Foundation;  either version 2 of the  License, or (at your
0010  * option) any later version.
0011  *
0012  * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR   IMPLIED
0013  * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
0014  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
0015  * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
0016  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0017  * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
0018  * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0019  * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
0020  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0021  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0022  *
0023  * You should have received a copy of the  GNU General Public License along
0024  * with this program; if not, write  to the Free Software Foundation, Inc.,
0025  * 675 Mass Ave, Cambridge, MA 02139, USA.
0026  *
0027  *******************************************************************/
0028 
0029 #ifndef _IDT77252_H
0030 #define _IDT77252_H 1
0031 
0032 
0033 #include <linux/ptrace.h>
0034 #include <linux/skbuff.h>
0035 #include <linux/workqueue.h>
0036 #include <linux/mutex.h>
0037 
0038 /*****************************************************************************/
0039 /*                                                                           */
0040 /* Makros                                                                    */
0041 /*                                                                           */
0042 /*****************************************************************************/
0043 #define VPCI2VC(card, vpi, vci) \
0044         (((vpi) << card->vcibits) | ((vci) & card->vcimask))
0045 
0046 /*****************************************************************************/
0047 /*                                                                           */
0048 /*   DEBUGGING definitions                                                   */
0049 /*                                                                           */
0050 /*****************************************************************************/
0051 
0052 #define DBG_RAW_CELL    0x00000400
0053 #define DBG_TINY    0x00000200
0054 #define DBG_GENERAL     0x00000100
0055 #define DBG_XGENERAL    0x00000080
0056 #define DBG_INIT        0x00000040
0057 #define DBG_DEINIT      0x00000020
0058 #define DBG_INTERRUPT   0x00000010
0059 #define DBG_OPEN_CONN   0x00000008
0060 #define DBG_CLOSE_CONN  0x00000004
0061 #define DBG_RX_DATA     0x00000002
0062 #define DBG_TX_DATA     0x00000001
0063 
0064 #ifdef CONFIG_ATM_IDT77252_DEBUG
0065 
0066 #define CPRINTK(args...)   do { if (debug & DBG_CLOSE_CONN) printk(args); } while(0)
0067 #define OPRINTK(args...)   do { if (debug & DBG_OPEN_CONN)  printk(args); } while(0)
0068 #define IPRINTK(args...)   do { if (debug & DBG_INIT)       printk(args); } while(0)
0069 #define INTPRINTK(args...) do { if (debug & DBG_INTERRUPT)  printk(args); } while(0)
0070 #define DIPRINTK(args...)  do { if (debug & DBG_DEINIT)     printk(args); } while(0)
0071 #define TXPRINTK(args...)  do { if (debug & DBG_TX_DATA)    printk(args); } while(0)
0072 #define RXPRINTK(args...)  do { if (debug & DBG_RX_DATA)    printk(args); } while(0)
0073 #define XPRINTK(args...)   do { if (debug & DBG_XGENERAL)   printk(args); } while(0)
0074 #define DPRINTK(args...)   do { if (debug & DBG_GENERAL)    printk(args); } while(0)
0075 #define NPRINTK(args...)   do { if (debug & DBG_TINY)       printk(args); } while(0)
0076 #define RPRINTK(args...)   do { if (debug & DBG_RAW_CELL)   printk(args); } while(0)
0077 
0078 #else
0079 
0080 #define CPRINTK(args...)    do { } while(0)
0081 #define OPRINTK(args...)    do { } while(0)
0082 #define IPRINTK(args...)    do { } while(0)
0083 #define INTPRINTK(args...)  do { } while(0)
0084 #define DIPRINTK(args...)   do { } while(0)
0085 #define TXPRINTK(args...)   do { } while(0)
0086 #define RXPRINTK(args...)   do { } while(0)
0087 #define XPRINTK(args...)    do { } while(0)
0088 #define DPRINTK(args...)    do { } while(0)
0089 #define NPRINTK(args...)    do { } while(0)
0090 #define RPRINTK(args...)    do { } while(0)
0091 
0092 #endif
0093 
0094 #define SCHED_UBR0      0
0095 #define SCHED_UBR       1
0096 #define SCHED_VBR       2
0097 #define SCHED_ABR       3
0098 #define SCHED_CBR       4
0099 
0100 #define SCQFULL_TIMEOUT     HZ
0101 
0102 /*****************************************************************************/
0103 /*                                                                           */
0104 /*   Free Buffer Queue Layout                                                */
0105 /*                                                                           */
0106 /*****************************************************************************/
0107 #define SAR_FB_SIZE_0       (2048 - 256)
0108 #define SAR_FB_SIZE_1       (4096 - 256)
0109 #define SAR_FB_SIZE_2       (8192 - 256)
0110 #define SAR_FB_SIZE_3       (16384 - 256)
0111 
0112 #define SAR_FBQ0_LOW        4
0113 #define SAR_FBQ0_HIGH       8
0114 #define SAR_FBQ1_LOW        2
0115 #define SAR_FBQ1_HIGH       4
0116 #define SAR_FBQ2_LOW        1
0117 #define SAR_FBQ2_HIGH       2
0118 #define SAR_FBQ3_LOW        1
0119 #define SAR_FBQ3_HIGH       2
0120 
0121 #if 0
0122 #define SAR_TST_RESERVED    44  /* Num TST reserved for UBR/ABR/VBR */
0123 #else
0124 #define SAR_TST_RESERVED    0   /* Num TST reserved for UBR/ABR/VBR */
0125 #endif
0126 
0127 #define TCT_CBR         0x00000000
0128 #define TCT_UBR         0x00000000
0129 #define TCT_VBR         0x40000000
0130 #define TCT_ABR         0x80000000
0131 #define TCT_TYPE        0xc0000000
0132 
0133 #define TCT_RR          0x20000000
0134 #define TCT_LMCR        0x08000000
0135 #define TCT_SCD_MASK        0x0007ffff
0136 
0137 #define TCT_TSIF        0x00004000
0138 #define TCT_HALT        0x80000000
0139 #define TCT_IDLE        0x40000000
0140 #define TCT_FLAG_UBR        0x80000000
0141 
0142 /*****************************************************************************/
0143 /*                                                                           */
0144 /*   Structure describing an IDT77252                                        */
0145 /*                                                                           */
0146 /*****************************************************************************/
0147 
0148 struct scqe
0149 {
0150     u32     word_1;
0151     u32     word_2;
0152     u32     word_3;
0153     u32     word_4;
0154 };
0155 
0156 #define SCQ_ENTRIES 64
0157 #define SCQ_SIZE    (SCQ_ENTRIES * sizeof(struct scqe))
0158 #define SCQ_MASK    (SCQ_SIZE - 1)
0159 
0160 struct scq_info
0161 {
0162     struct scqe     *base;
0163     struct scqe     *next;
0164     struct scqe     *last;
0165     dma_addr_t      paddr;
0166     spinlock_t      lock;
0167     atomic_t        used;
0168     unsigned long       trans_start;
0169         unsigned long       scd;
0170     spinlock_t      skblock;
0171     struct sk_buff_head transmit;
0172     struct sk_buff_head pending;
0173 };
0174 
0175 struct rx_pool {
0176     struct sk_buff_head queue;
0177     unsigned int        len;
0178 };
0179 
0180 struct aal1 {
0181     unsigned int        total;
0182     unsigned int        count;
0183     struct sk_buff      *data;
0184     unsigned char       sequence;
0185 };
0186 
0187 struct vc_map;
0188 
0189 struct rate_estimator {
0190     struct timer_list   timer;
0191     unsigned int        interval;
0192     unsigned int        ewma_log;
0193     u64         cells;
0194     u64         last_cells;
0195     long            avcps;
0196     u32         cps;
0197     u32         maxcps;
0198     struct vc_map       *vc;
0199 };
0200 
0201 struct vc_map {
0202     unsigned int        index;
0203     unsigned long       flags;
0204 #define VCF_TX      0
0205 #define VCF_RX      1
0206 #define VCF_IDLE    2
0207 #define VCF_RSV     3
0208     unsigned int        class;
0209     u8          init_er;
0210     u8          lacr;
0211     u8          max_er;
0212     unsigned int        ntste;
0213     spinlock_t      lock;
0214     struct atm_vcc      *tx_vcc;
0215     struct atm_vcc      *rx_vcc;
0216     struct idt77252_dev *card;
0217     struct scq_info     *scq;       /* To keep track of the SCQ */
0218     struct rate_estimator   *estimator;
0219     int         scd_index;
0220     union {
0221         struct rx_pool  rx_pool;
0222         struct aal1 aal1;
0223     } rcv;
0224 };
0225 
0226 /*****************************************************************************/
0227 /*                                                                           */
0228 /*   RCTE - Receive Connection Table Entry                                   */
0229 /*                                                                           */
0230 /*****************************************************************************/
0231 
0232 struct rct_entry
0233 {
0234     u32     word_1;
0235     u32     buffer_handle;
0236     u32     dma_address;
0237     u32     aal5_crc32;
0238 };
0239 
0240 /*****************************************************************************/
0241 /*                                                                           */
0242 /*   RSQ - Receive Status Queue                                              */
0243 /*                                                                           */
0244 /*****************************************************************************/
0245 
0246 #define SAR_RSQE_VALID      0x80000000
0247 #define SAR_RSQE_IDLE       0x40000000
0248 #define SAR_RSQE_BUF_MASK   0x00030000
0249 #define SAR_RSQE_BUF_ASGN   0x00008000
0250 #define SAR_RSQE_NZGFC      0x00004000
0251 #define SAR_RSQE_EPDU       0x00002000
0252 #define SAR_RSQE_BUF_CONT   0x00001000
0253 #define SAR_RSQE_EFCIE      0x00000800
0254 #define SAR_RSQE_CLP        0x00000400
0255 #define SAR_RSQE_CRC        0x00000200
0256 #define SAR_RSQE_CELLCNT    0x000001FF
0257 
0258 
0259 #define RSQSIZE            8192
0260 #define RSQ_NUM_ENTRIES    (RSQSIZE / 16)
0261 #define RSQ_ALIGNMENT      8192
0262 
0263 struct rsq_entry {
0264     u32         word_1;
0265     u32         word_2;
0266     u32         word_3;
0267     u32         word_4;
0268 };
0269 
0270 struct rsq_info {
0271     struct rsq_entry    *base;
0272     struct rsq_entry    *next;
0273     struct rsq_entry    *last;
0274     dma_addr_t      paddr;
0275 };
0276 
0277 
0278 /*****************************************************************************/
0279 /*                                                                           */
0280 /*   TSQ - Transmit Status Queue                                             */
0281 /*                                                                           */
0282 /*****************************************************************************/
0283 
0284 #define SAR_TSQE_INVALID         0x80000000
0285 #define SAR_TSQE_TIMESTAMP       0x00FFFFFF
0286 #define SAR_TSQE_TYPE        0x60000000
0287 #define SAR_TSQE_TYPE_TIMER      0x00000000
0288 #define SAR_TSQE_TYPE_TSR        0x20000000
0289 #define SAR_TSQE_TYPE_IDLE       0x40000000
0290 #define SAR_TSQE_TYPE_TBD_COMP   0x60000000
0291 
0292 #define SAR_TSQE_TAG(stat)  (((stat) >> 24) & 0x1f)
0293 
0294 #define TSQSIZE            8192
0295 #define TSQ_NUM_ENTRIES    1024
0296 #define TSQ_ALIGNMENT      8192
0297 
0298 struct tsq_entry
0299 {
0300     u32         word_1;
0301     u32         word_2;
0302 };
0303 
0304 struct tsq_info
0305 {
0306     struct tsq_entry    *base;
0307     struct tsq_entry    *next;
0308     struct tsq_entry    *last;
0309     dma_addr_t      paddr;
0310 };
0311 
0312 struct tst_info
0313 {
0314     struct vc_map       *vc;
0315     u32         tste;
0316 };
0317 
0318 #define TSTE_MASK       0x601fffff
0319 
0320 #define TSTE_OPC_MASK       0x60000000
0321 #define TSTE_OPC_NULL       0x00000000
0322 #define TSTE_OPC_CBR        0x20000000
0323 #define TSTE_OPC_VAR        0x40000000
0324 #define TSTE_OPC_JMP        0x60000000
0325 
0326 #define TSTE_PUSH_IDLE      0x01000000
0327 #define TSTE_PUSH_ACTIVE    0x02000000
0328 
0329 #define TST_SWITCH_DONE     0
0330 #define TST_SWITCH_PENDING  1
0331 #define TST_SWITCH_WAIT     2
0332 
0333 #define FBQ_SHIFT       9
0334 #define FBQ_SIZE        (1 << FBQ_SHIFT)
0335 #define FBQ_MASK        (FBQ_SIZE - 1)
0336 
0337 struct sb_pool
0338 {
0339     unsigned int        index;
0340     struct sk_buff      *skb[FBQ_SIZE];
0341 };
0342 
0343 #define POOL_HANDLE(queue, index)   (((queue + 1) << 16) | (index))
0344 #define POOL_QUEUE(handle)      (((handle) >> 16) - 1)
0345 #define POOL_INDEX(handle)      ((handle) & 0xffff)
0346 
0347 struct idt77252_dev
0348 {
0349         struct tsq_info     tsq;        /* Transmit Status Queue */
0350         struct rsq_info     rsq;        /* Receive Status Queue */
0351 
0352     struct pci_dev      *pcidev;    /* PCI handle (desriptor) */
0353     struct atm_dev      *atmdev;    /* ATM device desriptor */
0354 
0355     void __iomem        *membase;   /* SAR's memory base address */
0356     unsigned long       srambase;   /* SAR's sram  base address */
0357     void __iomem        *fbq[4];    /* FBQ fill addresses */
0358 
0359     struct mutex        mutex;
0360     spinlock_t      cmd_lock;   /* for r/w utility/sram */
0361 
0362     unsigned long       softstat;
0363     unsigned long       flags;      /* see blow */
0364 
0365     struct work_struct  tqueue;
0366 
0367     unsigned long       tct_base;   /* TCT base address in SRAM */
0368         unsigned long       rct_base;   /* RCT base address in SRAM */
0369         unsigned long       rt_base;    /* Rate Table base in SRAM */
0370         unsigned long       scd_base;   /* SCD base address in SRAM */
0371         unsigned long       tst[2];     /* TST base address in SRAM */
0372     unsigned long       abrst_base; /* ABRST base address in SRAM */
0373         unsigned long       fifo_base;  /* RX FIFO base in SRAM */
0374 
0375     unsigned long       irqstat[16];
0376 
0377     unsigned int        sramsize;   /* SAR's sram size */
0378 
0379         unsigned int        tct_size;   /* total TCT entries */
0380         unsigned int        rct_size;   /* total RCT entries */
0381         unsigned int        scd_size;   /* length of SCD */
0382         unsigned int        tst_size;   /* total TST entries */
0383         unsigned int        tst_free;   /* free TSTEs in TST */
0384         unsigned int        abrst_size; /* size of ABRST in words */
0385         unsigned int        fifo_size;  /* size of RX FIFO in words */
0386 
0387         unsigned int        vpibits;    /* Bits used for VPI index */
0388         unsigned int        vcibits;    /* Bits used for VCI index */
0389         unsigned int        vcimask;    /* Mask for VCI index */
0390 
0391     unsigned int        utopia_pcr; /* Utopia Itf's Cell Rate */
0392     unsigned int        link_pcr;   /* PHY's Peek Cell Rate */
0393 
0394     struct vc_map       **vcs;      /* Open Connections */
0395     struct vc_map       **scd2vc;   /* SCD to Connection map */
0396 
0397     struct tst_info     *soft_tst;  /* TST to Connection map */
0398     unsigned int        tst_index;  /* Current TST in use */
0399     struct timer_list   tst_timer;
0400     spinlock_t      tst_lock;
0401     unsigned long       tst_state;
0402 
0403     struct sb_pool      sbpool[4];  /* Pool of RX skbuffs */
0404     struct sk_buff      *raw_cell_head; /* Pointer to raw cell queue */
0405     u32         *raw_cell_hnd;  /* Pointer to RCQ handle */
0406     dma_addr_t      raw_cell_paddr;
0407 
0408     int         index;      /* SAR's ID */
0409     int         revision;   /* chip revision */
0410 
0411     char            name[16];   /* Device name */
0412 
0413     struct idt77252_dev *next;
0414 };
0415 
0416 
0417 /* definition for flag field above */
0418 #define IDT77252_BIT_INIT       1
0419 #define IDT77252_BIT_INTERRUPT      2
0420 
0421 
0422 #define ATM_CELL_PAYLOAD         48
0423 
0424 #define FREEBUF_ALIGNMENT        16
0425 
0426 /*****************************************************************************/
0427 /*                                                                           */
0428 /* Makros                                                                    */
0429 /*                                                                           */
0430 /*****************************************************************************/
0431 #define ALIGN_ADDRESS(addr, alignment) \
0432         ((((u32)(addr)) + (((u32)(alignment))-1)) & ~(((u32)(alignment)) - 1))
0433 
0434 
0435 /*****************************************************************************/
0436 /*                                                                           */
0437 /*   ABR SAR Network operation Register                                      */
0438 /*                                                                           */
0439 /*****************************************************************************/
0440 
0441 #define SAR_REG_DR0 (card->membase + 0x00)
0442 #define SAR_REG_DR1 (card->membase + 0x04)
0443 #define SAR_REG_DR2 (card->membase + 0x08)
0444 #define SAR_REG_DR3 (card->membase + 0x0C)
0445 #define SAR_REG_CMD (card->membase + 0x10)
0446 #define SAR_REG_CFG (card->membase + 0x14)
0447 #define SAR_REG_STAT    (card->membase + 0x18)
0448 #define SAR_REG_RSQB    (card->membase + 0x1C)
0449 #define SAR_REG_RSQT    (card->membase + 0x20)
0450 #define SAR_REG_RSQH    (card->membase + 0x24)
0451 #define SAR_REG_CDC (card->membase + 0x28)
0452 #define SAR_REG_VPEC    (card->membase + 0x2C)
0453 #define SAR_REG_ICC (card->membase + 0x30)
0454 #define SAR_REG_RAWCT   (card->membase + 0x34)
0455 #define SAR_REG_TMR (card->membase + 0x38)
0456 #define SAR_REG_TSTB    (card->membase + 0x3C)
0457 #define SAR_REG_TSQB    (card->membase + 0x40)
0458 #define SAR_REG_TSQT    (card->membase + 0x44)
0459 #define SAR_REG_TSQH    (card->membase + 0x48)
0460 #define SAR_REG_GP  (card->membase + 0x4C)
0461 #define SAR_REG_VPM (card->membase + 0x50)
0462 #define SAR_REG_RXFD    (card->membase + 0x54)
0463 #define SAR_REG_RXFT    (card->membase + 0x58)
0464 #define SAR_REG_RXFH    (card->membase + 0x5C)
0465 #define SAR_REG_RAWHND  (card->membase + 0x60)
0466 #define SAR_REG_RXSTAT  (card->membase + 0x64)
0467 #define SAR_REG_ABRSTD  (card->membase + 0x68)
0468 #define SAR_REG_ABRRQ   (card->membase + 0x6C)
0469 #define SAR_REG_VBRRQ   (card->membase + 0x70)
0470 #define SAR_REG_RTBL    (card->membase + 0x74)
0471 #define SAR_REG_MDFCT   (card->membase + 0x78)
0472 #define SAR_REG_TXSTAT  (card->membase + 0x7C)
0473 #define SAR_REG_TCMDQ   (card->membase + 0x80)
0474 #define SAR_REG_IRCP    (card->membase + 0x84)
0475 #define SAR_REG_FBQP0   (card->membase + 0x88)
0476 #define SAR_REG_FBQP1   (card->membase + 0x8C)
0477 #define SAR_REG_FBQP2   (card->membase + 0x90)
0478 #define SAR_REG_FBQP3   (card->membase + 0x94)
0479 #define SAR_REG_FBQS0   (card->membase + 0x98)
0480 #define SAR_REG_FBQS1   (card->membase + 0x9C)
0481 #define SAR_REG_FBQS2   (card->membase + 0xA0)
0482 #define SAR_REG_FBQS3   (card->membase + 0xA4)
0483 #define SAR_REG_FBQWP0  (card->membase + 0xA8)
0484 #define SAR_REG_FBQWP1  (card->membase + 0xAC)
0485 #define SAR_REG_FBQWP2  (card->membase + 0xB0)
0486 #define SAR_REG_FBQWP3  (card->membase + 0xB4)
0487 #define SAR_REG_NOW (card->membase + 0xB8)
0488 
0489 
0490 /*****************************************************************************/
0491 /*                                                                           */
0492 /*   Commands                                                                */
0493 /*                                                                           */
0494 /*****************************************************************************/
0495 
0496 #define SAR_CMD_NO_OPERATION         0x00000000
0497 #define SAR_CMD_OPENCLOSE_CONNECTION 0x20000000
0498 #define SAR_CMD_WRITE_SRAM           0x40000000
0499 #define SAR_CMD_READ_SRAM            0x50000000
0500 #define SAR_CMD_READ_UTILITY         0x80000000
0501 #define SAR_CMD_WRITE_UTILITY        0x90000000
0502 
0503 #define SAR_CMD_OPEN_CONNECTION     (SAR_CMD_OPENCLOSE_CONNECTION | 0x00080000)
0504 #define SAR_CMD_CLOSE_CONNECTION     SAR_CMD_OPENCLOSE_CONNECTION
0505 
0506 
0507 /*****************************************************************************/
0508 /*                                                                           */
0509 /*   Configuration Register bits                                             */
0510 /*                                                                           */
0511 /*****************************************************************************/
0512 
0513 #define SAR_CFG_SWRST          0x80000000  /* Software reset                 */
0514 #define SAR_CFG_LOOP           0x40000000  /* Internal Loopback              */
0515 #define SAR_CFG_RXPTH          0x20000000  /* Receive Path Enable            */
0516 #define SAR_CFG_IDLE_CLP       0x10000000  /* SAR set CLP Bits of Null Cells */
0517 #define SAR_CFG_TX_FIFO_SIZE_1 0x04000000  /* TX FIFO Size = 1 cell          */
0518 #define SAR_CFG_TX_FIFO_SIZE_2 0x08000000  /* TX FIFO Size = 2 cells         */
0519 #define SAR_CFG_TX_FIFO_SIZE_4 0x0C000000  /* TX FIFO Size = 4 cells         */
0520 #define SAR_CFG_TX_FIFO_SIZE_9 0x00000000  /* TX FIFO Size = 9 cells (full)  */
0521 #define SAR_CFG_NO_IDLE        0x02000000  /* SAR sends no Null Cells        */
0522 #define SAR_CFG_RSVD1          0x01000000  /* Reserved                       */
0523 #define SAR_CFG_RXSTQ_SIZE_2k  0x00000000  /* RX Stat Queue Size = 2048 byte */
0524 #define SAR_CFG_RXSTQ_SIZE_4k  0x00400000  /* RX Stat Queue Size = 4096 byte */
0525 #define SAR_CFG_RXSTQ_SIZE_8k  0x00800000  /* RX Stat Queue Size = 8192 byte */
0526 #define SAR_CFG_RXSTQ_SIZE_R   0x00C00000  /* RX Stat Queue Size = reserved  */
0527 #define SAR_CFG_ICAPT          0x00200000  /* accept Invalid Cells           */
0528 #define SAR_CFG_IGGFC          0x00100000  /* Ignore GFC                     */
0529 #define SAR_CFG_VPVCS_0        0x00000000  /* VPI/VCI Select bit range       */
0530 #define SAR_CFG_VPVCS_1        0x00040000  /* VPI/VCI Select bit range       */
0531 #define SAR_CFG_VPVCS_2        0x00080000  /* VPI/VCI Select bit range       */
0532 #define SAR_CFG_VPVCS_8        0x000C0000  /* VPI/VCI Select bit range       */
0533 #define SAR_CFG_CNTBL_1k       0x00000000  /* Connection Table Size          */
0534 #define SAR_CFG_CNTBL_4k       0x00010000  /* Connection Table Size          */
0535 #define SAR_CFG_CNTBL_16k      0x00020000  /* Connection Table Size          */
0536 #define SAR_CFG_CNTBL_512      0x00030000  /* Connection Table Size          */
0537 #define SAR_CFG_VPECA          0x00008000  /* VPI/VCI Error Cell Accept      */
0538 #define SAR_CFG_RXINT_NOINT    0x00000000  /* No Interrupt on PDU received   */
0539 #define SAR_CFG_RXINT_NODELAY  0x00001000  /* Interrupt without delay to host*/
0540 #define SAR_CFG_RXINT_256US    0x00002000  /* Interrupt with delay 256 usec  */
0541 #define SAR_CFG_RXINT_505US    0x00003000  /* Interrupt with delay 505 usec  */
0542 #define SAR_CFG_RXINT_742US    0x00004000  /* Interrupt with delay 742 usec  */
0543 #define SAR_CFG_RAWIE          0x00000800  /* Raw Cell Queue Interrupt Enable*/
0544 #define SAR_CFG_RQFIE          0x00000400  /* RSQ Almost Full Int Enable     */
0545 #define SAR_CFG_RSVD2          0x00000200  /* Reserved                       */
0546 #define SAR_CFG_CACHE          0x00000100  /* DMA on Cache Line Boundary     */
0547 #define SAR_CFG_TMOIE          0x00000080  /* Timer Roll Over Int Enable     */
0548 #define SAR_CFG_FBIE           0x00000040  /* Free Buffer Queue Int Enable   */
0549 #define SAR_CFG_TXEN           0x00000020  /* Transmit Operation Enable      */
0550 #define SAR_CFG_TXINT          0x00000010  /* Transmit status Int Enable     */
0551 #define SAR_CFG_TXUIE          0x00000008  /* Transmit underrun Int Enable   */
0552 #define SAR_CFG_UMODE          0x00000004  /* Utopia Mode Select             */
0553 #define SAR_CFG_TXSFI          0x00000002  /* Transmit status Full Int Enable*/
0554 #define SAR_CFG_PHYIE          0x00000001  /* PHY Interrupt Enable           */
0555 
0556 #define SAR_CFG_TX_FIFO_SIZE_MASK 0x0C000000  /* TX FIFO Size Mask           */
0557 #define SAR_CFG_RXSTQSIZE_MASK 0x00C00000
0558 #define SAR_CFG_CNTBL_MASK     0x00030000
0559 #define SAR_CFG_RXINT_MASK     0x00007000
0560 
0561 
0562 /*****************************************************************************/
0563 /*                                                                           */
0564 /*   Status Register bits                                                    */
0565 /*                                                                           */
0566 /*****************************************************************************/
0567 
0568 #define SAR_STAT_FRAC_3     0xF0000000 /* Fraction of Free Buffer Queue 3 */
0569 #define SAR_STAT_FRAC_2     0x0F000000 /* Fraction of Free Buffer Queue 2 */
0570 #define SAR_STAT_FRAC_1     0x00F00000 /* Fraction of Free Buffer Queue 1 */
0571 #define SAR_STAT_FRAC_0     0x000F0000 /* Fraction of Free Buffer Queue 0 */
0572 #define SAR_STAT_TSIF       0x00008000 /* Transmit Status Indicator       */
0573 #define SAR_STAT_TXICP      0x00004000 /* Transmit Status Indicator       */
0574 #define SAR_STAT_RSVD1      0x00002000 /* Reserved                        */
0575 #define SAR_STAT_TSQF       0x00001000 /* Transmit Status Queue full      */
0576 #define SAR_STAT_TMROF      0x00000800 /* Timer overflow                  */
0577 #define SAR_STAT_PHYI       0x00000400 /* PHY device Interrupt flag       */
0578 #define SAR_STAT_CMDBZ      0x00000200 /* ABR SAR Command Busy Flag       */
0579 #define SAR_STAT_FBQ3A      0x00000100 /* Free Buffer Queue 3 Attention   */
0580 #define SAR_STAT_FBQ2A      0x00000080 /* Free Buffer Queue 2 Attention   */
0581 #define SAR_STAT_RSQF       0x00000040 /* Receive Status Queue full       */
0582 #define SAR_STAT_EPDU       0x00000020 /* End Of PDU Flag                 */
0583 #define SAR_STAT_RAWCF      0x00000010 /* Raw Cell Flag                   */ 
0584 #define SAR_STAT_FBQ1A      0x00000008 /* Free Buffer Queue 1 Attention   */
0585 #define SAR_STAT_FBQ0A      0x00000004 /* Free Buffer Queue 0 Attention   */
0586 #define SAR_STAT_RSQAF      0x00000002 /* Receive Status Queue almost full*/  
0587 #define SAR_STAT_RSVD2      0x00000001 /* Reserved                        */
0588 
0589 
0590 /*****************************************************************************/
0591 /*                                                                           */
0592 /*   General Purpose Register bits                                           */
0593 /*                                                                           */
0594 /*****************************************************************************/
0595 
0596 #define SAR_GP_TXNCC_MASK   0xff000000  /* Transmit Negative Credit Count   */
0597 #define SAR_GP_EEDI         0x00010000  /* EEPROM Data In                   */
0598 #define SAR_GP_BIGE         0x00008000  /* Big Endian Operation             */
0599 #define SAR_GP_RM_NORMAL    0x00000000  /* Normal handling of RM cells      */
0600 #define SAR_GP_RM_TO_RCQ    0x00002000  /* put RM cells into Raw Cell Queue */
0601 #define SAR_GP_RM_RSVD      0x00004000  /* Reserved                         */
0602 #define SAR_GP_RM_INHIBIT   0x00006000  /* Inhibit update of Connection tab */
0603 #define SAR_GP_PHY_RESET    0x00000008  /* PHY Reset                        */
0604 #define SAR_GP_EESCLK       0x00000004  /* EEPROM SCLK              */
0605 #define SAR_GP_EECS     0x00000002  /* EEPROM Chip Select           */
0606 #define SAR_GP_EEDO     0x00000001  /* EEPROM Data Out          */
0607 
0608 
0609 /*****************************************************************************/
0610 /*                                                                           */
0611 /*   SAR local SRAM layout for 128k work SRAM                                */
0612 /*                                                                           */
0613 /*****************************************************************************/
0614 
0615 #define SAR_SRAM_SCD_SIZE        12
0616 #define SAR_SRAM_TCT_SIZE         8
0617 #define SAR_SRAM_RCT_SIZE         4
0618 
0619 #define SAR_SRAM_TCT_128_BASE    0x00000
0620 #define SAR_SRAM_TCT_128_TOP     0x01fff
0621 #define SAR_SRAM_RCT_128_BASE    0x02000
0622 #define SAR_SRAM_RCT_128_TOP     0x02fff
0623 #define SAR_SRAM_FB0_128_BASE    0x03000
0624 #define SAR_SRAM_FB0_128_TOP     0x033ff
0625 #define SAR_SRAM_FB1_128_BASE    0x03400
0626 #define SAR_SRAM_FB1_128_TOP     0x037ff
0627 #define SAR_SRAM_FB2_128_BASE    0x03800
0628 #define SAR_SRAM_FB2_128_TOP     0x03bff
0629 #define SAR_SRAM_FB3_128_BASE    0x03c00
0630 #define SAR_SRAM_FB3_128_TOP     0x03fff
0631 #define SAR_SRAM_SCD_128_BASE    0x04000
0632 #define SAR_SRAM_SCD_128_TOP     0x07fff
0633 #define SAR_SRAM_TST1_128_BASE   0x08000
0634 #define SAR_SRAM_TST1_128_TOP    0x0bfff
0635 #define SAR_SRAM_TST2_128_BASE   0x0c000
0636 #define SAR_SRAM_TST2_128_TOP    0x0ffff
0637 #define SAR_SRAM_ABRSTD_128_BASE 0x10000
0638 #define SAR_SRAM_ABRSTD_128_TOP  0x13fff
0639 #define SAR_SRAM_RT_128_BASE     0x14000
0640 #define SAR_SRAM_RT_128_TOP      0x15fff
0641 
0642 #define SAR_SRAM_FIFO_128_BASE   0x18000
0643 #define SAR_SRAM_FIFO_128_TOP    0x1ffff
0644 
0645 
0646 /*****************************************************************************/
0647 /*                                                                           */
0648 /*   SAR local SRAM layout for 32k work SRAM                                 */
0649 /*                                                                           */
0650 /*****************************************************************************/
0651 
0652 #define SAR_SRAM_TCT_32_BASE     0x00000
0653 #define SAR_SRAM_TCT_32_TOP      0x00fff
0654 #define SAR_SRAM_RCT_32_BASE     0x01000
0655 #define SAR_SRAM_RCT_32_TOP      0x017ff
0656 #define SAR_SRAM_FB0_32_BASE     0x01800
0657 #define SAR_SRAM_FB0_32_TOP      0x01bff
0658 #define SAR_SRAM_FB1_32_BASE     0x01c00
0659 #define SAR_SRAM_FB1_32_TOP      0x01fff
0660 #define SAR_SRAM_FB2_32_BASE     0x02000
0661 #define SAR_SRAM_FB2_32_TOP      0x023ff
0662 #define SAR_SRAM_FB3_32_BASE     0x02400
0663 #define SAR_SRAM_FB3_32_TOP      0x027ff
0664 #define SAR_SRAM_SCD_32_BASE     0x02800
0665 #define SAR_SRAM_SCD_32_TOP      0x03fff
0666 #define SAR_SRAM_TST1_32_BASE    0x04000
0667 #define SAR_SRAM_TST1_32_TOP     0x04fff
0668 #define SAR_SRAM_TST2_32_BASE    0x05000
0669 #define SAR_SRAM_TST2_32_TOP     0x05fff
0670 #define SAR_SRAM_ABRSTD_32_BASE  0x06000
0671 #define SAR_SRAM_ABRSTD_32_TOP   0x067ff
0672 #define SAR_SRAM_RT_32_BASE      0x06800
0673 #define SAR_SRAM_RT_32_TOP       0x06fff
0674 #define SAR_SRAM_FIFO_32_BASE    0x07000
0675 #define SAR_SRAM_FIFO_32_TOP     0x07fff
0676 
0677 
0678 /*****************************************************************************/
0679 /*                                                                           */
0680 /*   TSR - Transmit Status Request                                           */
0681 /*                                                                           */
0682 /*****************************************************************************/
0683 
0684 #define SAR_TSR_TYPE_TSR  0x80000000
0685 #define SAR_TSR_TYPE_TBD  0x00000000
0686 #define SAR_TSR_TSIF      0x20000000
0687 #define SAR_TSR_TAG_MASK  0x01F00000
0688 
0689 
0690 /*****************************************************************************/
0691 /*                                                                           */
0692 /*   TBD - Transmit Buffer Descriptor                                        */
0693 /*                                                                           */
0694 /*****************************************************************************/
0695 
0696 #define SAR_TBD_EPDU      0x40000000
0697 #define SAR_TBD_TSIF      0x20000000
0698 #define SAR_TBD_OAM       0x10000000
0699 #define SAR_TBD_AAL0      0x00000000
0700 #define SAR_TBD_AAL34     0x04000000
0701 #define SAR_TBD_AAL5      0x08000000
0702 #define SAR_TBD_GTSI      0x02000000
0703 #define SAR_TBD_TAG_MASK  0x01F00000
0704 
0705 #define SAR_TBD_VPI_MASK  0x0FF00000
0706 #define SAR_TBD_VCI_MASK  0x000FFFF0
0707 #define SAR_TBD_VC_MASK   (SAR_TBD_VPI_MASK | SAR_TBD_VCI_MASK)
0708 
0709 #define SAR_TBD_VPI_SHIFT 20
0710 #define SAR_TBD_VCI_SHIFT 4
0711 
0712 
0713 /*****************************************************************************/
0714 /*                                                                           */
0715 /*   RXFD - Receive FIFO Descriptor                                          */
0716 /*                                                                           */
0717 /*****************************************************************************/
0718 
0719 #define SAR_RXFD_SIZE_MASK     0x0F000000
0720 #define SAR_RXFD_SIZE_512      0x00000000  /* 512 words                      */
0721 #define SAR_RXFD_SIZE_1K       0x01000000  /* 1k words                       */
0722 #define SAR_RXFD_SIZE_2K       0x02000000  /* 2k words                       */
0723 #define SAR_RXFD_SIZE_4K       0x03000000  /* 4k words                       */
0724 #define SAR_RXFD_SIZE_8K       0x04000000  /* 8k words                       */
0725 #define SAR_RXFD_SIZE_16K      0x05000000  /* 16k words                      */
0726 #define SAR_RXFD_SIZE_32K      0x06000000  /* 32k words                      */
0727 #define SAR_RXFD_SIZE_64K      0x07000000  /* 64k words                      */
0728 #define SAR_RXFD_SIZE_128K     0x08000000  /* 128k words                     */
0729 #define SAR_RXFD_SIZE_256K     0x09000000  /* 256k words                     */
0730 #define SAR_RXFD_ADDR_MASK     0x001ffc00
0731 
0732 
0733 /*****************************************************************************/
0734 /*                                                                           */
0735 /*   ABRSTD - ABR + VBR Schedule Tables                                      */
0736 /*                                                                           */
0737 /*****************************************************************************/
0738 
0739 #define SAR_ABRSTD_SIZE_MASK   0x07000000
0740 #define SAR_ABRSTD_SIZE_512    0x00000000  /* 512 words                      */
0741 #define SAR_ABRSTD_SIZE_1K     0x01000000  /* 1k words                       */
0742 #define SAR_ABRSTD_SIZE_2K     0x02000000  /* 2k words                       */
0743 #define SAR_ABRSTD_SIZE_4K     0x03000000  /* 4k words                       */
0744 #define SAR_ABRSTD_SIZE_8K     0x04000000  /* 8k words                       */
0745 #define SAR_ABRSTD_SIZE_16K    0x05000000  /* 16k words                      */
0746 #define SAR_ABRSTD_ADDR_MASK   0x001ffc00
0747 
0748 
0749 /*****************************************************************************/
0750 /*                                                                           */
0751 /*   RCTE - Receive Connection Table Entry                                   */
0752 /*                                                                           */
0753 /*****************************************************************************/
0754 
0755 #define SAR_RCTE_IL_MASK       0xE0000000  /* inactivity limit               */
0756 #define SAR_RCTE_IC_MASK       0x1C000000  /* inactivity count               */
0757 #define SAR_RCTE_RSVD          0x02000000  /* reserved                       */
0758 #define SAR_RCTE_LCD           0x01000000  /* last cell data                 */
0759 #define SAR_RCTE_CI_VC         0x00800000  /* EFCI in previous cell of VC    */
0760 #define SAR_RCTE_FBP_01        0x00000000  /* 1. cell->FBQ0, others->FBQ1    */
0761 #define SAR_RCTE_FBP_1         0x00200000  /* use FBQ 1 for all cells        */
0762 #define SAR_RCTE_FBP_2         0x00400000  /* use FBQ 2 for all cells        */
0763 #define SAR_RCTE_FBP_3         0x00600000  /* use FBQ 3 for all cells        */
0764 #define SAR_RCTE_NZ_GFC        0x00100000  /* non zero GFC in all cell of VC */
0765 #define SAR_RCTE_CONNECTOPEN   0x00080000  /* VC is open                     */
0766 #define SAR_RCTE_AAL_MASK      0x00070000  /* mask for AAL type field s.b.   */
0767 #define SAR_RCTE_RAWCELLINTEN  0x00008000  /* raw cell interrupt enable      */
0768 #define SAR_RCTE_RXCONCELLADDR 0x00004000  /* RX constant cell address       */
0769 #define SAR_RCTE_BUFFSTAT_MASK 0x00003000  /* buffer status                  */
0770 #define SAR_RCTE_EFCI          0x00000800  /* EFCI Congestion flag           */
0771 #define SAR_RCTE_CLP           0x00000400  /* Cell Loss Priority flag        */
0772 #define SAR_RCTE_CRC           0x00000200  /* Received CRC Error             */
0773 #define SAR_RCTE_CELLCNT_MASK  0x000001FF  /* cell Count                     */
0774 
0775 #define SAR_RCTE_AAL0          0x00000000  /* AAL types for ALL field        */
0776 #define SAR_RCTE_AAL34         0x00010000
0777 #define SAR_RCTE_AAL5          0x00020000
0778 #define SAR_RCTE_RCQ           0x00030000
0779 #define SAR_RCTE_OAM           0x00040000
0780 
0781 #define TCMDQ_START     0x01000000
0782 #define TCMDQ_LACR      0x02000000
0783 #define TCMDQ_START_LACR    0x03000000
0784 #define TCMDQ_INIT_ER       0x04000000
0785 #define TCMDQ_HALT      0x05000000
0786 
0787 
0788 struct idt77252_skb_prv {
0789     struct scqe tbd;    /* Transmit Buffer Descriptor */
0790     dma_addr_t  paddr;  /* DMA handle */
0791     u32     pool;   /* sb_pool handle */
0792 } __packed;
0793 
0794 #define IDT77252_PRV_TBD(skb)   \
0795     (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->tbd)
0796 #define IDT77252_PRV_PADDR(skb) \
0797     (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->paddr)
0798 #define IDT77252_PRV_POOL(skb)  \
0799     (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->pool)
0800 
0801 /*****************************************************************************/
0802 /*                                                                           */
0803 /*   PCI related items                                                       */
0804 /*                                                                           */
0805 /*****************************************************************************/
0806 
0807 #ifndef PCI_VENDOR_ID_IDT
0808 #define PCI_VENDOR_ID_IDT 0x111D
0809 #endif /* PCI_VENDOR_ID_IDT */
0810 
0811 #ifndef PCI_DEVICE_ID_IDT_IDT77252
0812 #define PCI_DEVICE_ID_IDT_IDT77252 0x0003
0813 #endif /* PCI_DEVICE_ID_IDT_IDT772052 */
0814 
0815 
0816 #endif /* !(_IDT77252_H) */
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