drivers/atm/idt77252.c

0001 /*******************************************************************
0002  *
0003  * Copyright (c) 2000 ATecoM GmbH
0004  *
0005  * The author may be reached at ecd@atecom.com.
0006  *
0007  * This program is free software; you can redistribute  it and/or modify it
0008  * under  the terms of  the GNU General  Public License as published by the
0009  * Free Software Foundation;  either version 2 of the  License, or (at your
0010  * option) any later version.
0011  *
0012  * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR   IMPLIED
0013  * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
0014  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
0015  * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
0016  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0017  * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
0018  * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0019  * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
0020  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0021  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0022  *
0023  * You should have received a copy of the  GNU General Public License along
0024  * with this program; if not, write  to the Free Software Foundation, Inc.,
0025  * 675 Mass Ave, Cambridge, MA 02139, USA.
0026  *
0027  *******************************************************************/
0028
0029 #include <linux/module.h>
0030 #include <linux/pci.h>
0031 #include <linux/poison.h>
0032 #include <linux/skbuff.h>
0033 #include <linux/kernel.h>
0034 #include <linux/vmalloc.h>
0035 #include <linux/netdevice.h>
0036 #include <linux/atmdev.h>
0037 #include <linux/atm.h>
0038 #include <linux/delay.h>
0039 #include <linux/init.h>
0040 #include <linux/interrupt.h>
0041 #include <linux/bitops.h>
0042 #include <linux/wait.h>
0043 #include <linux/jiffies.h>
0044 #include <linux/mutex.h>
0045 #include <linux/slab.h>
0046
0047 #include <asm/io.h>
0048 #include <linux/uaccess.h>
0049 #include <linux/atomic.h>
0050 #include <asm/byteorder.h>
0051
0052 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
0053 #include "suni.h"
0054 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
0055
0056
0057 #include "idt77252.h"
0058 #include "idt77252_tables.h"
0059
0060 static unsigned int vpibits = 1;
0061
0062
0063 #define ATM_IDT77252_SEND_IDLE 1
0064
0065
0066 /*
0067  * Debug HACKs.
0068  */
0069 #define DEBUG_MODULE 1
0070 #undef HAVE_EEPROM  /* does not work, yet. */
0071
0072 #ifdef CONFIG_ATM_IDT77252_DEBUG
0073 static unsigned long debug = DBG_GENERAL;
0074 #endif
0075
0076
0077 #define SAR_RX_DELAY    (SAR_CFG_RXINT_NODELAY)
0078
0079
0080 /*
0081  * SCQ Handling.
0082  */
0083 static struct scq_info *alloc_scq(struct idt77252_dev *, int);
0084 static void free_scq(struct idt77252_dev *, struct scq_info *);
0085 static int queue_skb(struct idt77252_dev *, struct vc_map *,
0086              struct sk_buff *, int oam);
0087 static void drain_scq(struct idt77252_dev *, struct vc_map *);
0088 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
0089 static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
0090
0091 /*
0092  * FBQ Handling.
0093  */
0094 static int push_rx_skb(struct idt77252_dev *,
0095                struct sk_buff *, int queue);
0096 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
0097 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
0098 static void recycle_rx_pool_skb(struct idt77252_dev *,
0099                 struct rx_pool *);
0100 static void add_rx_skb(struct idt77252_dev *, int queue,
0101                unsigned int size, unsigned int count);
0102
0103 /*
0104  * RSQ Handling.
0105  */
0106 static int init_rsq(struct idt77252_dev *);
0107 static void deinit_rsq(struct idt77252_dev *);
0108 static void idt77252_rx(struct idt77252_dev *);
0109
0110 /*
0111  * TSQ handling.
0112  */
0113 static int init_tsq(struct idt77252_dev *);
0114 static void deinit_tsq(struct idt77252_dev *);
0115 static void idt77252_tx(struct idt77252_dev *);
0116
0117
0118 /*
0119  * ATM Interface.
0120  */
0121 static void idt77252_dev_close(struct atm_dev *dev);
0122 static int idt77252_open(struct atm_vcc *vcc);
0123 static void idt77252_close(struct atm_vcc *vcc);
0124 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
0125 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
0126                  int flags);
0127 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
0128                  unsigned long addr);
0129 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
0130 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
0131                    int flags);
0132 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
0133                   char *page);
0134 static void idt77252_softint(struct work_struct *work);
0135
0136
0137 static const struct atmdev_ops idt77252_ops =
0138 {
0139     .dev_close  = idt77252_dev_close,
0140     .open       = idt77252_open,
0141     .close      = idt77252_close,
0142     .send       = idt77252_send,
0143     .send_oam   = idt77252_send_oam,
0144     .phy_put    = idt77252_phy_put,
0145     .phy_get    = idt77252_phy_get,
0146     .change_qos = idt77252_change_qos,
0147     .proc_read  = idt77252_proc_read,
0148     .owner      = THIS_MODULE
0149 };
0150
0151 static struct idt77252_dev *idt77252_chain = NULL;
0152 static unsigned int idt77252_sram_write_errors = 0;
0153
0154 /*****************************************************************************/
0155 /*                                                                           */
0156 /* I/O and Utility Bus                                                       */
0157 /*                                                                           */
0158 /*****************************************************************************/
0159
0160 static void
0161 waitfor_idle(struct idt77252_dev *card)
0162 {
0163     u32 stat;
0164
0165     stat = readl(SAR_REG_STAT);
0166     while (stat & SAR_STAT_CMDBZ)
0167         stat = readl(SAR_REG_STAT);
0168 }
0169
0170 static u32
0171 read_sram(struct idt77252_dev *card, unsigned long addr)
0172 {
0173     unsigned long flags;
0174     u32 value;
0175
0176     spin_lock_irqsave(&card->cmd_lock, flags);
0177     writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
0178     waitfor_idle(card);
0179     value = readl(SAR_REG_DR0);
0180     spin_unlock_irqrestore(&card->cmd_lock, flags);
0181     return value;
0182 }
0183
0184 static void
0185 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
0186 {
0187     unsigned long flags;
0188
0189     if ((idt77252_sram_write_errors == 0) &&
0190         (((addr > card->tst[0] + card->tst_size - 2) &&
0191           (addr < card->tst[0] + card->tst_size)) ||
0192          ((addr > card->tst[1] + card->tst_size - 2) &&
0193           (addr < card->tst[1] + card->tst_size)))) {
0194         printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
0195                card->name, addr, value);
0196     }
0197
0198     spin_lock_irqsave(&card->cmd_lock, flags);
0199     writel(value, SAR_REG_DR0);
0200     writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
0201     waitfor_idle(card);
0202     spin_unlock_irqrestore(&card->cmd_lock, flags);
0203 }
0204
0205 static u8
0206 read_utility(void *dev, unsigned long ubus_addr)
0207 {
0208     struct idt77252_dev *card = dev;
0209     unsigned long flags;
0210     u8 value;
0211
0212     if (!card) {
0213         printk("Error: No such device.\n");
0214         return -1;
0215     }
0216
0217     spin_lock_irqsave(&card->cmd_lock, flags);
0218     writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
0219     waitfor_idle(card);
0220     value = readl(SAR_REG_DR0);
0221     spin_unlock_irqrestore(&card->cmd_lock, flags);
0222     return value;
0223 }
0224
0225 static void
0226 write_utility(void *dev, unsigned long ubus_addr, u8 value)
0227 {
0228     struct idt77252_dev *card = dev;
0229     unsigned long flags;
0230
0231     if (!card) {
0232         printk("Error: No such device.\n");
0233         return;
0234     }
0235
0236     spin_lock_irqsave(&card->cmd_lock, flags);
0237     writel((u32) value, SAR_REG_DR0);
0238     writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
0239     waitfor_idle(card);
0240     spin_unlock_irqrestore(&card->cmd_lock, flags);
0241 }
0242
0243 #ifdef HAVE_EEPROM
0244 static u32 rdsrtab[] =
0245 {
0246     SAR_GP_EECS | SAR_GP_EESCLK,
0247     0,
0248     SAR_GP_EESCLK,          /* 0 */
0249     0,
0250     SAR_GP_EESCLK,          /* 0 */
0251     0,
0252     SAR_GP_EESCLK,          /* 0 */
0253     0,
0254     SAR_GP_EESCLK,          /* 0 */
0255     0,
0256     SAR_GP_EESCLK,          /* 0 */
0257     SAR_GP_EEDO,
0258     SAR_GP_EESCLK | SAR_GP_EEDO,    /* 1 */
0259     0,
0260     SAR_GP_EESCLK,          /* 0 */
0261     SAR_GP_EEDO,
0262     SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
0263 };
0264
0265 static u32 wrentab[] =
0266 {
0267     SAR_GP_EECS | SAR_GP_EESCLK,
0268     0,
0269     SAR_GP_EESCLK,          /* 0 */
0270     0,
0271     SAR_GP_EESCLK,          /* 0 */
0272     0,
0273     SAR_GP_EESCLK,          /* 0 */
0274     0,
0275     SAR_GP_EESCLK,          /* 0 */
0276     SAR_GP_EEDO,
0277     SAR_GP_EESCLK | SAR_GP_EEDO,    /* 1 */
0278     SAR_GP_EEDO,
0279     SAR_GP_EESCLK | SAR_GP_EEDO,    /* 1 */
0280     0,
0281     SAR_GP_EESCLK,          /* 0 */
0282     0,
0283     SAR_GP_EESCLK           /* 0 */
0284 };
0285
0286 static u32 rdtab[] =
0287 {
0288     SAR_GP_EECS | SAR_GP_EESCLK,
0289     0,
0290     SAR_GP_EESCLK,          /* 0 */
0291     0,
0292     SAR_GP_EESCLK,          /* 0 */
0293     0,
0294     SAR_GP_EESCLK,          /* 0 */
0295     0,
0296     SAR_GP_EESCLK,          /* 0 */
0297     0,
0298     SAR_GP_EESCLK,          /* 0 */
0299     0,
0300     SAR_GP_EESCLK,          /* 0 */
0301     SAR_GP_EEDO,
0302     SAR_GP_EESCLK | SAR_GP_EEDO,    /* 1 */
0303     SAR_GP_EEDO,
0304     SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
0305 };
0306
0307 static u32 wrtab[] =
0308 {
0309     SAR_GP_EECS | SAR_GP_EESCLK,
0310     0,
0311     SAR_GP_EESCLK,          /* 0 */
0312     0,
0313     SAR_GP_EESCLK,          /* 0 */
0314     0,
0315     SAR_GP_EESCLK,          /* 0 */
0316     0,
0317     SAR_GP_EESCLK,          /* 0 */
0318     0,
0319     SAR_GP_EESCLK,          /* 0 */
0320     0,
0321     SAR_GP_EESCLK,          /* 0 */
0322     SAR_GP_EEDO,
0323     SAR_GP_EESCLK | SAR_GP_EEDO,    /* 1 */
0324     0,
0325     SAR_GP_EESCLK           /* 0 */
0326 };
0327
0328 static u32 clktab[] =
0329 {
0330     0,
0331     SAR_GP_EESCLK,
0332     0,
0333     SAR_GP_EESCLK,
0334     0,
0335     SAR_GP_EESCLK,
0336     0,
0337     SAR_GP_EESCLK,
0338     0,
0339     SAR_GP_EESCLK,
0340     0,
0341     SAR_GP_EESCLK,
0342     0,
0343     SAR_GP_EESCLK,
0344     0,
0345     SAR_GP_EESCLK,
0346     0
0347 };
0348
0349 static u32
0350 idt77252_read_gp(struct idt77252_dev *card)
0351 {
0352     u32 gp;
0353
0354     gp = readl(SAR_REG_GP);
0355 #if 0
0356     printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
0357 #endif
0358     return gp;
0359 }
0360
0361 static void
0362 idt77252_write_gp(struct idt77252_dev *card, u32 value)
0363 {
0364     unsigned long flags;
0365
0366 #if 0
0367     printk("WR: %s %s %s\n", value & SAR_GP_EECS ? "   " : "/CS",
0368            value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
0369            value & SAR_GP_EEDO   ? "1" : "0");
0370 #endif
0371
0372     spin_lock_irqsave(&card->cmd_lock, flags);
0373     waitfor_idle(card);
0374     writel(value, SAR_REG_GP);
0375     spin_unlock_irqrestore(&card->cmd_lock, flags);
0376 }
0377
0378 static u8
0379 idt77252_eeprom_read_status(struct idt77252_dev *card)
0380 {
0381     u8 byte;
0382     u32 gp;
0383     int i, j;
0384
0385     gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
0386
0387     for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
0388         idt77252_write_gp(card, gp | rdsrtab[i]);
0389         udelay(5);
0390     }
0391     idt77252_write_gp(card, gp | SAR_GP_EECS);
0392     udelay(5);
0393
0394     byte = 0;
0395     for (i = 0, j = 0; i < 8; i++) {
0396         byte <<= 1;
0397
0398         idt77252_write_gp(card, gp | clktab[j++]);
0399         udelay(5);
0400
0401         byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
0402
0403         idt77252_write_gp(card, gp | clktab[j++]);
0404         udelay(5);
0405     }
0406     idt77252_write_gp(card, gp | SAR_GP_EECS);
0407     udelay(5);
0408
0409     return byte;
0410 }
0411
0412 static u8
0413 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
0414 {
0415     u8 byte;
0416     u32 gp;
0417     int i, j;
0418
0419     gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
0420
0421     for (i = 0; i < ARRAY_SIZE(rdtab); i++) {
0422         idt77252_write_gp(card, gp | rdtab[i]);
0423         udelay(5);
0424     }
0425     idt77252_write_gp(card, gp | SAR_GP_EECS);
0426     udelay(5);
0427
0428     for (i = 0, j = 0; i < 8; i++) {
0429         idt77252_write_gp(card, gp | clktab[j++] |
0430                     (offset & 1 ? SAR_GP_EEDO : 0));
0431         udelay(5);
0432
0433         idt77252_write_gp(card, gp | clktab[j++] |
0434                     (offset & 1 ? SAR_GP_EEDO : 0));
0435         udelay(5);
0436
0437         offset >>= 1;
0438     }
0439     idt77252_write_gp(card, gp | SAR_GP_EECS);
0440     udelay(5);
0441
0442     byte = 0;
0443     for (i = 0, j = 0; i < 8; i++) {
0444         byte <<= 1;
0445
0446         idt77252_write_gp(card, gp | clktab[j++]);
0447         udelay(5);
0448
0449         byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
0450
0451         idt77252_write_gp(card, gp | clktab[j++]);
0452         udelay(5);
0453     }
0454     idt77252_write_gp(card, gp | SAR_GP_EECS);
0455     udelay(5);
0456
0457     return byte;
0458 }
0459
0460 static void
0461 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
0462 {
0463     u32 gp;
0464     int i, j;
0465
0466     gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
0467
0468     for (i = 0; i < ARRAY_SIZE(wrentab); i++) {
0469         idt77252_write_gp(card, gp | wrentab[i]);
0470         udelay(5);
0471     }
0472     idt77252_write_gp(card, gp | SAR_GP_EECS);
0473     udelay(5);
0474
0475     for (i = 0; i < ARRAY_SIZE(wrtab); i++) {
0476         idt77252_write_gp(card, gp | wrtab[i]);
0477         udelay(5);
0478     }
0479     idt77252_write_gp(card, gp | SAR_GP_EECS);
0480     udelay(5);
0481
0482     for (i = 0, j = 0; i < 8; i++) {
0483         idt77252_write_gp(card, gp | clktab[j++] |
0484                     (offset & 1 ? SAR_GP_EEDO : 0));
0485         udelay(5);
0486
0487         idt77252_write_gp(card, gp | clktab[j++] |
0488                     (offset & 1 ? SAR_GP_EEDO : 0));
0489         udelay(5);
0490
0491         offset >>= 1;
0492     }
0493     idt77252_write_gp(card, gp | SAR_GP_EECS);
0494     udelay(5);
0495
0496     for (i = 0, j = 0; i < 8; i++) {
0497         idt77252_write_gp(card, gp | clktab[j++] |
0498                     (data & 1 ? SAR_GP_EEDO : 0));
0499         udelay(5);
0500
0501         idt77252_write_gp(card, gp | clktab[j++] |
0502                     (data & 1 ? SAR_GP_EEDO : 0));
0503         udelay(5);
0504
0505         data >>= 1;
0506     }
0507     idt77252_write_gp(card, gp | SAR_GP_EECS);
0508     udelay(5);
0509 }
0510
0511 static void
0512 idt77252_eeprom_init(struct idt77252_dev *card)
0513 {
0514     u32 gp;
0515
0516     gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
0517
0518     idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
0519     udelay(5);
0520     idt77252_write_gp(card, gp | SAR_GP_EECS);
0521     udelay(5);
0522     idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
0523     udelay(5);
0524     idt77252_write_gp(card, gp | SAR_GP_EECS);
0525     udelay(5);
0526 }
0527 #endif /* HAVE_EEPROM */
0528
0529
0530 #ifdef CONFIG_ATM_IDT77252_DEBUG
0531 static void
0532 dump_tct(struct idt77252_dev *card, int index)
0533 {
0534     unsigned long tct;
0535     int i;
0536
0537     tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
0538
0539     printk("%s: TCT %x:", card->name, index);
0540     for (i = 0; i < 8; i++) {
0541         printk(" %08x", read_sram(card, tct + i));
0542     }
0543     printk("\n");
0544 }
0545
0546 static void
0547 idt77252_tx_dump(struct idt77252_dev *card)
0548 {
0549     struct atm_vcc *vcc;
0550     struct vc_map *vc;
0551     int i;
0552
0553     printk("%s\n", __func__);
0554     for (i = 0; i < card->tct_size; i++) {
0555         vc = card->vcs[i];
0556         if (!vc)
0557             continue;
0558
0559         vcc = NULL;
0560         if (vc->rx_vcc)
0561             vcc = vc->rx_vcc;
0562         else if (vc->tx_vcc)
0563             vcc = vc->tx_vcc;
0564
0565         if (!vcc)
0566             continue;
0567
0568         printk("%s: Connection %d:\n", card->name, vc->index);
0569         dump_tct(card, vc->index);
0570     }
0571 }
0572 #endif
0573
0574
0575 /*****************************************************************************/
0576 /*                                                                           */
0577 /* SCQ Handling                                                              */
0578 /*                                                                           */
0579 /*****************************************************************************/
0580
0581 static int
0582 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
0583 {
0584     struct sb_pool *pool = &card->sbpool[queue];
0585     int index;
0586
0587     index = pool->index;
0588     while (pool->skb[index]) {
0589         index = (index + 1) & FBQ_MASK;
0590         if (index == pool->index)
0591             return -ENOBUFS;
0592     }
0593
0594     pool->skb[index] = skb;
0595     IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
0596
0597     pool->index = (index + 1) & FBQ_MASK;
0598     return 0;
0599 }
0600
0601 static void
0602 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
0603 {
0604     unsigned int queue, index;
0605     u32 handle;
0606
0607     handle = IDT77252_PRV_POOL(skb);
0608
0609     queue = POOL_QUEUE(handle);
0610     if (queue > 3)
0611         return;
0612
0613     index = POOL_INDEX(handle);
0614     if (index > FBQ_SIZE - 1)
0615         return;
0616
0617     card->sbpool[queue].skb[index] = NULL;
0618 }
0619
0620 static struct sk_buff *
0621 sb_pool_skb(struct idt77252_dev *card, u32 handle)
0622 {
0623     unsigned int queue, index;
0624
0625     queue = POOL_QUEUE(handle);
0626     if (queue > 3)
0627         return NULL;
0628
0629     index = POOL_INDEX(handle);
0630     if (index > FBQ_SIZE - 1)
0631         return NULL;
0632
0633     return card->sbpool[queue].skb[index];
0634 }
0635
0636 static struct scq_info *
0637 alloc_scq(struct idt77252_dev *card, int class)
0638 {
0639     struct scq_info *scq;
0640
0641     scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL);
0642     if (!scq)
0643         return NULL;
0644     scq->base = dma_alloc_coherent(&card->pcidev->dev, SCQ_SIZE,
0645                        &scq->paddr, GFP_KERNEL);
0646     if (scq->base == NULL) {
0647         kfree(scq);
0648         return NULL;
0649     }
0650
0651     scq->next = scq->base;
0652     scq->last = scq->base + (SCQ_ENTRIES - 1);
0653     atomic_set(&scq->used, 0);
0654
0655     spin_lock_init(&scq->lock);
0656     spin_lock_init(&scq->skblock);
0657
0658     skb_queue_head_init(&scq->transmit);
0659     skb_queue_head_init(&scq->pending);
0660
0661     TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
0662          scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
0663
0664     return scq;
0665 }
0666
0667 static void
0668 free_scq(struct idt77252_dev *card, struct scq_info *scq)
0669 {
0670     struct sk_buff *skb;
0671     struct atm_vcc *vcc;
0672
0673     dma_free_coherent(&card->pcidev->dev, SCQ_SIZE,
0674               scq->base, scq->paddr);
0675
0676     while ((skb = skb_dequeue(&scq->transmit))) {
0677         dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
0678                  skb->len, DMA_TO_DEVICE);
0679
0680         vcc = ATM_SKB(skb)->vcc;
0681         if (vcc->pop)
0682             vcc->pop(vcc, skb);
0683         else
0684             dev_kfree_skb(skb);
0685     }
0686
0687     while ((skb = skb_dequeue(&scq->pending))) {
0688         dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
0689                  skb->len, DMA_TO_DEVICE);
0690
0691         vcc = ATM_SKB(skb)->vcc;
0692         if (vcc->pop)
0693             vcc->pop(vcc, skb);
0694         else
0695             dev_kfree_skb(skb);
0696     }
0697
0698     kfree(scq);
0699 }
0700
0701
0702 static int
0703 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
0704 {
0705     struct scq_info *scq = vc->scq;
0706     unsigned long flags;
0707     struct scqe *tbd;
0708     int entries;
0709
0710     TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
0711
0712     atomic_inc(&scq->used);
0713     entries = atomic_read(&scq->used);
0714     if (entries > (SCQ_ENTRIES - 1)) {
0715         atomic_dec(&scq->used);
0716         goto out;
0717     }
0718
0719     skb_queue_tail(&scq->transmit, skb);
0720
0721     spin_lock_irqsave(&vc->lock, flags);
0722     if (vc->estimator) {
0723         struct atm_vcc *vcc = vc->tx_vcc;
0724         struct sock *sk = sk_atm(vcc);
0725
0726         vc->estimator->cells += (skb->len + 47) / 48;
0727         if (refcount_read(&sk->sk_wmem_alloc) >
0728             (sk->sk_sndbuf >> 1)) {
0729             u32 cps = vc->estimator->maxcps;
0730
0731             vc->estimator->cps = cps;
0732             vc->estimator->avcps = cps << 5;
0733             if (vc->lacr < vc->init_er) {
0734                 vc->lacr = vc->init_er;
0735                 writel(TCMDQ_LACR | (vc->lacr << 16) |
0736                        vc->index, SAR_REG_TCMDQ);
0737             }
0738         }
0739     }
0740     spin_unlock_irqrestore(&vc->lock, flags);
0741
0742     tbd = &IDT77252_PRV_TBD(skb);
0743
0744     spin_lock_irqsave(&scq->lock, flags);
0745     scq->next->word_1 = cpu_to_le32(tbd->word_1 |
0746                     SAR_TBD_TSIF | SAR_TBD_GTSI);
0747     scq->next->word_2 = cpu_to_le32(tbd->word_2);
0748     scq->next->word_3 = cpu_to_le32(tbd->word_3);
0749     scq->next->word_4 = cpu_to_le32(tbd->word_4);
0750
0751     if (scq->next == scq->last)
0752         scq->next = scq->base;
0753     else
0754         scq->next++;
0755
0756     write_sram(card, scq->scd,
0757            scq->paddr +
0758            (u32)((unsigned long)scq->next - (unsigned long)scq->base));
0759     spin_unlock_irqrestore(&scq->lock, flags);
0760
0761     scq->trans_start = jiffies;
0762
0763     if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
0764         writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
0765                SAR_REG_TCMDQ);
0766     }
0767
0768     TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
0769
0770     XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
0771         card->name, atomic_read(&scq->used),
0772         read_sram(card, scq->scd + 1), scq->next);
0773
0774     return 0;
0775
0776 out:
0777     if (time_after(jiffies, scq->trans_start + HZ)) {
0778         printk("%s: Error pushing TBD for %d.%d\n",
0779                card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
0780 #ifdef CONFIG_ATM_IDT77252_DEBUG
0781         idt77252_tx_dump(card);
0782 #endif
0783         scq->trans_start = jiffies;
0784     }
0785
0786     return -ENOBUFS;
0787 }
0788
0789
0790 static void
0791 drain_scq(struct idt77252_dev *card, struct vc_map *vc)
0792 {
0793     struct scq_info *scq = vc->scq;
0794     struct sk_buff *skb;
0795     struct atm_vcc *vcc;
0796
0797     TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
0798          card->name, atomic_read(&scq->used), scq->next);
0799
0800     skb = skb_dequeue(&scq->transmit);
0801     if (skb) {
0802         TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
0803
0804         dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
0805                  skb->len, DMA_TO_DEVICE);
0806
0807         vcc = ATM_SKB(skb)->vcc;
0808
0809         if (vcc->pop)
0810             vcc->pop(vcc, skb);
0811         else
0812             dev_kfree_skb(skb);
0813
0814         atomic_inc(&vcc->stats->tx);
0815     }
0816
0817     atomic_dec(&scq->used);
0818
0819     spin_lock(&scq->skblock);
0820     while ((skb = skb_dequeue(&scq->pending))) {
0821         if (push_on_scq(card, vc, skb)) {
0822             skb_queue_head(&vc->scq->pending, skb);
0823             break;
0824         }
0825     }
0826     spin_unlock(&scq->skblock);
0827 }
0828
0829 static int
0830 queue_skb(struct idt77252_dev *card, struct vc_map *vc,
0831       struct sk_buff *skb, int oam)
0832 {
0833     struct atm_vcc *vcc;
0834     struct scqe *tbd;
0835     unsigned long flags;
0836     int error;
0837     int aal;
0838     u32 word4;
0839
0840     if (skb->len == 0) {
0841         printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
0842         return -EINVAL;
0843     }
0844
0845     TXPRINTK("%s: Sending %d bytes of data.\n",
0846          card->name, skb->len);
0847
0848     tbd = &IDT77252_PRV_TBD(skb);
0849     vcc = ATM_SKB(skb)->vcc;
0850     word4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
0851             (skb->data[2] <<  8) | (skb->data[3] <<  0);
0852
0853     IDT77252_PRV_PADDR(skb) = dma_map_single(&card->pcidev->dev, skb->data,
0854                          skb->len, DMA_TO_DEVICE);
0855
0856     error = -EINVAL;
0857
0858     if (oam) {
0859         if (skb->len != 52)
0860             goto errout;
0861
0862         tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
0863         tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
0864         tbd->word_3 = 0x00000000;
0865         tbd->word_4 = word4;
0866
0867         if (test_bit(VCF_RSV, &vc->flags))
0868             vc = card->vcs[0];
0869
0870         goto done;
0871     }
0872
0873     if (test_bit(VCF_RSV, &vc->flags)) {
0874         printk("%s: Trying to transmit on reserved VC\n", card->name);
0875         goto errout;
0876     }
0877
0878     aal = vcc->qos.aal;
0879
0880     switch (aal) {
0881     case ATM_AAL0:
0882     case ATM_AAL34:
0883         if (skb->len > 52)
0884             goto errout;
0885
0886         if (aal == ATM_AAL0)
0887             tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
0888                       ATM_CELL_PAYLOAD;
0889         else
0890             tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
0891                       ATM_CELL_PAYLOAD;
0892
0893         tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
0894         tbd->word_3 = 0x00000000;
0895         tbd->word_4 = word4;
0896         break;
0897
0898     case ATM_AAL5:
0899         tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
0900         tbd->word_2 = IDT77252_PRV_PADDR(skb);
0901         tbd->word_3 = skb->len;
0902         tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
0903                   (vcc->vci << SAR_TBD_VCI_SHIFT);
0904         break;
0905
0906     case ATM_AAL1:
0907     case ATM_AAL2:
0908     default:
0909         printk("%s: Traffic type not supported.\n", card->name);
0910         error = -EPROTONOSUPPORT;
0911         goto errout;
0912     }
0913
0914 done:
0915     spin_lock_irqsave(&vc->scq->skblock, flags);
0916     skb_queue_tail(&vc->scq->pending, skb);
0917
0918     while ((skb = skb_dequeue(&vc->scq->pending))) {
0919         if (push_on_scq(card, vc, skb)) {
0920             skb_queue_head(&vc->scq->pending, skb);
0921             break;
0922         }
0923     }
0924     spin_unlock_irqrestore(&vc->scq->skblock, flags);
0925
0926     return 0;
0927
0928 errout:
0929     dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
0930              skb->len, DMA_TO_DEVICE);
0931     return error;
0932 }
0933
0934 static unsigned long
0935 get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
0936 {
0937     int i;
0938
0939     for (i = 0; i < card->scd_size; i++) {
0940         if (!card->scd2vc[i]) {
0941             card->scd2vc[i] = vc;
0942             vc->scd_index = i;
0943             return card->scd_base + i * SAR_SRAM_SCD_SIZE;
0944         }
0945     }
0946     return 0;
0947 }
0948
0949 static void
0950 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
0951 {
0952     write_sram(card, scq->scd, scq->paddr);
0953     write_sram(card, scq->scd + 1, 0x00000000);
0954     write_sram(card, scq->scd + 2, 0xffffffff);
0955     write_sram(card, scq->scd + 3, 0x00000000);
0956 }
0957
0958 static void
0959 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
0960 {
0961     return;
0962 }
0963
0964 /*****************************************************************************/
0965 /*                                                                           */
0966 /* RSQ Handling                                                              */
0967 /*                                                                           */
0968 /*****************************************************************************/
0969
0970 static int
0971 init_rsq(struct idt77252_dev *card)
0972 {
0973     struct rsq_entry *rsqe;
0974
0975     card->rsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE,
0976                         &card->rsq.paddr, GFP_KERNEL);
0977     if (card->rsq.base == NULL) {
0978         printk("%s: can't allocate RSQ.\n", card->name);
0979         return -1;
0980     }
0981
0982     card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
0983     card->rsq.next = card->rsq.last;
0984     for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
0985         rsqe->word_4 = 0;
0986
0987     writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
0988            SAR_REG_RSQH);
0989     writel(card->rsq.paddr, SAR_REG_RSQB);
0990
0991     IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
0992         (unsigned long) card->rsq.base,
0993         readl(SAR_REG_RSQB));
0994     IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
0995         card->name,
0996         readl(SAR_REG_RSQH),
0997         readl(SAR_REG_RSQB),
0998         readl(SAR_REG_RSQT));
0999
1000     return 0;
1001 }
1002
1003 static void
1004 deinit_rsq(struct idt77252_dev *card)
1005 {
1006     dma_free_coherent(&card->pcidev->dev, RSQSIZE,
1007               card->rsq.base, card->rsq.paddr);
1008 }
1009
1010 static void
1011 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1012 {
1013     struct atm_vcc *vcc;
1014     struct sk_buff *skb;
1015     struct rx_pool *rpp;
1016     struct vc_map *vc;
1017     u32 header, vpi, vci;
1018     u32 stat;
1019     int i;
1020
1021     stat = le32_to_cpu(rsqe->word_4);
1022
1023     if (stat & SAR_RSQE_IDLE) {
1024         RXPRINTK("%s: message about inactive connection.\n",
1025              card->name);
1026         return;
1027     }
1028
1029     skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1030     if (skb == NULL) {
1031         printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1032                card->name, __func__,
1033                le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1034                le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1035         return;
1036     }
1037
1038     header = le32_to_cpu(rsqe->word_1);
1039     vpi = (header >> 16) & 0x00ff;
1040     vci = (header >>  0) & 0xffff;
1041
1042     RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1043          card->name, vpi, vci, skb, skb->data);
1044
1045     if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1046         printk("%s: SDU received for out-of-range vc %u.%u\n",
1047                card->name, vpi, vci);
1048         recycle_rx_skb(card, skb);
1049         return;
1050     }
1051
1052     vc = card->vcs[VPCI2VC(card, vpi, vci)];
1053     if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1054         printk("%s: SDU received on non RX vc %u.%u\n",
1055                card->name, vpi, vci);
1056         recycle_rx_skb(card, skb);
1057         return;
1058     }
1059
1060     vcc = vc->rx_vcc;
1061
1062     dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1063                 skb_end_pointer(skb) - skb->data,
1064                 DMA_FROM_DEVICE);
1065
1066     if ((vcc->qos.aal == ATM_AAL0) ||
1067         (vcc->qos.aal == ATM_AAL34)) {
1068         struct sk_buff *sb;
1069         unsigned char *cell;
1070         u32 aal0;
1071
1072         cell = skb->data;
1073         for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1074             if ((sb = dev_alloc_skb(64)) == NULL) {
1075                 printk("%s: Can't allocate buffers for aal0.\n",
1076                        card->name);
1077                 atomic_add(i, &vcc->stats->rx_drop);
1078                 break;
1079             }
1080             if (!atm_charge(vcc, sb->truesize)) {
1081                 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1082                      card->name);
1083                 atomic_add(i - 1, &vcc->stats->rx_drop);
1084                 dev_kfree_skb(sb);
1085                 break;
1086             }
1087             aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1088                    (vci << ATM_HDR_VCI_SHIFT);
1089             aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1090             aal0 |= (stat & SAR_RSQE_CLP)  ? 0x00000001 : 0;
1091
1092             *((u32 *) sb->data) = aal0;
1093             skb_put(sb, sizeof(u32));
1094             skb_put_data(sb, cell, ATM_CELL_PAYLOAD);
1095
1096             ATM_SKB(sb)->vcc = vcc;
1097             __net_timestamp(sb);
1098             vcc->push(vcc, sb);
1099             atomic_inc(&vcc->stats->rx);
1100
1101             cell += ATM_CELL_PAYLOAD;
1102         }
1103
1104         recycle_rx_skb(card, skb);
1105         return;
1106     }
1107     if (vcc->qos.aal != ATM_AAL5) {
1108         printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1109                card->name, vcc->qos.aal);
1110         recycle_rx_skb(card, skb);
1111         return;
1112     }
1113     skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1114
1115     rpp = &vc->rcv.rx_pool;
1116
1117     __skb_queue_tail(&rpp->queue, skb);
1118     rpp->len += skb->len;
1119
1120     if (stat & SAR_RSQE_EPDU) {
1121         unsigned char *l1l2;
1122         unsigned int len;
1123
1124         l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1125
1126         len = (l1l2[0] << 8) | l1l2[1];
1127         len = len ? len : 0x10000;
1128
1129         RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1130
1131         if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1132             RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1133                      "(CDC: %08x)\n",
1134                      card->name, len, rpp->len, readl(SAR_REG_CDC));
1135             recycle_rx_pool_skb(card, rpp);
1136             atomic_inc(&vcc->stats->rx_err);
1137             return;
1138         }
1139         if (stat & SAR_RSQE_CRC) {
1140             RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1141             recycle_rx_pool_skb(card, rpp);
1142             atomic_inc(&vcc->stats->rx_err);
1143             return;
1144         }
1145         if (skb_queue_len(&rpp->queue) > 1) {
1146             struct sk_buff *sb;
1147
1148             skb = dev_alloc_skb(rpp->len);
1149             if (!skb) {
1150                 RXPRINTK("%s: Can't alloc RX skb.\n",
1151                      card->name);
1152                 recycle_rx_pool_skb(card, rpp);
1153                 atomic_inc(&vcc->stats->rx_err);
1154                 return;
1155             }
1156             if (!atm_charge(vcc, skb->truesize)) {
1157                 recycle_rx_pool_skb(card, rpp);
1158                 dev_kfree_skb(skb);
1159                 return;
1160             }
1161             skb_queue_walk(&rpp->queue, sb)
1162                 skb_put_data(skb, sb->data, sb->len);
1163
1164             recycle_rx_pool_skb(card, rpp);
1165
1166             skb_trim(skb, len);
1167             ATM_SKB(skb)->vcc = vcc;
1168             __net_timestamp(skb);
1169
1170             vcc->push(vcc, skb);
1171             atomic_inc(&vcc->stats->rx);
1172
1173             return;
1174         }
1175
1176         flush_rx_pool(card, rpp);
1177
1178         if (!atm_charge(vcc, skb->truesize)) {
1179             recycle_rx_skb(card, skb);
1180             return;
1181         }
1182
1183         dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1184                  skb_end_pointer(skb) - skb->data,
1185                  DMA_FROM_DEVICE);
1186         sb_pool_remove(card, skb);
1187
1188         skb_trim(skb, len);
1189         ATM_SKB(skb)->vcc = vcc;
1190         __net_timestamp(skb);
1191
1192         vcc->push(vcc, skb);
1193         atomic_inc(&vcc->stats->rx);
1194
1195         if (skb->truesize > SAR_FB_SIZE_3)
1196             add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1197         else if (skb->truesize > SAR_FB_SIZE_2)
1198             add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1199         else if (skb->truesize > SAR_FB_SIZE_1)
1200             add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1201         else
1202             add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1203         return;
1204     }
1205 }
1206
1207 static void
1208 idt77252_rx(struct idt77252_dev *card)
1209 {
1210     struct rsq_entry *rsqe;
1211
1212     if (card->rsq.next == card->rsq.last)
1213         rsqe = card->rsq.base;
1214     else
1215         rsqe = card->rsq.next + 1;
1216
1217     if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1218         RXPRINTK("%s: no entry in RSQ.\n", card->name);
1219         return;
1220     }
1221
1222     do {
1223         dequeue_rx(card, rsqe);
1224         rsqe->word_4 = 0;
1225         card->rsq.next = rsqe;
1226         if (card->rsq.next == card->rsq.last)
1227             rsqe = card->rsq.base;
1228         else
1229             rsqe = card->rsq.next + 1;
1230     } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1231
1232     writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1233            SAR_REG_RSQH);
1234 }
1235
1236 static void
1237 idt77252_rx_raw(struct idt77252_dev *card)
1238 {
1239     struct sk_buff  *queue;
1240     u32     head, tail;
1241     struct atm_vcc  *vcc;
1242     struct vc_map   *vc;
1243     struct sk_buff  *sb;
1244
1245     if (card->raw_cell_head == NULL) {
1246         u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1247         card->raw_cell_head = sb_pool_skb(card, handle);
1248     }
1249
1250     queue = card->raw_cell_head;
1251     if (!queue)
1252         return;
1253
1254     head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1255     tail = readl(SAR_REG_RAWCT);
1256
1257     dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(queue),
1258                 skb_end_offset(queue) - 16,
1259                 DMA_FROM_DEVICE);
1260
1261     while (head != tail) {
1262         unsigned int vpi, vci;
1263         u32 header;
1264
1265         header = le32_to_cpu(*(u32 *) &queue->data[0]);
1266
1267         vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1268         vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1269
1270 #ifdef CONFIG_ATM_IDT77252_DEBUG
1271         if (debug & DBG_RAW_CELL) {
1272             int i;
1273
1274             printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1275                    card->name, (header >> 28) & 0x000f,
1276                    (header >> 20) & 0x00ff,
1277                    (header >>  4) & 0xffff,
1278                    (header >>  1) & 0x0007,
1279                    (header >>  0) & 0x0001);
1280             for (i = 16; i < 64; i++)
1281                 printk(" %02x", queue->data[i]);
1282             printk("\n");
1283         }
1284 #endif
1285
1286         if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1287             RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1288                 card->name, vpi, vci);
1289             goto drop;
1290         }
1291
1292         vc = card->vcs[VPCI2VC(card, vpi, vci)];
1293         if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1294             RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1295                 card->name, vpi, vci);
1296             goto drop;
1297         }
1298
1299         vcc = vc->rx_vcc;
1300
1301         if (vcc->qos.aal != ATM_AAL0) {
1302             RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1303                 card->name, vpi, vci);
1304             atomic_inc(&vcc->stats->rx_drop);
1305             goto drop;
1306         }
1307
1308         if ((sb = dev_alloc_skb(64)) == NULL) {
1309             printk("%s: Can't allocate buffers for AAL0.\n",
1310                    card->name);
1311             atomic_inc(&vcc->stats->rx_err);
1312             goto drop;
1313         }
1314
1315         if (!atm_charge(vcc, sb->truesize)) {
1316             RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1317                  card->name);
1318             dev_kfree_skb(sb);
1319             goto drop;
1320         }
1321
1322         *((u32 *) sb->data) = header;
1323         skb_put(sb, sizeof(u32));
1324         skb_put_data(sb, &(queue->data[16]), ATM_CELL_PAYLOAD);
1325
1326         ATM_SKB(sb)->vcc = vcc;
1327         __net_timestamp(sb);
1328         vcc->push(vcc, sb);
1329         atomic_inc(&vcc->stats->rx);
1330
1331 drop:
1332         skb_pull(queue, 64);
1333
1334         head = IDT77252_PRV_PADDR(queue)
1335                     + (queue->data - queue->head - 16);
1336
1337         if (queue->len < 128) {
1338             struct sk_buff *next;
1339             u32 handle;
1340
1341             head = le32_to_cpu(*(u32 *) &queue->data[0]);
1342             handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1343
1344             next = sb_pool_skb(card, handle);
1345             recycle_rx_skb(card, queue);
1346
1347             if (next) {
1348                 card->raw_cell_head = next;
1349                 queue = card->raw_cell_head;
1350                 dma_sync_single_for_cpu(&card->pcidev->dev,
1351                             IDT77252_PRV_PADDR(queue),
1352                             (skb_end_pointer(queue) -
1353                              queue->data),
1354                             DMA_FROM_DEVICE);
1355             } else {
1356                 card->raw_cell_head = NULL;
1357                 printk("%s: raw cell queue overrun\n",
1358                        card->name);
1359                 break;
1360             }
1361         }
1362     }
1363 }
1364
1365
1366 /*****************************************************************************/
1367 /*                                                                           */
1368 /* TSQ Handling                                                              */
1369 /*                                                                           */
1370 /*****************************************************************************/
1371
1372 static int
1373 init_tsq(struct idt77252_dev *card)
1374 {
1375     struct tsq_entry *tsqe;
1376
1377     card->tsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE,
1378                         &card->tsq.paddr, GFP_KERNEL);
1379     if (card->tsq.base == NULL) {
1380         printk("%s: can't allocate TSQ.\n", card->name);
1381         return -1;
1382     }
1383
1384     card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1385     card->tsq.next = card->tsq.last;
1386     for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1387         tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1388
1389     writel(card->tsq.paddr, SAR_REG_TSQB);
1390     writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1391            SAR_REG_TSQH);
1392
1393     return 0;
1394 }
1395
1396 static void
1397 deinit_tsq(struct idt77252_dev *card)
1398 {
1399     dma_free_coherent(&card->pcidev->dev, TSQSIZE,
1400               card->tsq.base, card->tsq.paddr);
1401 }
1402
1403 static void
1404 idt77252_tx(struct idt77252_dev *card)
1405 {
1406     struct tsq_entry *tsqe;
1407     unsigned int vpi, vci;
1408     struct vc_map *vc;
1409     u32 conn, stat;
1410
1411     if (card->tsq.next == card->tsq.last)
1412         tsqe = card->tsq.base;
1413     else
1414         tsqe = card->tsq.next + 1;
1415
1416     TXPRINTK("idt77252_tx: tsq  %p: base %p, next %p, last %p\n", tsqe,
1417          card->tsq.base, card->tsq.next, card->tsq.last);
1418     TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1419          readl(SAR_REG_TSQB),
1420          readl(SAR_REG_TSQT),
1421          readl(SAR_REG_TSQH));
1422
1423     stat = le32_to_cpu(tsqe->word_2);
1424
1425     if (stat & SAR_TSQE_INVALID)
1426         return;
1427
1428     do {
1429         TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1430              le32_to_cpu(tsqe->word_1),
1431              le32_to_cpu(tsqe->word_2));
1432
1433         switch (stat & SAR_TSQE_TYPE) {
1434         case SAR_TSQE_TYPE_TIMER:
1435             TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1436             break;
1437
1438         case SAR_TSQE_TYPE_IDLE:
1439
1440             conn = le32_to_cpu(tsqe->word_1);
1441
1442             if (SAR_TSQE_TAG(stat) == 0x10) {
1443 #ifdef  NOTDEF
1444                 printk("%s: Connection %d halted.\n",
1445                        card->name,
1446                        le32_to_cpu(tsqe->word_1) & 0x1fff);
1447 #endif
1448                 break;
1449             }
1450
1451             vc = card->vcs[conn & 0x1fff];
1452             if (!vc) {
1453                 printk("%s: could not find VC from conn %d\n",
1454                        card->name, conn & 0x1fff);
1455                 break;
1456             }
1457
1458             printk("%s: Connection %d IDLE.\n",
1459                    card->name, vc->index);
1460
1461             set_bit(VCF_IDLE, &vc->flags);
1462             break;
1463
1464         case SAR_TSQE_TYPE_TSR:
1465
1466             conn = le32_to_cpu(tsqe->word_1);
1467
1468             vc = card->vcs[conn & 0x1fff];
1469             if (!vc) {
1470                 printk("%s: no VC at index %d\n",
1471                        card->name,
1472                        le32_to_cpu(tsqe->word_1) & 0x1fff);
1473                 break;
1474             }
1475
1476             drain_scq(card, vc);
1477             break;
1478
1479         case SAR_TSQE_TYPE_TBD_COMP:
1480
1481             conn = le32_to_cpu(tsqe->word_1);
1482
1483             vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1484             vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1485
1486             if (vpi >= (1 << card->vpibits) ||
1487                 vci >= (1 << card->vcibits)) {
1488                 printk("%s: TBD complete: "
1489                        "out of range VPI.VCI %u.%u\n",
1490                        card->name, vpi, vci);
1491                 break;
1492             }
1493
1494             vc = card->vcs[VPCI2VC(card, vpi, vci)];
1495             if (!vc) {
1496                 printk("%s: TBD complete: "
1497                        "no VC at VPI.VCI %u.%u\n",
1498                        card->name, vpi, vci);
1499                 break;
1500             }
1501
1502             drain_scq(card, vc);
1503             break;
1504         }
1505
1506         tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1507
1508         card->tsq.next = tsqe;
1509         if (card->tsq.next == card->tsq.last)
1510             tsqe = card->tsq.base;
1511         else
1512             tsqe = card->tsq.next + 1;
1513
1514         TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1515              card->tsq.base, card->tsq.next, card->tsq.last);
1516
1517         stat = le32_to_cpu(tsqe->word_2);
1518
1519     } while (!(stat & SAR_TSQE_INVALID));
1520
1521     writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1522            SAR_REG_TSQH);
1523
1524     XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1525         card->index, readl(SAR_REG_TSQH),
1526         readl(SAR_REG_TSQT), card->tsq.next);
1527 }
1528
1529
1530 static void
1531 tst_timer(struct timer_list *t)
1532 {
1533     struct idt77252_dev *card = from_timer(card, t, tst_timer);
1534     unsigned long base, idle, jump;
1535     unsigned long flags;
1536     u32 pc;
1537     int e;
1538
1539     spin_lock_irqsave(&card->tst_lock, flags);
1540
1541     base = card->tst[card->tst_index];
1542     idle = card->tst[card->tst_index ^ 1];
1543
1544     if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1545         jump = base + card->tst_size - 2;
1546
1547         pc = readl(SAR_REG_NOW) >> 2;
1548         if ((pc ^ idle) & ~(card->tst_size - 1)) {
1549             mod_timer(&card->tst_timer, jiffies + 1);
1550             goto out;
1551         }
1552
1553         clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1554
1555         card->tst_index ^= 1;
1556         write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1557
1558         base = card->tst[card->tst_index];
1559         idle = card->tst[card->tst_index ^ 1];
1560
1561         for (e = 0; e < card->tst_size - 2; e++) {
1562             if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1563                 write_sram(card, idle + e,
1564                        card->soft_tst[e].tste & TSTE_MASK);
1565                 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1566             }
1567         }
1568     }
1569
1570     if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1571
1572         for (e = 0; e < card->tst_size - 2; e++) {
1573             if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1574                 write_sram(card, idle + e,
1575                        card->soft_tst[e].tste & TSTE_MASK);
1576                 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1577                 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1578             }
1579         }
1580
1581         jump = base + card->tst_size - 2;
1582
1583         write_sram(card, jump, TSTE_OPC_NULL);
1584         set_bit(TST_SWITCH_WAIT, &card->tst_state);
1585
1586         mod_timer(&card->tst_timer, jiffies + 1);
1587     }
1588
1589 out:
1590     spin_unlock_irqrestore(&card->tst_lock, flags);
1591 }
1592
1593 static int
1594 __fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1595        int n, unsigned int opc)
1596 {
1597     unsigned long cl, avail;
1598     unsigned long idle;
1599     int e, r;
1600     u32 data;
1601
1602     avail = card->tst_size - 2;
1603     for (e = 0; e < avail; e++) {
1604         if (card->soft_tst[e].vc == NULL)
1605             break;
1606     }
1607     if (e >= avail) {
1608         printk("%s: No free TST entries found\n", card->name);
1609         return -1;
1610     }
1611
1612     NPRINTK("%s: conn %d: first TST entry at %d.\n",
1613         card->name, vc ? vc->index : -1, e);
1614
1615     r = n;
1616     cl = avail;
1617     data = opc & TSTE_OPC_MASK;
1618     if (vc && (opc != TSTE_OPC_NULL))
1619         data = opc | vc->index;
1620
1621     idle = card->tst[card->tst_index ^ 1];
1622
1623     /*
1624      * Fill Soft TST.
1625      */
1626     while (r > 0) {
1627         if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1628             if (vc)
1629                 card->soft_tst[e].vc = vc;
1630             else
1631                 card->soft_tst[e].vc = (void *)-1;
1632
1633             card->soft_tst[e].tste = data;
1634             if (timer_pending(&card->tst_timer))
1635                 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1636             else {
1637                 write_sram(card, idle + e, data);
1638                 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1639             }
1640
1641             cl -= card->tst_size;
1642             r--;
1643         }
1644
1645         if (++e == avail)
1646             e = 0;
1647         cl += n;
1648     }
1649
1650     return 0;
1651 }
1652
1653 static int
1654 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1655 {
1656     unsigned long flags;
1657     int res;
1658
1659     spin_lock_irqsave(&card->tst_lock, flags);
1660
1661     res = __fill_tst(card, vc, n, opc);
1662
1663     set_bit(TST_SWITCH_PENDING, &card->tst_state);
1664     if (!timer_pending(&card->tst_timer))
1665         mod_timer(&card->tst_timer, jiffies + 1);
1666
1667     spin_unlock_irqrestore(&card->tst_lock, flags);
1668     return res;
1669 }
1670
1671 static int
1672 __clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1673 {
1674     unsigned long idle;
1675     int e;
1676
1677     idle = card->tst[card->tst_index ^ 1];
1678
1679     for (e = 0; e < card->tst_size - 2; e++) {
1680         if (card->soft_tst[e].vc == vc) {
1681             card->soft_tst[e].vc = NULL;
1682
1683             card->soft_tst[e].tste = TSTE_OPC_VAR;
1684             if (timer_pending(&card->tst_timer))
1685                 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1686             else {
1687                 write_sram(card, idle + e, TSTE_OPC_VAR);
1688                 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1689             }
1690         }
1691     }
1692
1693     return 0;
1694 }
1695
1696 static int
1697 clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1698 {
1699     unsigned long flags;
1700     int res;
1701
1702     spin_lock_irqsave(&card->tst_lock, flags);
1703
1704     res = __clear_tst(card, vc);
1705
1706     set_bit(TST_SWITCH_PENDING, &card->tst_state);
1707     if (!timer_pending(&card->tst_timer))
1708         mod_timer(&card->tst_timer, jiffies + 1);
1709
1710     spin_unlock_irqrestore(&card->tst_lock, flags);
1711     return res;
1712 }
1713
1714 static int
1715 change_tst(struct idt77252_dev *card, struct vc_map *vc,
1716        int n, unsigned int opc)
1717 {
1718     unsigned long flags;
1719     int res;
1720
1721     spin_lock_irqsave(&card->tst_lock, flags);
1722
1723     __clear_tst(card, vc);
1724     res = __fill_tst(card, vc, n, opc);
1725
1726     set_bit(TST_SWITCH_PENDING, &card->tst_state);
1727     if (!timer_pending(&card->tst_timer))
1728         mod_timer(&card->tst_timer, jiffies + 1);
1729
1730     spin_unlock_irqrestore(&card->tst_lock, flags);
1731     return res;
1732 }
1733
1734
1735 static int
1736 set_tct(struct idt77252_dev *card, struct vc_map *vc)
1737 {
1738     unsigned long tct;
1739
1740     tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1741
1742     switch (vc->class) {
1743     case SCHED_CBR:
1744         OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1745                 card->name, tct, vc->scq->scd);
1746
1747         write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1748         write_sram(card, tct + 1, 0);
1749         write_sram(card, tct + 2, 0);
1750         write_sram(card, tct + 3, 0);
1751         write_sram(card, tct + 4, 0);
1752         write_sram(card, tct + 5, 0);
1753         write_sram(card, tct + 6, 0);
1754         write_sram(card, tct + 7, 0);
1755         break;
1756
1757     case SCHED_UBR:
1758         OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1759                 card->name, tct, vc->scq->scd);
1760
1761         write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1762         write_sram(card, tct + 1, 0);
1763         write_sram(card, tct + 2, TCT_TSIF);
1764         write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1765         write_sram(card, tct + 4, 0);
1766         write_sram(card, tct + 5, vc->init_er);
1767         write_sram(card, tct + 6, 0);
1768         write_sram(card, tct + 7, TCT_FLAG_UBR);
1769         break;
1770
1771     case SCHED_VBR:
1772     case SCHED_ABR:
1773     default:
1774         return -ENOSYS;
1775     }
1776
1777     return 0;
1778 }
1779
1780 /*****************************************************************************/
1781 /*                                                                           */
1782 /* FBQ Handling                                                              */
1783 /*                                                                           */
1784 /*****************************************************************************/
1785
1786 static __inline__ int
1787 idt77252_fbq_full(struct idt77252_dev *card, int queue)
1788 {
1789     return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1790 }
1791
1792 static int
1793 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1794 {
1795     unsigned long flags;
1796     u32 handle;
1797     u32 addr;
1798
1799     skb->data = skb->head;
1800     skb_reset_tail_pointer(skb);
1801     skb->len = 0;
1802
1803     skb_reserve(skb, 16);
1804
1805     switch (queue) {
1806     case 0:
1807         skb_put(skb, SAR_FB_SIZE_0);
1808         break;
1809     case 1:
1810         skb_put(skb, SAR_FB_SIZE_1);
1811         break;
1812     case 2:
1813         skb_put(skb, SAR_FB_SIZE_2);
1814         break;
1815     case 3:
1816         skb_put(skb, SAR_FB_SIZE_3);
1817         break;
1818     default:
1819         return -1;
1820     }
1821
1822     if (idt77252_fbq_full(card, queue))
1823         return -1;
1824
1825     memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1826
1827     handle = IDT77252_PRV_POOL(skb);
1828     addr = IDT77252_PRV_PADDR(skb);
1829
1830     spin_lock_irqsave(&card->cmd_lock, flags);
1831     writel(handle, card->fbq[queue]);
1832     writel(addr, card->fbq[queue]);
1833     spin_unlock_irqrestore(&card->cmd_lock, flags);
1834
1835     return 0;
1836 }
1837
1838 static void
1839 add_rx_skb(struct idt77252_dev *card, int queue,
1840        unsigned int size, unsigned int count)
1841 {
1842     struct sk_buff *skb;
1843     dma_addr_t paddr;
1844     u32 handle;
1845
1846     while (count--) {
1847         skb = dev_alloc_skb(size);
1848         if (!skb)
1849             return;
1850
1851         if (sb_pool_add(card, skb, queue)) {
1852             printk("%s: SB POOL full\n", __func__);
1853             goto outfree;
1854         }
1855
1856         paddr = dma_map_single(&card->pcidev->dev, skb->data,
1857                        skb_end_pointer(skb) - skb->data,
1858                        DMA_FROM_DEVICE);
1859         IDT77252_PRV_PADDR(skb) = paddr;
1860
1861         if (push_rx_skb(card, skb, queue)) {
1862             printk("%s: FB QUEUE full\n", __func__);
1863             goto outunmap;
1864         }
1865     }
1866
1867     return;
1868
1869 outunmap:
1870     dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1871              skb_end_pointer(skb) - skb->data, DMA_FROM_DEVICE);
1872
1873     handle = IDT77252_PRV_POOL(skb);
1874     card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1875
1876 outfree:
1877     dev_kfree_skb(skb);
1878 }
1879
1880
1881 static void
1882 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1883 {
1884     u32 handle = IDT77252_PRV_POOL(skb);
1885     int err;
1886
1887     dma_sync_single_for_device(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1888                    skb_end_pointer(skb) - skb->data,
1889                    DMA_FROM_DEVICE);
1890
1891     err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1892     if (err) {
1893         dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1894                  skb_end_pointer(skb) - skb->data,
1895                  DMA_FROM_DEVICE);
1896         sb_pool_remove(card, skb);
1897         dev_kfree_skb(skb);
1898     }
1899 }
1900
1901 static void
1902 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1903 {
1904     skb_queue_head_init(&rpp->queue);
1905     rpp->len = 0;
1906 }
1907
1908 static void
1909 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1910 {
1911     struct sk_buff *skb, *tmp;
1912
1913     skb_queue_walk_safe(&rpp->queue, skb, tmp)
1914         recycle_rx_skb(card, skb);
1915
1916     flush_rx_pool(card, rpp);
1917 }
1918
1919 /*****************************************************************************/
1920 /*                                                                           */
1921 /* ATM Interface                                                             */
1922 /*                                                                           */
1923 /*****************************************************************************/
1924
1925 static void
1926 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1927 {
1928     write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1929 }
1930
1931 static unsigned char
1932 idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1933 {
1934     return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1935 }
1936
1937 static inline int
1938 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1939 {
1940     struct atm_dev *dev = vcc->dev;
1941     struct idt77252_dev *card = dev->dev_data;
1942     struct vc_map *vc = vcc->dev_data;
1943     int err;
1944
1945     if (vc == NULL) {
1946         printk("%s: NULL connection in send().\n", card->name);
1947         atomic_inc(&vcc->stats->tx_err);
1948         dev_kfree_skb(skb);
1949         return -EINVAL;
1950     }
1951     if (!test_bit(VCF_TX, &vc->flags)) {
1952         printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1953         atomic_inc(&vcc->stats->tx_err);
1954         dev_kfree_skb(skb);
1955         return -EINVAL;
1956     }
1957
1958     switch (vcc->qos.aal) {
1959     case ATM_AAL0:
1960     case ATM_AAL1:
1961     case ATM_AAL5:
1962         break;
1963     default:
1964         printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1965         atomic_inc(&vcc->stats->tx_err);
1966         dev_kfree_skb(skb);
1967         return -EINVAL;
1968     }
1969
1970     if (skb_shinfo(skb)->nr_frags != 0) {
1971         printk("%s: No scatter-gather yet.\n", card->name);
1972         atomic_inc(&vcc->stats->tx_err);
1973         dev_kfree_skb(skb);
1974         return -EINVAL;
1975     }
1976     ATM_SKB(skb)->vcc = vcc;
1977
1978     err = queue_skb(card, vc, skb, oam);
1979     if (err) {
1980         atomic_inc(&vcc->stats->tx_err);
1981         dev_kfree_skb(skb);
1982         return err;
1983     }
1984
1985     return 0;
1986 }
1987
1988 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
1989 {
1990     return idt77252_send_skb(vcc, skb, 0);
1991 }
1992
1993 static int
1994 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
1995 {
1996     struct atm_dev *dev = vcc->dev;
1997     struct idt77252_dev *card = dev->dev_data;
1998     struct sk_buff *skb;
1999
2000     skb = dev_alloc_skb(64);
2001     if (!skb) {
2002         printk("%s: Out of memory in send_oam().\n", card->name);
2003         atomic_inc(&vcc->stats->tx_err);
2004         return -ENOMEM;
2005     }
2006     refcount_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
2007
2008     skb_put_data(skb, cell, 52);
2009
2010     return idt77252_send_skb(vcc, skb, 1);
2011 }
2012
2013 static __inline__ unsigned int
2014 idt77252_fls(unsigned int x)
2015 {
2016     int r = 1;
2017
2018     if (x == 0)
2019         return 0;
2020     if (x & 0xffff0000) {
2021         x >>= 16;
2022         r += 16;
2023     }
2024     if (x & 0xff00) {
2025         x >>= 8;
2026         r += 8;
2027     }
2028     if (x & 0xf0) {
2029         x >>= 4;
2030         r += 4;
2031     }
2032     if (x & 0xc) {
2033         x >>= 2;
2034         r += 2;
2035     }
2036     if (x & 0x2)
2037         r += 1;
2038     return r;
2039 }
2040
2041 static u16
2042 idt77252_int_to_atmfp(unsigned int rate)
2043 {
2044     u16 m, e;
2045
2046     if (rate == 0)
2047         return 0;
2048     e = idt77252_fls(rate) - 1;
2049     if (e < 9)
2050         m = (rate - (1 << e)) << (9 - e);
2051     else if (e == 9)
2052         m = (rate - (1 << e));
2053     else /* e > 9 */
2054         m = (rate - (1 << e)) >> (e - 9);
2055     return 0x4000 | (e << 9) | m;
2056 }
2057
2058 static u8
2059 idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2060 {
2061     u16 afp;
2062
2063     afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2064     if (pcr < 0)
2065         return rate_to_log[(afp >> 5) & 0x1ff];
2066     return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2067 }
2068
2069 static void
2070 idt77252_est_timer(struct timer_list *t)
2071 {
2072     struct rate_estimator *est = from_timer(est, t, timer);
2073     struct vc_map *vc = est->vc;
2074     struct idt77252_dev *card = vc->card;
2075     unsigned long flags;
2076     u32 rate, cps;
2077     u64 ncells;
2078     u8 lacr;
2079
2080     spin_lock_irqsave(&vc->lock, flags);
2081     if (!vc->estimator)
2082         goto out;
2083     ncells = est->cells;
2084
2085     rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2086     est->last_cells = ncells;
2087     est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2088     est->cps = (est->avcps + 0x1f) >> 5;
2089
2090     cps = est->cps;
2091     if (cps < (est->maxcps >> 4))
2092         cps = est->maxcps >> 4;
2093
2094     lacr = idt77252_rate_logindex(card, cps);
2095     if (lacr > vc->max_er)
2096         lacr = vc->max_er;
2097
2098     if (lacr != vc->lacr) {
2099         vc->lacr = lacr;
2100         writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2101     }
2102
2103     est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2104     add_timer(&est->timer);
2105
2106 out:
2107     spin_unlock_irqrestore(&vc->lock, flags);
2108 }
2109
2110 static struct rate_estimator *
2111 idt77252_init_est(struct vc_map *vc, int pcr)
2112 {
2113     struct rate_estimator *est;
2114
2115     est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2116     if (!est)
2117         return NULL;
2118     est->maxcps = pcr < 0 ? -pcr : pcr;
2119     est->cps = est->maxcps;
2120     est->avcps = est->cps << 5;
2121     est->vc = vc;
2122
2123     est->interval = 2;      /* XXX: make this configurable */
2124     est->ewma_log = 2;      /* XXX: make this configurable */
2125     timer_setup(&est->timer, idt77252_est_timer, 0);
2126     mod_timer(&est->timer, jiffies + ((HZ / 4) << est->interval));
2127
2128     return est;
2129 }
2130
2131 static int
2132 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2133           struct atm_vcc *vcc, struct atm_qos *qos)
2134 {
2135     int tst_free, tst_used, tst_entries;
2136     unsigned long tmpl, modl;
2137     int tcr, tcra;
2138
2139     if ((qos->txtp.max_pcr == 0) &&
2140         (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
2141         printk("%s: trying to open a CBR VC with cell rate = 0\n",
2142                card->name);
2143         return -EINVAL;
2144     }
2145
2146     tst_used = 0;
2147     tst_free = card->tst_free;
2148     if (test_bit(VCF_TX, &vc->flags))
2149         tst_used = vc->ntste;
2150     tst_free += tst_used;
2151
2152     tcr = atm_pcr_goal(&qos->txtp);
2153     tcra = tcr >= 0 ? tcr : -tcr;
2154
2155     TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
2156
2157     tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
2158     modl = tmpl % (unsigned long)card->utopia_pcr;
2159
2160     tst_entries = (int) (tmpl / card->utopia_pcr);
2161     if (tcr > 0) {
2162         if (modl > 0)
2163             tst_entries++;
2164     } else if (tcr == 0) {
2165         tst_entries = tst_free - SAR_TST_RESERVED;
2166         if (tst_entries <= 0) {
2167             printk("%s: no CBR bandwidth free.\n", card->name);
2168             return -ENOSR;
2169         }
2170     }
2171
2172     if (tst_entries == 0) {
2173         printk("%s: selected CBR bandwidth < granularity.\n",
2174                card->name);
2175         return -EINVAL;
2176     }
2177
2178     if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
2179         printk("%s: not enough CBR bandwidth free.\n", card->name);
2180         return -ENOSR;
2181     }
2182
2183     vc->ntste = tst_entries;
2184
2185     card->tst_free = tst_free - tst_entries;
2186     if (test_bit(VCF_TX, &vc->flags)) {
2187         if (tst_used == tst_entries)
2188             return 0;
2189
2190         OPRINTK("%s: modify %d -> %d entries in TST.\n",
2191             card->name, tst_used, tst_entries);
2192         change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2193         return 0;
2194     }
2195
2196     OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
2197     fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2198     return 0;
2199 }
2200
2201 static int
2202 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
2203           struct atm_vcc *vcc, struct atm_qos *qos)
2204 {
2205     struct rate_estimator *est = NULL;
2206     unsigned long flags;
2207     int tcr;
2208
2209     spin_lock_irqsave(&vc->lock, flags);
2210     if (vc->estimator) {
2211         est = vc->estimator;
2212         vc->estimator = NULL;
2213     }
2214     spin_unlock_irqrestore(&vc->lock, flags);
2215     if (est) {
2216         del_timer_sync(&est->timer);
2217         kfree(est);
2218     }
2219
2220     tcr = atm_pcr_goal(&qos->txtp);
2221     if (tcr == 0)
2222         tcr = card->link_pcr;
2223
2224     vc->estimator = idt77252_init_est(vc, tcr);
2225
2226     vc->class = SCHED_UBR;
2227     vc->init_er = idt77252_rate_logindex(card, tcr);
2228     vc->lacr = vc->init_er;
2229     if (tcr < 0)
2230         vc->max_er = vc->init_er;
2231     else
2232         vc->max_er = 0xff;
2233
2234     return 0;
2235 }
2236
2237 static int
2238 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
2239          struct atm_vcc *vcc, struct atm_qos *qos)
2240 {
2241     int error;
2242
2243     if (test_bit(VCF_TX, &vc->flags))
2244         return -EBUSY;
2245
2246     switch (qos->txtp.traffic_class) {
2247         case ATM_CBR:
2248             vc->class = SCHED_CBR;
2249             break;
2250
2251         case ATM_UBR:
2252             vc->class = SCHED_UBR;
2253             break;
2254
2255         case ATM_VBR:
2256         case ATM_ABR:
2257         default:
2258             return -EPROTONOSUPPORT;
2259     }
2260
2261     vc->scq = alloc_scq(card, vc->class);
2262     if (!vc->scq) {
2263         printk("%s: can't get SCQ.\n", card->name);
2264         return -ENOMEM;
2265     }
2266
2267     vc->scq->scd = get_free_scd(card, vc);
2268     if (vc->scq->scd == 0) {
2269         printk("%s: no SCD available.\n", card->name);
2270         free_scq(card, vc->scq);
2271         return -ENOMEM;
2272     }
2273
2274     fill_scd(card, vc->scq, vc->class);
2275
2276     if (set_tct(card, vc)) {
2277         printk("%s: class %d not supported.\n",
2278                card->name, qos->txtp.traffic_class);
2279
2280         card->scd2vc[vc->scd_index] = NULL;
2281         free_scq(card, vc->scq);
2282         return -EPROTONOSUPPORT;
2283     }
2284
2285     switch (vc->class) {
2286         case SCHED_CBR:
2287             error = idt77252_init_cbr(card, vc, vcc, qos);
2288             if (error) {
2289                 card->scd2vc[vc->scd_index] = NULL;
2290                 free_scq(card, vc->scq);
2291                 return error;
2292             }
2293
2294             clear_bit(VCF_IDLE, &vc->flags);
2295             writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
2296             break;
2297
2298         case SCHED_UBR:
2299             error = idt77252_init_ubr(card, vc, vcc, qos);
2300             if (error) {
2301                 card->scd2vc[vc->scd_index] = NULL;
2302                 free_scq(card, vc->scq);
2303                 return error;
2304             }
2305
2306             set_bit(VCF_IDLE, &vc->flags);
2307             break;
2308     }
2309
2310     vc->tx_vcc = vcc;
2311     set_bit(VCF_TX, &vc->flags);
2312     return 0;
2313 }
2314
2315 static int
2316 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
2317          struct atm_vcc *vcc, struct atm_qos *qos)
2318 {
2319     unsigned long flags;
2320     unsigned long addr;
2321     u32 rcte = 0;
2322
2323     if (test_bit(VCF_RX, &vc->flags))
2324         return -EBUSY;
2325
2326     vc->rx_vcc = vcc;
2327     set_bit(VCF_RX, &vc->flags);
2328
2329     if ((vcc->vci == 3) || (vcc->vci == 4))
2330         return 0;
2331
2332     flush_rx_pool(card, &vc->rcv.rx_pool);
2333
2334     rcte |= SAR_RCTE_CONNECTOPEN;
2335     rcte |= SAR_RCTE_RAWCELLINTEN;
2336
2337     switch (qos->aal) {
2338         case ATM_AAL0:
2339             rcte |= SAR_RCTE_RCQ;
2340             break;
2341         case ATM_AAL1:
2342             rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
2343             break;
2344         case ATM_AAL34:
2345             rcte |= SAR_RCTE_AAL34;
2346             break;
2347         case ATM_AAL5:
2348             rcte |= SAR_RCTE_AAL5;
2349             break;
2350         default:
2351             rcte |= SAR_RCTE_RCQ;
2352             break;
2353     }
2354
2355     if (qos->aal != ATM_AAL5)
2356         rcte |= SAR_RCTE_FBP_1;
2357     else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
2358         rcte |= SAR_RCTE_FBP_3;
2359     else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
2360         rcte |= SAR_RCTE_FBP_2;
2361     else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
2362         rcte |= SAR_RCTE_FBP_1;
2363     else
2364         rcte |= SAR_RCTE_FBP_01;
2365
2366     addr = card->rct_base + (vc->index << 2);
2367
2368     OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
2369     write_sram(card, addr, rcte);
2370
2371     spin_lock_irqsave(&card->cmd_lock, flags);
2372     writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
2373     waitfor_idle(card);
2374     spin_unlock_irqrestore(&card->cmd_lock, flags);
2375
2376     return 0;
2377 }
2378
2379 static int
2380 idt77252_open(struct atm_vcc *vcc)
2381 {
2382     struct atm_dev *dev = vcc->dev;
2383     struct idt77252_dev *card = dev->dev_data;
2384     struct vc_map *vc;
2385     unsigned int index;
2386     unsigned int inuse;
2387     int error;
2388     int vci = vcc->vci;
2389     short vpi = vcc->vpi;
2390
2391     if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
2392         return 0;
2393
2394     if (vpi >= (1 << card->vpibits)) {
2395         printk("%s: unsupported VPI: %d\n", card->name, vpi);
2396         return -EINVAL;
2397     }
2398
2399     if (vci >= (1 << card->vcibits)) {
2400         printk("%s: unsupported VCI: %d\n", card->name, vci);
2401         return -EINVAL;
2402     }
2403
2404     set_bit(ATM_VF_ADDR, &vcc->flags);
2405
2406     mutex_lock(&card->mutex);
2407
2408     OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
2409
2410     switch (vcc->qos.aal) {
2411     case ATM_AAL0:
2412     case ATM_AAL1:
2413     case ATM_AAL5:
2414         break;
2415     default:
2416         printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2417         mutex_unlock(&card->mutex);
2418         return -EPROTONOSUPPORT;
2419     }
2420
2421     index = VPCI2VC(card, vpi, vci);
2422     if (!card->vcs[index]) {
2423         card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2424         if (!card->vcs[index]) {
2425             printk("%s: can't alloc vc in open()\n", card->name);
2426             mutex_unlock(&card->mutex);
2427             return -ENOMEM;
2428         }
2429         card->vcs[index]->card = card;
2430         card->vcs[index]->index = index;
2431
2432         spin_lock_init(&card->vcs[index]->lock);
2433     }
2434     vc = card->vcs[index];
2435
2436     vcc->dev_data = vc;
2437
2438     IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2439             card->name, vc->index, vcc->vpi, vcc->vci,
2440             vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
2441             vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
2442             vcc->qos.rxtp.max_sdu);
2443
2444     inuse = 0;
2445     if (vcc->qos.txtp.traffic_class != ATM_NONE &&
2446         test_bit(VCF_TX, &vc->flags))
2447         inuse = 1;
2448     if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
2449         test_bit(VCF_RX, &vc->flags))
2450         inuse += 2;
2451
2452     if (inuse) {
2453         printk("%s: %s vci already in use.\n", card->name,
2454                inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
2455         mutex_unlock(&card->mutex);
2456         return -EADDRINUSE;
2457     }
2458
2459     if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2460         error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
2461         if (error) {
2462             mutex_unlock(&card->mutex);
2463             return error;
2464         }
2465     }
2466
2467     if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2468         error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
2469         if (error) {
2470             mutex_unlock(&card->mutex);
2471             return error;
2472         }
2473     }
2474
2475     set_bit(ATM_VF_READY, &vcc->flags);
2476
2477     mutex_unlock(&card->mutex);
2478     return 0;
2479 }
2480
2481 static void
2482 idt77252_close(struct atm_vcc *vcc)
2483 {
2484     struct atm_dev *dev = vcc->dev;
2485     struct idt77252_dev *card = dev->dev_data;
2486     struct vc_map *vc = vcc->dev_data;
2487     unsigned long flags;
2488     unsigned long addr;
2489     unsigned long timeout;
2490
2491     mutex_lock(&card->mutex);
2492
2493     IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2494         card->name, vc->index, vcc->vpi, vcc->vci);
2495
2496     clear_bit(ATM_VF_READY, &vcc->flags);
2497
2498     if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2499
2500         spin_lock_irqsave(&vc->lock, flags);
2501         clear_bit(VCF_RX, &vc->flags);
2502         vc->rx_vcc = NULL;
2503         spin_unlock_irqrestore(&vc->lock, flags);
2504
2505         if ((vcc->vci == 3) || (vcc->vci == 4))
2506             goto done;
2507
2508         addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2509
2510         spin_lock_irqsave(&card->cmd_lock, flags);
2511         writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
2512         waitfor_idle(card);
2513         spin_unlock_irqrestore(&card->cmd_lock, flags);
2514
2515         if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {
2516             DPRINTK("%s: closing a VC with pending rx buffers.\n",
2517                 card->name);
2518
2519             recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2520         }
2521     }
2522
2523 done:
2524     if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2525
2526         spin_lock_irqsave(&vc->lock, flags);
2527         clear_bit(VCF_TX, &vc->flags);
2528         clear_bit(VCF_IDLE, &vc->flags);
2529         clear_bit(VCF_RSV, &vc->flags);
2530         vc->tx_vcc = NULL;
2531
2532         if (vc->estimator) {
2533             del_timer(&vc->estimator->timer);
2534             kfree(vc->estimator);
2535             vc->estimator = NULL;
2536         }
2537         spin_unlock_irqrestore(&vc->lock, flags);
2538
2539         timeout = 5 * 1000;
2540         while (atomic_read(&vc->scq->used) > 0) {
2541             timeout = msleep_interruptible(timeout);
2542             if (!timeout) {
2543                 pr_warn("%s: SCQ drain timeout: %u used\n",
2544                     card->name, atomic_read(&vc->scq->used));
2545                 break;
2546             }
2547         }
2548
2549         writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
2550         clear_scd(card, vc->scq, vc->class);
2551
2552         if (vc->class == SCHED_CBR) {
2553             clear_tst(card, vc);
2554             card->tst_free += vc->ntste;
2555             vc->ntste = 0;
2556         }
2557
2558         card->scd2vc[vc->scd_index] = NULL;
2559         free_scq(card, vc->scq);
2560     }
2561
2562     mutex_unlock(&card->mutex);
2563 }
2564
2565 static int
2566 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2567 {
2568     struct atm_dev *dev = vcc->dev;
2569     struct idt77252_dev *card = dev->dev_data;
2570     struct vc_map *vc = vcc->dev_data;
2571     int error = 0;
2572
2573     mutex_lock(&card->mutex);
2574
2575     if (qos->txtp.traffic_class != ATM_NONE) {
2576             if (!test_bit(VCF_TX, &vc->flags)) {
2577             error = idt77252_init_tx(card, vc, vcc, qos);
2578             if (error)
2579                 goto out;
2580         } else {
2581             switch (qos->txtp.traffic_class) {
2582             case ATM_CBR:
2583                 error = idt77252_init_cbr(card, vc, vcc, qos);
2584                 if (error)
2585                     goto out;
2586                 break;
2587
2588             case ATM_UBR:
2589                 error = idt77252_init_ubr(card, vc, vcc, qos);
2590                 if (error)
2591                     goto out;
2592
2593                 if (!test_bit(VCF_IDLE, &vc->flags)) {
2594                     writel(TCMDQ_LACR | (vc->lacr << 16) |
2595                            vc->index, SAR_REG_TCMDQ);
2596                 }
2597                 break;
2598
2599             case ATM_VBR:
2600             case ATM_ABR:
2601                 error = -EOPNOTSUPP;
2602                 goto out;
2603             }
2604         }
2605     }
2606
2607     if ((qos->rxtp.traffic_class != ATM_NONE) &&
2608         !test_bit(VCF_RX, &vc->flags)) {
2609         error = idt77252_init_rx(card, vc, vcc, qos);
2610         if (error)
2611             goto out;
2612     }
2613
2614     memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
2615
2616     set_bit(ATM_VF_HASQOS, &vcc->flags);
2617
2618 out:
2619     mutex_unlock(&card->mutex);
2620     return error;
2621 }
2622
2623 static int
2624 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2625 {
2626     struct idt77252_dev *card = dev->dev_data;
2627     int i, left;
2628
2629     left = (int) *pos;
2630     if (!left--)
2631         return sprintf(page, "IDT77252 Interrupts:\n");
2632     if (!left--)
2633         return sprintf(page, "TSIF:  %lu\n", card->irqstat[15]);
2634     if (!left--)
2635         return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
2636     if (!left--)
2637         return sprintf(page, "TSQF:  %lu\n", card->irqstat[12]);
2638     if (!left--)
2639         return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
2640     if (!left--)
2641         return sprintf(page, "PHYI:  %lu\n", card->irqstat[10]);
2642     if (!left--)
2643         return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
2644     if (!left--)
2645         return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
2646     if (!left--)
2647         return sprintf(page, "RSQF:  %lu\n", card->irqstat[6]);
2648     if (!left--)
2649         return sprintf(page, "EPDU:  %lu\n", card->irqstat[5]);
2650     if (!left--)
2651         return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
2652     if (!left--)
2653         return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
2654     if (!left--)
2655         return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
2656     if (!left--)
2657         return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
2658     if (!left--)
2659         return sprintf(page, "IDT77252 Transmit Connection Table:\n");
2660
2661     for (i = 0; i < card->tct_size; i++) {
2662         unsigned long tct;
2663         struct atm_vcc *vcc;
2664         struct vc_map *vc;
2665         char *p;
2666
2667         vc = card->vcs[i];
2668         if (!vc)
2669             continue;
2670
2671         vcc = NULL;
2672         if (vc->tx_vcc)
2673             vcc = vc->tx_vcc;
2674         if (!vcc)
2675             continue;
2676         if (left--)
2677             continue;
2678
2679         p = page;
2680         p += sprintf(p, "  %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
2681         tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
2682
2683         for (i = 0; i < 8; i++)
2684             p += sprintf(p, " %08x", read_sram(card, tct + i));
2685         p += sprintf(p, "\n");
2686         return p - page;
2687     }
2688     return 0;
2689 }
2690
2691 /*****************************************************************************/
2692 /*                                                                           */
2693 /* Interrupt handler                                                         */
2694 /*                                                                           */
2695 /*****************************************************************************/
2696
2697 static void
2698 idt77252_collect_stat(struct idt77252_dev *card)
2699 {
2700     (void) readl(SAR_REG_CDC);
2701     (void) readl(SAR_REG_VPEC);
2702     (void) readl(SAR_REG_ICC);
2703
2704 }
2705
2706 static irqreturn_t
2707 idt77252_interrupt(int irq, void *dev_id)
2708 {
2709     struct idt77252_dev *card = dev_id;
2710     u32 stat;
2711
2712     stat = readl(SAR_REG_STAT) & 0xffff;
2713     if (!stat)  /* no interrupt for us */
2714         return IRQ_NONE;
2715
2716     if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
2717         printk("%s: Re-entering irq_handler()\n", card->name);
2718         goto out;
2719     }
2720
2721     writel(stat, SAR_REG_STAT); /* reset interrupt */
2722
2723     if (stat & SAR_STAT_TSIF) { /* entry written to TSQ  */
2724         INTPRINTK("%s: TSIF\n", card->name);
2725         card->irqstat[15]++;
2726         idt77252_tx(card);
2727     }
2728     if (stat & SAR_STAT_TXICP) {    /* Incomplete CS-PDU has  */
2729         INTPRINTK("%s: TXICP\n", card->name);
2730         card->irqstat[14]++;
2731 #ifdef CONFIG_ATM_IDT77252_DEBUG
2732         idt77252_tx_dump(card);
2733 #endif
2734     }
2735     if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full           */
2736         INTPRINTK("%s: TSQF\n", card->name);
2737         card->irqstat[12]++;
2738         idt77252_tx(card);
2739     }
2740     if (stat & SAR_STAT_TMROF) {    /* Timer overflow         */
2741         INTPRINTK("%s: TMROF\n", card->name);
2742         card->irqstat[11]++;
2743         idt77252_collect_stat(card);
2744     }
2745
2746     if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU    */
2747         INTPRINTK("%s: EPDU\n", card->name);
2748         card->irqstat[5]++;
2749         idt77252_rx(card);
2750     }
2751     if (stat & SAR_STAT_RSQAF) {    /* RSQ is 7/8 full        */
2752         INTPRINTK("%s: RSQAF\n", card->name);
2753         card->irqstat[1]++;
2754         idt77252_rx(card);
2755     }
2756     if (stat & SAR_STAT_RSQF) { /* RSQ is full            */
2757         INTPRINTK("%s: RSQF\n", card->name);
2758         card->irqstat[6]++;
2759         idt77252_rx(card);
2760     }
2761     if (stat & SAR_STAT_RAWCF) {    /* Raw cell received      */
2762         INTPRINTK("%s: RAWCF\n", card->name);
2763         card->irqstat[4]++;
2764         idt77252_rx_raw(card);
2765     }
2766
2767     if (stat & SAR_STAT_PHYI) { /* PHY device interrupt   */
2768         INTPRINTK("%s: PHYI", card->name);
2769         card->irqstat[10]++;
2770         if (card->atmdev->phy && card->atmdev->phy->interrupt)
2771             card->atmdev->phy->interrupt(card->atmdev);
2772     }
2773
2774     if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
2775             SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
2776
2777         writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
2778
2779         INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
2780
2781         if (stat & SAR_STAT_FBQ0A)
2782             card->irqstat[2]++;
2783         if (stat & SAR_STAT_FBQ1A)
2784             card->irqstat[3]++;
2785         if (stat & SAR_STAT_FBQ2A)
2786             card->irqstat[7]++;
2787         if (stat & SAR_STAT_FBQ3A)
2788             card->irqstat[8]++;
2789
2790         schedule_work(&card->tqueue);
2791     }
2792
2793 out:
2794     clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
2795     return IRQ_HANDLED;
2796 }
2797
2798 static void
2799 idt77252_softint(struct work_struct *work)
2800 {
2801     struct idt77252_dev *card =
2802         container_of(work, struct idt77252_dev, tqueue);
2803     u32 stat;
2804     int done;
2805
2806     for (done = 1; ; done = 1) {
2807         stat = readl(SAR_REG_STAT) >> 16;
2808
2809         if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
2810             add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
2811             done = 0;
2812         }
2813
2814         stat >>= 4;
2815         if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
2816             add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
2817             done = 0;
2818         }
2819
2820         stat >>= 4;
2821         if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
2822             add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
2823             done = 0;
2824         }
2825
2826         stat >>= 4;
2827         if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
2828             add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
2829             done = 0;
2830         }
2831
2832         if (done)
2833             break;
2834     }
2835
2836     writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
2837 }
2838
2839
2840 static int
2841 open_card_oam(struct idt77252_dev *card)
2842 {
2843     unsigned long flags;
2844     unsigned long addr;
2845     struct vc_map *vc;
2846     int vpi, vci;
2847     int index;
2848     u32 rcte;
2849
2850     for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2851         for (vci = 3; vci < 5; vci++) {
2852             index = VPCI2VC(card, vpi, vci);
2853
2854             vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2855             if (!vc) {
2856                 printk("%s: can't alloc vc\n", card->name);
2857                 return -ENOMEM;
2858             }
2859             vc->index = index;
2860             card->vcs[index] = vc;
2861
2862             flush_rx_pool(card, &vc->rcv.rx_pool);
2863
2864             rcte = SAR_RCTE_CONNECTOPEN |
2865                    SAR_RCTE_RAWCELLINTEN |
2866                    SAR_RCTE_RCQ |
2867                    SAR_RCTE_FBP_1;
2868
2869             addr = card->rct_base + (vc->index << 2);
2870             write_sram(card, addr, rcte);
2871
2872             spin_lock_irqsave(&card->cmd_lock, flags);
2873             writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
2874                    SAR_REG_CMD);
2875             waitfor_idle(card);
2876             spin_unlock_irqrestore(&card->cmd_lock, flags);
2877         }
2878     }
2879
2880     return 0;
2881 }
2882
2883 static void
2884 close_card_oam(struct idt77252_dev *card)
2885 {
2886     unsigned long flags;
2887     unsigned long addr;
2888     struct vc_map *vc;
2889     int vpi, vci;
2890     int index;
2891
2892     for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2893         for (vci = 3; vci < 5; vci++) {
2894             index = VPCI2VC(card, vpi, vci);
2895             vc = card->vcs[index];
2896
2897             addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2898
2899             spin_lock_irqsave(&card->cmd_lock, flags);
2900             writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
2901                    SAR_REG_CMD);
2902             waitfor_idle(card);
2903             spin_unlock_irqrestore(&card->cmd_lock, flags);
2904
2905             if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {
2906                 DPRINTK("%s: closing a VC "
2907                     "with pending rx buffers.\n",
2908                     card->name);
2909
2910                 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2911             }
2912         }
2913     }
2914 }
2915
2916 static int
2917 open_card_ubr0(struct idt77252_dev *card)
2918 {
2919     struct vc_map *vc;
2920
2921     vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2922     if (!vc) {
2923         printk("%s: can't alloc vc\n", card->name);
2924         return -ENOMEM;
2925     }
2926     card->vcs[0] = vc;
2927     vc->class = SCHED_UBR0;
2928
2929     vc->scq = alloc_scq(card, vc->class);
2930     if (!vc->scq) {
2931         printk("%s: can't get SCQ.\n", card->name);
2932         return -ENOMEM;
2933     }
2934
2935     card->scd2vc[0] = vc;
2936     vc->scd_index = 0;
2937     vc->scq->scd = card->scd_base;
2938
2939     fill_scd(card, vc->scq, vc->class);
2940
2941     write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
2942     write_sram(card, card->tct_base + 1, 0);
2943     write_sram(card, card->tct_base + 2, 0);
2944     write_sram(card, card->tct_base + 3, 0);
2945     write_sram(card, card->tct_base + 4, 0);
2946     write_sram(card, card->tct_base + 5, 0);
2947     write_sram(card, card->tct_base + 6, 0);
2948     write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
2949
2950     clear_bit(VCF_IDLE, &vc->flags);
2951     writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
2952     return 0;
2953 }
2954
2955 static int
2956 idt77252_dev_open(struct idt77252_dev *card)
2957 {
2958     u32 conf;
2959
2960     if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
2961         printk("%s: SAR not yet initialized.\n", card->name);
2962         return -1;
2963     }
2964
2965     conf = SAR_CFG_RXPTH|   /* enable receive path                  */
2966         SAR_RX_DELAY |  /* interrupt on complete PDU        */
2967         SAR_CFG_RAWIE | /* interrupt enable on raw cells        */
2968         SAR_CFG_RQFIE | /* interrupt on RSQ almost full         */
2969         SAR_CFG_TMOIE | /* interrupt on timer overflow          */
2970         SAR_CFG_FBIE |  /* interrupt on low free buffers        */
2971         SAR_CFG_TXEN |  /* transmit operation enable            */
2972         SAR_CFG_TXINT | /* interrupt on transmit status         */
2973         SAR_CFG_TXUIE | /* interrupt on transmit underrun       */
2974         SAR_CFG_TXSFI | /* interrupt on TSQ almost full         */
2975         SAR_CFG_PHYIE   /* enable PHY interrupts        */
2976         ;
2977
2978 #ifdef CONFIG_ATM_IDT77252_RCV_ALL
2979     /* Test RAW cell receive. */
2980     conf |= SAR_CFG_VPECA;
2981 #endif
2982
2983     writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
2984
2985     if (open_card_oam(card)) {
2986         printk("%s: Error initializing OAM.\n", card->name);
2987         return -1;
2988     }
2989
2990     if (open_card_ubr0(card)) {
2991         printk("%s: Error initializing UBR0.\n", card->name);
2992         return -1;
2993     }
2994
2995     IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
2996     return 0;
2997 }
2998
2999 static void idt77252_dev_close(struct atm_dev *dev)
3000 {
3001     struct idt77252_dev *card = dev->dev_data;
3002     u32 conf;
3003
3004     close_card_oam(card);
3005
3006     conf = SAR_CFG_RXPTH |  /* enable receive path           */
3007         SAR_RX_DELAY |  /* interrupt on complete PDU     */
3008         SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3009         SAR_CFG_RQFIE | /* interrupt on RSQ almost full  */
3010         SAR_CFG_TMOIE | /* interrupt on timer overflow   */
3011         SAR_CFG_FBIE |  /* interrupt on low free buffers */
3012         SAR_CFG_TXEN |  /* transmit operation enable     */
3013         SAR_CFG_TXINT | /* interrupt on transmit status  */
3014         SAR_CFG_TXUIE | /* interrupt on xmit underrun    */
3015         SAR_CFG_TXSFI   /* interrupt on TSQ almost full  */
3016         ;
3017
3018     writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
3019
3020     DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
3021 }
3022
3023
3024 /*****************************************************************************/
3025 /*                                                                           */
3026 /* Initialisation and Deinitialization of IDT77252                           */
3027 /*                                                                           */
3028 /*****************************************************************************/
3029
3030
3031 static void
3032 deinit_card(struct idt77252_dev *card)
3033 {
3034     struct sk_buff *skb;
3035     int i, j;
3036
3037     if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3038         printk("%s: SAR not yet initialized.\n", card->name);
3039         return;
3040     }
3041     DIPRINTK("idt77252: deinitialize card %u\n", card->index);
3042
3043     writel(0, SAR_REG_CFG);
3044
3045     if (card->atmdev)
3046         atm_dev_deregister(card->atmdev);
3047
3048     for (i = 0; i < 4; i++) {
3049         for (j = 0; j < FBQ_SIZE; j++) {
3050             skb = card->sbpool[i].skb[j];
3051             if (skb) {
3052                 dma_unmap_single(&card->pcidev->dev,
3053                          IDT77252_PRV_PADDR(skb),
3054                          (skb_end_pointer(skb) -
3055                           skb->data),
3056                          DMA_FROM_DEVICE);
3057                 card->sbpool[i].skb[j] = NULL;
3058                 dev_kfree_skb(skb);
3059             }
3060         }
3061     }
3062
3063     vfree(card->soft_tst);
3064
3065     vfree(card->scd2vc);
3066
3067     vfree(card->vcs);
3068
3069     if (card->raw_cell_hnd) {
3070         dma_free_coherent(&card->pcidev->dev, 2 * sizeof(u32),
3071                   card->raw_cell_hnd, card->raw_cell_paddr);
3072     }
3073
3074     if (card->rsq.base) {
3075         DIPRINTK("%s: Release RSQ ...\n", card->name);
3076         deinit_rsq(card);
3077     }
3078
3079     if (card->tsq.base) {
3080         DIPRINTK("%s: Release TSQ ...\n", card->name);
3081         deinit_tsq(card);
3082     }
3083
3084     DIPRINTK("idt77252: Release IRQ.\n");
3085     free_irq(card->pcidev->irq, card);
3086
3087     for (i = 0; i < 4; i++) {
3088         if (card->fbq[i])
3089             iounmap(card->fbq[i]);
3090     }
3091
3092     if (card->membase)
3093         iounmap(card->membase);
3094
3095     clear_bit(IDT77252_BIT_INIT, &card->flags);
3096     DIPRINTK("%s: Card deinitialized.\n", card->name);
3097 }
3098
3099
3100 static void init_sram(struct idt77252_dev *card)
3101 {
3102     int i;
3103
3104     for (i = 0; i < card->sramsize; i += 4)
3105         write_sram(card, (i >> 2), 0);
3106
3107     /* set SRAM layout for THIS card */
3108     if (card->sramsize == (512 * 1024)) {
3109         card->tct_base = SAR_SRAM_TCT_128_BASE;
3110         card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
3111             / SAR_SRAM_TCT_SIZE;
3112         card->rct_base = SAR_SRAM_RCT_128_BASE;
3113         card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
3114             / SAR_SRAM_RCT_SIZE;
3115         card->rt_base = SAR_SRAM_RT_128_BASE;
3116         card->scd_base = SAR_SRAM_SCD_128_BASE;
3117         card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
3118             / SAR_SRAM_SCD_SIZE;
3119         card->tst[0] = SAR_SRAM_TST1_128_BASE;
3120         card->tst[1] = SAR_SRAM_TST2_128_BASE;
3121         card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
3122         card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
3123         card->abrst_size = SAR_ABRSTD_SIZE_8K;
3124         card->fifo_base = SAR_SRAM_FIFO_128_BASE;
3125         card->fifo_size = SAR_RXFD_SIZE_32K;
3126     } else {
3127         card->tct_base = SAR_SRAM_TCT_32_BASE;
3128         card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
3129             / SAR_SRAM_TCT_SIZE;
3130         card->rct_base = SAR_SRAM_RCT_32_BASE;
3131         card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
3132             / SAR_SRAM_RCT_SIZE;
3133         card->rt_base = SAR_SRAM_RT_32_BASE;
3134         card->scd_base = SAR_SRAM_SCD_32_BASE;
3135         card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
3136             / SAR_SRAM_SCD_SIZE;
3137         card->tst[0] = SAR_SRAM_TST1_32_BASE;
3138         card->tst[1] = SAR_SRAM_TST2_32_BASE;
3139         card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
3140         card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
3141         card->abrst_size = SAR_ABRSTD_SIZE_1K;
3142         card->fifo_base = SAR_SRAM_FIFO_32_BASE;
3143         card->fifo_size = SAR_RXFD_SIZE_4K;
3144     }
3145
3146     /* Initialize TCT */
3147     for (i = 0; i < card->tct_size; i++) {
3148         write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
3149         write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
3150         write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
3151         write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
3152         write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
3153         write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
3154         write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
3155         write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
3156     }
3157
3158     /* Initialize RCT */
3159     for (i = 0; i < card->rct_size; i++) {
3160         write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
3161                     (u32) SAR_RCTE_RAWCELLINTEN);
3162         write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
3163                     (u32) 0);
3164         write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
3165                     (u32) 0);
3166         write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
3167                     (u32) 0xffffffff);
3168     }
3169
3170     writel((SAR_FBQ0_LOW << 28) | (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
3171     writel((SAR_FBQ1_LOW << 28) | (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
3172     writel((SAR_FBQ2_LOW << 28) | (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
3173     writel((SAR_FBQ3_LOW << 28) | (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
3174
3175     /* Initialize rate table  */
3176     for (i = 0; i < 256; i++) {
3177         write_sram(card, card->rt_base + i, log_to_rate[i]);
3178     }
3179
3180     for (i = 0; i < 128; i++) {
3181         unsigned int tmp;
3182
3183         tmp  = rate_to_log[(i << 2) + 0] << 0;
3184         tmp |= rate_to_log[(i << 2) + 1] << 8;
3185         tmp |= rate_to_log[(i << 2) + 2] << 16;
3186         tmp |= rate_to_log[(i << 2) + 3] << 24;
3187         write_sram(card, card->rt_base + 256 + i, tmp);
3188     }
3189
3190 #if 0 /* Fill RDF and AIR tables. */
3191     for (i = 0; i < 128; i++) {
3192         unsigned int tmp;
3193
3194         tmp = RDF[0][(i << 1) + 0] << 16;
3195         tmp |= RDF[0][(i << 1) + 1] << 0;
3196         write_sram(card, card->rt_base + 512 + i, tmp);
3197     }
3198
3199     for (i = 0; i < 128; i++) {
3200         unsigned int tmp;
3201
3202         tmp = AIR[0][(i << 1) + 0] << 16;
3203         tmp |= AIR[0][(i << 1) + 1] << 0;
3204         write_sram(card, card->rt_base + 640 + i, tmp);
3205     }
3206 #endif
3207
3208     IPRINTK("%s: initialize rate table ...\n", card->name);
3209     writel(card->rt_base << 2, SAR_REG_RTBL);
3210
3211     /* Initialize TSTs */
3212     IPRINTK("%s: initialize TST ...\n", card->name);
3213     card->tst_free = card->tst_size - 2;    /* last two are jumps */
3214
3215     for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
3216         write_sram(card, i, TSTE_OPC_VAR);
3217     write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3218     idt77252_sram_write_errors = 1;
3219     write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3220     idt77252_sram_write_errors = 0;
3221     for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
3222         write_sram(card, i, TSTE_OPC_VAR);
3223     write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3224     idt77252_sram_write_errors = 1;
3225     write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3226     idt77252_sram_write_errors = 0;
3227
3228     card->tst_index = 0;
3229     writel(card->tst[0] << 2, SAR_REG_TSTB);
3230
3231     /* Initialize ABRSTD and Receive FIFO */
3232     IPRINTK("%s: initialize ABRSTD ...\n", card->name);
3233     writel(card->abrst_size | (card->abrst_base << 2),
3234            SAR_REG_ABRSTD);
3235
3236     IPRINTK("%s: initialize receive fifo ...\n", card->name);
3237     writel(card->fifo_size | (card->fifo_base << 2),
3238            SAR_REG_RXFD);
3239
3240     IPRINTK("%s: SRAM initialization complete.\n", card->name);
3241 }
3242
3243 static int init_card(struct atm_dev *dev)
3244 {
3245     struct idt77252_dev *card = dev->dev_data;
3246     struct pci_dev *pcidev = card->pcidev;
3247     unsigned long tmpl, modl;
3248     unsigned int linkrate, rsvdcr;
3249     unsigned int tst_entries;
3250     struct net_device *tmp;
3251     char tname[10];
3252
3253     u32 size;
3254     u_char pci_byte;
3255     u32 conf;
3256     int i, k;
3257
3258     if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
3259         printk("Error: SAR already initialized.\n");
3260         return -1;
3261     }
3262
3263 /*****************************************************************/
3264 /*   P C I   C O N F I G U R A T I O N                           */
3265 /*****************************************************************/
3266
3267     /* Set PCI Retry-Timeout and TRDY timeout */
3268     IPRINTK("%s: Checking PCI retries.\n", card->name);
3269     if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
3270         printk("%s: can't read PCI retry timeout.\n", card->name);
3271         deinit_card(card);
3272         return -1;
3273     }
3274     if (pci_byte != 0) {
3275         IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3276             card->name, pci_byte);
3277         if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
3278             printk("%s: can't set PCI retry timeout.\n",
3279                    card->name);
3280             deinit_card(card);
3281             return -1;
3282         }
3283     }
3284     IPRINTK("%s: Checking PCI TRDY.\n", card->name);
3285     if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
3286         printk("%s: can't read PCI TRDY timeout.\n", card->name);
3287         deinit_card(card);
3288         return -1;
3289     }
3290     if (pci_byte != 0) {
3291         IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3292                 card->name, pci_byte);
3293         if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
3294             printk("%s: can't set PCI TRDY timeout.\n", card->name);
3295             deinit_card(card);
3296             return -1;
3297         }
3298     }
3299     /* Reset Timer register */
3300     if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
3301         printk("%s: resetting timer overflow.\n", card->name);
3302         writel(SAR_STAT_TMROF, SAR_REG_STAT);
3303     }
3304     IPRINTK("%s: Request IRQ ... ", card->name);
3305     if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_SHARED,
3306             card->name, card) != 0) {
3307         printk("%s: can't allocate IRQ.\n", card->name);
3308         deinit_card(card);
3309         return -1;
3310     }
3311     IPRINTK("got %d.\n", pcidev->irq);
3312
3313 /*****************************************************************/
3314 /*   C H E C K   A N D   I N I T   S R A M                       */
3315 /*****************************************************************/
3316
3317     IPRINTK("%s: Initializing SRAM\n", card->name);
3318
3319     /* preset size of connecton table, so that init_sram() knows about it */
3320     conf =  SAR_CFG_TX_FIFO_SIZE_9 |    /* Use maximum fifo size */
3321         SAR_CFG_RXSTQ_SIZE_8k |     /* Receive Status Queue is 8k */
3322         SAR_CFG_IDLE_CLP |      /* Set CLP on idle cells */
3323 #ifndef ATM_IDT77252_SEND_IDLE
3324         SAR_CFG_NO_IDLE |       /* Do not send idle cells */
3325 #endif
3326         0;
3327
3328     if (card->sramsize == (512 * 1024))
3329         conf |= SAR_CFG_CNTBL_1k;
3330     else
3331         conf |= SAR_CFG_CNTBL_512;
3332
3333     switch (vpibits) {
3334     case 0:
3335         conf |= SAR_CFG_VPVCS_0;
3336         break;
3337     default:
3338     case 1:
3339         conf |= SAR_CFG_VPVCS_1;
3340         break;
3341     case 2:
3342         conf |= SAR_CFG_VPVCS_2;
3343         break;
3344     case 8:
3345         conf |= SAR_CFG_VPVCS_8;
3346         break;
3347     }
3348
3349     writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3350
3351     init_sram(card);
3352
3353 /********************************************************************/
3354 /*  A L L O C   R A M   A N D   S E T   V A R I O U S   T H I N G S */
3355 /********************************************************************/
3356     /* Initialize TSQ */
3357     if (0 != init_tsq(card)) {
3358         deinit_card(card);
3359         return -1;
3360     }
3361     /* Initialize RSQ */
3362     if (0 != init_rsq(card)) {
3363         deinit_card(card);
3364         return -1;
3365     }
3366
3367     card->vpibits = vpibits;
3368     if (card->sramsize == (512 * 1024)) {
3369         card->vcibits = 10 - card->vpibits;
3370     } else {
3371         card->vcibits = 9 - card->vpibits;
3372     }
3373
3374     card->vcimask = 0;
3375     for (k = 0, i = 1; k < card->vcibits; k++) {
3376         card->vcimask |= i;
3377         i <<= 1;
3378     }
3379
3380     IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
3381     writel(0, SAR_REG_VPM);
3382
3383     /* Little Endian Order   */
3384     writel(0, SAR_REG_GP);
3385
3386     /* Initialize RAW Cell Handle Register  */
3387     card->raw_cell_hnd = dma_alloc_coherent(&card->pcidev->dev,
3388                         2 * sizeof(u32),
3389                         &card->raw_cell_paddr,
3390                         GFP_KERNEL);
3391     if (!card->raw_cell_hnd) {
3392         printk("%s: memory allocation failure.\n", card->name);
3393         deinit_card(card);
3394         return -1;
3395     }
3396     writel(card->raw_cell_paddr, SAR_REG_RAWHND);
3397     IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
3398         card->raw_cell_hnd);
3399
3400     size = sizeof(struct vc_map *) * card->tct_size;
3401     IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
3402     card->vcs = vzalloc(size);
3403     if (!card->vcs) {
3404         printk("%s: memory allocation failure.\n", card->name);
3405         deinit_card(card);
3406         return -1;
3407     }
3408
3409     size = sizeof(struct vc_map *) * card->scd_size;
3410     IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3411             card->name, size);
3412     card->scd2vc = vzalloc(size);
3413     if (!card->scd2vc) {
3414         printk("%s: memory allocation failure.\n", card->name);
3415         deinit_card(card);
3416         return -1;
3417     }
3418
3419     size = sizeof(struct tst_info) * (card->tst_size - 2);
3420     IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3421         card->name, size);
3422     card->soft_tst = vmalloc(size);
3423     if (!card->soft_tst) {
3424         printk("%s: memory allocation failure.\n", card->name);
3425         deinit_card(card);
3426         return -1;
3427     }
3428     for (i = 0; i < card->tst_size - 2; i++) {
3429         card->soft_tst[i].tste = TSTE_OPC_VAR;
3430         card->soft_tst[i].vc = NULL;
3431     }
3432
3433     if (dev->phy == NULL) {
3434         printk("%s: No LT device defined.\n", card->name);
3435         deinit_card(card);
3436         return -1;
3437     }
3438     if (dev->phy->ioctl == NULL) {
3439         printk("%s: LT had no IOCTL function defined.\n", card->name);
3440         deinit_card(card);
3441         return -1;
3442     }
3443
3444 #ifdef  CONFIG_ATM_IDT77252_USE_SUNI
3445     /*
3446      * this is a jhs hack to get around special functionality in the
3447      * phy driver for the atecom hardware; the functionality doesn't
3448      * exist in the linux atm suni driver
3449      *
3450      * it isn't the right way to do things, but as the guy from NIST
3451      * said, talking about their measurement of the fine structure
3452      * constant, "it's good enough for government work."
3453      */
3454     linkrate = 149760000;
3455 #endif
3456
3457     card->link_pcr = (linkrate / 8 / 53);
3458     printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3459            card->name, linkrate, card->link_pcr);
3460
3461 #ifdef ATM_IDT77252_SEND_IDLE
3462     card->utopia_pcr = card->link_pcr;
3463 #else
3464     card->utopia_pcr = (160000000 / 8 / 54);
3465 #endif
3466
3467     rsvdcr = 0;
3468     if (card->utopia_pcr > card->link_pcr)
3469         rsvdcr = card->utopia_pcr - card->link_pcr;
3470
3471     tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
3472     modl = tmpl % (unsigned long)card->utopia_pcr;
3473     tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
3474     if (modl)
3475         tst_entries++;
3476     card->tst_free -= tst_entries;
3477     fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
3478
3479 #ifdef HAVE_EEPROM
3480     idt77252_eeprom_init(card);
3481     printk("%s: EEPROM: %02x:", card->name,
3482         idt77252_eeprom_read_status(card));
3483
3484     for (i = 0; i < 0x80; i++) {
3485         printk(" %02x",
3486         idt77252_eeprom_read_byte(card, i)
3487         );
3488     }
3489     printk("\n");
3490 #endif /* HAVE_EEPROM */
3491
3492     /*
3493      * XXX: <hack>
3494      */
3495     sprintf(tname, "eth%d", card->index);
3496     tmp = dev_get_by_name(&init_net, tname);    /* jhs: was "tmp = dev_get(tname);" */
3497     if (tmp) {
3498         memcpy(card->atmdev->esi, tmp->dev_addr, 6);
3499         dev_put(tmp);
3500         printk("%s: ESI %pM\n", card->name, card->atmdev->esi);
3501     }
3502     /*
3503      * XXX: </hack>
3504      */
3505
3506     /* Set Maximum Deficit Count for now. */
3507     writel(0xffff, SAR_REG_MDFCT);
3508
3509     set_bit(IDT77252_BIT_INIT, &card->flags);
3510
3511     XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
3512     return 0;
3513 }
3514
3515
3516 /*****************************************************************************/
3517 /*                                                                           */
3518 /* Probing of IDT77252 ABR SAR                                               */
3519 /*                                                                           */
3520 /*****************************************************************************/
3521
3522
3523 static int idt77252_preset(struct idt77252_dev *card)
3524 {
3525     u16 pci_command;
3526
3527 /*****************************************************************/
3528 /*   P C I   C O N F I G U R A T I O N                           */
3529 /*****************************************************************/
3530
3531     XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3532         card->name);
3533     if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
3534         printk("%s: can't read PCI_COMMAND.\n", card->name);
3535         deinit_card(card);
3536         return -1;
3537     }
3538     if (!(pci_command & PCI_COMMAND_IO)) {
3539         printk("%s: PCI_COMMAND: %04x (?)\n",
3540                card->name, pci_command);
3541         deinit_card(card);
3542         return (-1);
3543     }
3544     pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3545     if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
3546         printk("%s: can't write PCI_COMMAND.\n", card->name);
3547         deinit_card(card);
3548         return -1;
3549     }
3550 /*****************************************************************/
3551 /*   G E N E R I C   R E S E T                                   */
3552 /*****************************************************************/
3553
3554     /* Software reset */
3555     writel(SAR_CFG_SWRST, SAR_REG_CFG);
3556     mdelay(1);
3557     writel(0, SAR_REG_CFG);
3558
3559     IPRINTK("%s: Software resetted.\n", card->name);
3560     return 0;
3561 }
3562
3563
3564 static unsigned long probe_sram(struct idt77252_dev *card)
3565 {
3566     u32 data, addr;
3567
3568     writel(0, SAR_REG_DR0);
3569     writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
3570
3571     for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
3572         writel(ATM_POISON, SAR_REG_DR0);
3573         writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
3574
3575         writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
3576         data = readl(SAR_REG_DR0);
3577
3578         if (data != 0)
3579             break;
3580     }
3581
3582     return addr * sizeof(u32);
3583 }
3584
3585 static int idt77252_init_one(struct pci_dev *pcidev,
3586                  const struct pci_device_id *id)
3587 {
3588     static struct idt77252_dev **last = &idt77252_chain;
3589     static int index = 0;
3590
3591     unsigned long membase, srambase;
3592     struct idt77252_dev *card;
3593     struct atm_dev *dev;
3594     int i, err;
3595
3596
3597     if ((err = pci_enable_device(pcidev))) {
3598         printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev));
3599         return err;
3600     }
3601
3602     if ((err = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)))) {
3603         printk("idt77252: can't enable DMA for PCI device at %s\n", pci_name(pcidev));
3604         goto err_out_disable_pdev;
3605     }
3606
3607     card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
3608     if (!card) {
3609         printk("idt77252-%d: can't allocate private data\n", index);
3610         err = -ENOMEM;
3611         goto err_out_disable_pdev;
3612     }
3613     card->revision = pcidev->revision;
3614     card->index = index;
3615     card->pcidev = pcidev;
3616     sprintf(card->name, "idt77252-%d", card->index);
3617
3618     INIT_WORK(&card->tqueue, idt77252_softint);
3619
3620     membase = pci_resource_start(pcidev, 1);
3621     srambase = pci_resource_start(pcidev, 2);
3622
3623     mutex_init(&card->mutex);
3624     spin_lock_init(&card->cmd_lock);
3625     spin_lock_init(&card->tst_lock);
3626
3627     timer_setup(&card->tst_timer, tst_timer, 0);
3628
3629     /* Do the I/O remapping... */
3630     card->membase = ioremap(membase, 1024);
3631     if (!card->membase) {
3632         printk("%s: can't ioremap() membase\n", card->name);
3633         err = -EIO;
3634         goto err_out_free_card;
3635     }
3636
3637     if (idt77252_preset(card)) {
3638         printk("%s: preset failed\n", card->name);
3639         err = -EIO;
3640         goto err_out_iounmap;
3641     }
3642
3643     dev = atm_dev_register("idt77252", &pcidev->dev, &idt77252_ops, -1,
3644                    NULL);
3645     if (!dev) {
3646         printk("%s: can't register atm device\n", card->name);
3647         err = -EIO;
3648         goto err_out_iounmap;
3649     }
3650     dev->dev_data = card;
3651     card->atmdev = dev;
3652
3653 #ifdef  CONFIG_ATM_IDT77252_USE_SUNI
3654     suni_init(dev);
3655     if (!dev->phy) {
3656         printk("%s: can't init SUNI\n", card->name);
3657         err = -EIO;
3658         goto err_out_deinit_card;
3659     }
3660 #endif  /* CONFIG_ATM_IDT77252_USE_SUNI */
3661
3662     card->sramsize = probe_sram(card);
3663
3664     for (i = 0; i < 4; i++) {
3665         card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4);
3666         if (!card->fbq[i]) {
3667             printk("%s: can't ioremap() FBQ%d\n", card->name, i);
3668             err = -EIO;
3669             goto err_out_deinit_card;
3670         }
3671     }
3672
3673     printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3674            card->name, ((card->revision > 1) && (card->revision < 25)) ?
3675            'A' + card->revision - 1 : '?', membase, srambase,
3676            card->sramsize / 1024);
3677
3678     if (init_card(dev)) {
3679         printk("%s: init_card failed\n", card->name);
3680         err = -EIO;
3681         goto err_out_deinit_card;
3682     }
3683
3684     dev->ci_range.vpi_bits = card->vpibits;
3685     dev->ci_range.vci_bits = card->vcibits;
3686     dev->link_rate = card->link_pcr;
3687
3688     if (dev->phy->start)
3689         dev->phy->start(dev);
3690
3691     if (idt77252_dev_open(card)) {
3692         printk("%s: dev_open failed\n", card->name);
3693         err = -EIO;
3694         goto err_out_stop;
3695     }
3696
3697     *last = card;
3698     last = &card->next;
3699     index++;
3700
3701     return 0;
3702
3703 err_out_stop:
3704     if (dev->phy->stop)
3705         dev->phy->stop(dev);
3706
3707 err_out_deinit_card:
3708     deinit_card(card);
3709
3710 err_out_iounmap:
3711     iounmap(card->membase);
3712
3713 err_out_free_card:
3714     kfree(card);
3715
3716 err_out_disable_pdev:
3717     pci_disable_device(pcidev);
3718     return err;
3719 }
3720
3721 static const struct pci_device_id idt77252_pci_tbl[] =
3722 {
3723     { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77252), 0 },
3724     { 0, }
3725 };
3726
3727 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl);
3728
3729 static struct pci_driver idt77252_driver = {
3730     .name       = "idt77252",
3731     .id_table   = idt77252_pci_tbl,
3732     .probe      = idt77252_init_one,
3733 };
3734
3735 static int __init idt77252_init(void)
3736 {
3737     struct sk_buff *skb;
3738
3739     printk("%s: at %p\n", __func__, idt77252_init);
3740     BUILD_BUG_ON(sizeof(skb->cb) < sizeof(struct idt77252_skb_prv) + sizeof(struct atm_skb_data));
3741     return pci_register_driver(&idt77252_driver);
3742 }
3743
3744 static void __exit idt77252_exit(void)
3745 {
3746     struct idt77252_dev *card;
3747     struct atm_dev *dev;
3748
3749     pci_unregister_driver(&idt77252_driver);
3750
3751     while (idt77252_chain) {
3752         card = idt77252_chain;
3753         dev = card->atmdev;
3754         idt77252_chain = card->next;
3755         del_timer_sync(&card->tst_timer);
3756
3757         if (dev->phy->stop)
3758             dev->phy->stop(dev);
3759         deinit_card(card);
3760         pci_disable_device(card->pcidev);
3761         kfree(card);
3762     }
3763
3764     DIPRINTK("idt77252: finished cleanup-module().\n");
3765 }
3766
3767 module_init(idt77252_init);
3768 module_exit(idt77252_exit);
3769
3770 MODULE_LICENSE("GPL");
3771
3772 module_param(vpibits, uint, 0);
3773 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
3774 #ifdef CONFIG_ATM_IDT77252_DEBUG
3775 module_param(debug, ulong, 0644);
3776 MODULE_PARM_DESC(debug,   "debug bitmap, see drivers/atm/idt77252.h");
3777 #endif
3778
3779 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
3780 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");