drivers/atm/idt77105.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* drivers/atm/idt77105.h - IDT77105 (PHY) declarations */
0003
0004 /* Written 1999 by Greg Banks, NEC Australia <gnb@linuxfan.com>. Based on suni.h */
0005
0006
0007 #ifndef DRIVER_ATM_IDT77105_H
0008 #define DRIVER_ATM_IDT77105_H
0009
0010 #include <linux/atmdev.h>
0011 #include <linux/atmioc.h>
0012
0013
0014 /* IDT77105 registers */
0015
0016 #define IDT77105_MCR        0x0 /* Master Control Register */
0017 #define IDT77105_ISTAT          0x1 /* Interrupt Status */
0018 #define IDT77105_DIAG       0x2 /* Diagnostic Control */
0019 #define IDT77105_LEDHEC     0x3 /* LED Driver & HEC Status/Control */
0020 #define IDT77105_CTRLO      0x4 /* Low Byte Counter Register */
0021 #define IDT77105_CTRHI      0x5 /* High Byte Counter Register */
0022 #define IDT77105_CTRSEL     0x6 /* Counter Register Read Select */
0023
0024 /* IDT77105 register values */
0025
0026 /* MCR */
0027 #define IDT77105_MCR_UPLO   0x80    /* R/W, User Prog'le Output Latch */
0028 #define IDT77105_MCR_DREC   0x40    /* R/W, Discard Receive Error Cells */
0029 #define IDT77105_MCR_ECEIO  0x20    /* R/W, Enable Cell Error Interrupts
0030                                          * Only */
0031 #define IDT77105_MCR_TDPC   0x10    /* R/W, Transmit Data Parity Check */
0032 #define IDT77105_MCR_DRIC   0x08    /* R/W, Discard Received Idle Cells */
0033 #define IDT77105_MCR_HALTTX 0x04    /* R/W, Halt Tx */
0034 #define IDT77105_MCR_UMODE  0x02    /* R/W, Utopia (cell/byte) Mode */
0035 #define IDT77105_MCR_EIP    0x01    /* R/W, Enable Interrupt Pin */
0036
0037 /* ISTAT */
0038 #define IDT77105_ISTAT_GOODSIG  0x40    /* R, Good Signal Bit */
0039 #define IDT77105_ISTAT_HECERR   0x20    /* sticky, HEC Error*/
0040 #define IDT77105_ISTAT_SCR  0x10    /* sticky, Short Cell Received */
0041 #define IDT77105_ISTAT_TPE  0x08    /* sticky, Transmit Parity Error */
0042 #define IDT77105_ISTAT_RSCC 0x04    /* sticky, Rx Signal Condition Change */
0043 #define IDT77105_ISTAT_RSE  0x02    /* sticky, Rx Symbol Error */
0044 #define IDT77105_ISTAT_RFO  0x01    /* sticky, Rx FIFO Overrun */
0045
0046 /* DIAG */
0047 #define IDT77105_DIAG_FTD   0x80    /* R/W, Force TxClav deassert */
0048 #define IDT77105_DIAG_ROS   0x40    /* R/W, RxClav operation select */
0049 #define IDT77105_DIAG_MPCS  0x20    /* R/W, Multi-PHY config'n select */
0050 #define IDT77105_DIAG_RFLUSH    0x10    /* R/W, clear receive FIFO */
0051 #define IDT77105_DIAG_ITPE  0x08    /* R/W, Insert Tx payload error */
0052 #define IDT77105_DIAG_ITHE  0x04    /* R/W, Insert Tx HEC error */
0053 #define IDT77105_DIAG_UMODE 0x02    /* R/W, Utopia (cell/byte) Mode */
0054 #define IDT77105_DIAG_LCMASK    0x03    /* R/W, Loopback Control */
0055
0056 #define IDT77105_DIAG_LC_NORMAL         0x00    /* Receive from network */
0057 #define IDT77105_DIAG_LC_PHY_LOOPBACK   0x02
0058 #define IDT77105_DIAG_LC_LINE_LOOPBACK  0x03
0059
0060 /* LEDHEC */
0061 #define IDT77105_LEDHEC_DRHC    0x40    /* R/W, Disable Rx HEC check */
0062 #define IDT77105_LEDHEC_DTHC    0x20    /* R/W, Disable Tx HEC calculation */
0063 #define IDT77105_LEDHEC_RPWMASK 0x18    /* R/W, RxRef pulse width select */
0064 #define IDT77105_LEDHEC_TFS 0x04    /* R, Tx FIFO Status (1=empty) */
0065 #define IDT77105_LEDHEC_TLS 0x02    /* R, Tx LED Status (1=lit) */
0066 #define IDT77105_LEDHEC_RLS 0x01    /* R, Rx LED Status (1=lit) */
0067
0068 #define IDT77105_LEDHEC_RPW_1   0x00    /* RxRef active for 1 RxClk cycle */
0069 #define IDT77105_LEDHEC_RPW_2   0x08    /* RxRef active for 2 RxClk cycle */
0070 #define IDT77105_LEDHEC_RPW_4   0x10    /* RxRef active for 4 RxClk cycle */
0071 #define IDT77105_LEDHEC_RPW_8   0x18    /* RxRef active for 8 RxClk cycle */
0072
0073 /* CTRSEL */
0074 #define IDT77105_CTRSEL_SEC 0x08    /* W, Symbol Error Counter */
0075 #define IDT77105_CTRSEL_TCC 0x04    /* W, Tx Cell Counter */
0076 #define IDT77105_CTRSEL_RCC 0x02    /* W, Rx Cell Counter */
0077 #define IDT77105_CTRSEL_RHEC    0x01    /* W, Rx HEC Error Counter */
0078
0079 #ifdef __KERNEL__
0080 int idt77105_init(struct atm_dev *dev);
0081 #endif
0082
0083 /*
0084  * Tunable parameters
0085  */
0086
0087 /* Time between samples of the hardware cell counters. Should be <= 1 sec */
0088 #define IDT77105_STATS_TIMER_PERIOD     (HZ)
0089 /* Time between checks to see if the signal has been found again */
0090 #define IDT77105_RESTART_TIMER_PERIOD   (5 * HZ)
0091
0092 #endif