drivers/atm/fore200e.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _FORE200E_H
0003 #define _FORE200E_H
0004
0005 #ifdef __KERNEL__
0006
0007 /* rx buffer sizes */
0008
0009 #define SMALL_BUFFER_SIZE    384     /* size of small buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */
0010 #define LARGE_BUFFER_SIZE    4032    /* size of large buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */
0011
0012
0013 #define RBD_BLK_SIZE         32      /* nbr of supplied rx buffers per rbd */
0014
0015
0016 #define MAX_PDU_SIZE         65535   /* maximum PDU size supported by AALs */
0017
0018
0019 #define BUFFER_S1_SIZE       SMALL_BUFFER_SIZE    /* size of small buffers, scheme 1 */
0020 #define BUFFER_L1_SIZE       LARGE_BUFFER_SIZE    /* size of large buffers, scheme 1 */
0021
0022 #define BUFFER_S2_SIZE       SMALL_BUFFER_SIZE    /* size of small buffers, scheme 2 */
0023 #define BUFFER_L2_SIZE       LARGE_BUFFER_SIZE    /* size of large buffers, scheme 2 */
0024
0025 #define BUFFER_S1_NBR        (RBD_BLK_SIZE * 6)
0026 #define BUFFER_L1_NBR        (RBD_BLK_SIZE * 4)
0027
0028 #define BUFFER_S2_NBR        (RBD_BLK_SIZE * 6)
0029 #define BUFFER_L2_NBR        (RBD_BLK_SIZE * 4)
0030
0031
0032 #define QUEUE_SIZE_CMD       16      /* command queue capacity       */
0033 #define QUEUE_SIZE_RX        64      /* receive queue capacity       */
0034 #define QUEUE_SIZE_TX        256     /* transmit queue capacity      */
0035 #define QUEUE_SIZE_BS        32      /* buffer supply queue capacity */
0036
0037 #define FORE200E_VPI_BITS     0
0038 #define FORE200E_VCI_BITS    10
0039 #define NBR_CONNECT          (1 << (FORE200E_VPI_BITS + FORE200E_VCI_BITS)) /* number of connections */
0040
0041
0042 #define TSD_FIXED            2
0043 #define TSD_EXTENSION        0
0044 #define TSD_NBR              (TSD_FIXED + TSD_EXTENSION)
0045
0046
0047 /* the cp starts putting a received PDU into one *small* buffer,
0048    then it uses a number of *large* buffers for the trailing data.
0049    we compute here the total number of receive segment descriptors
0050    required to hold the largest possible PDU */
0051
0052 #define RSD_REQUIRED  (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE) + 1)
0053
0054 #define RSD_FIXED     3
0055
0056 /* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU,
0057    but we have to keep the size of the receive PDU descriptor multiple of 32 bytes,
0058    so we add one extra RSD to RSD_EXTENSION
0059    (WARNING: THIS MAY CHANGE IF BUFFER SIZES ARE MODIFIED) */
0060
0061 #define RSD_EXTENSION  ((RSD_REQUIRED - RSD_FIXED) + 1)
0062 #define RSD_NBR         (RSD_FIXED + RSD_EXTENSION)
0063
0064
0065 #define FORE200E_DEV(d)          ((struct fore200e*)((d)->dev_data))
0066 #define FORE200E_VCC(d)          ((struct fore200e_vcc*)((d)->dev_data))
0067
0068 /* bitfields endian games */
0069
0070 #if defined(__LITTLE_ENDIAN_BITFIELD)
0071 #define BITFIELD2(b1, b2)                    b1; b2;
0072 #define BITFIELD3(b1, b2, b3)                b1; b2; b3;
0073 #define BITFIELD4(b1, b2, b3, b4)            b1; b2; b3; b4;
0074 #define BITFIELD5(b1, b2, b3, b4, b5)        b1; b2; b3; b4; b5;
0075 #define BITFIELD6(b1, b2, b3, b4, b5, b6)    b1; b2; b3; b4; b5; b6;
0076 #elif defined(__BIG_ENDIAN_BITFIELD)
0077 #define BITFIELD2(b1, b2)                                    b2; b1;
0078 #define BITFIELD3(b1, b2, b3)                            b3; b2; b1;
0079 #define BITFIELD4(b1, b2, b3, b4)                    b4; b3; b2; b1;
0080 #define BITFIELD5(b1, b2, b3, b4, b5)            b5; b4; b3; b2; b1;
0081 #define BITFIELD6(b1, b2, b3, b4, b5, b6)    b6; b5; b4; b3; b2; b1;
0082 #else
0083 #error unknown bitfield endianess
0084 #endif
0085
0086
0087 /* ATM cell header (minus HEC byte) */
0088
0089 typedef struct atm_header {
0090     BITFIELD5(
0091         u32 clp :  1,    /* cell loss priority         */
0092         u32 plt :  3,    /* payload type               */
0093         u32 vci : 16,    /* virtual channel identifier */
0094         u32 vpi :  8,    /* virtual path identifier    */
0095         u32 gfc :  4     /* generic flow control       */
0096    )
0097 } atm_header_t;
0098
0099
0100 /* ATM adaptation layer id */
0101
0102 typedef enum fore200e_aal {
0103     FORE200E_AAL0  = 0,
0104     FORE200E_AAL34 = 4,
0105     FORE200E_AAL5  = 5,
0106 } fore200e_aal_t;
0107
0108
0109 /* transmit PDU descriptor specification */
0110
0111 typedef struct tpd_spec {
0112     BITFIELD4(
0113         u32               length : 16,    /* total PDU length            */
0114         u32               nseg   :  8,    /* number of transmit segments */
0115         enum fore200e_aal aal    :  4,    /* adaptation layer            */
0116         u32               intr   :  4     /* interrupt requested         */
0117     )
0118 } tpd_spec_t;
0119
0120
0121 /* transmit PDU rate control */
0122
0123 typedef struct tpd_rate
0124 {
0125     BITFIELD2(
0126         u32 idle_cells : 16,    /* number of idle cells to insert   */
0127         u32 data_cells : 16     /* number of data cells to transmit */
0128     )
0129 } tpd_rate_t;
0130
0131
0132 /* transmit segment descriptor */
0133
0134 typedef struct tsd {
0135     u32 buffer;    /* transmit buffer DMA address */
0136     u32 length;    /* number of bytes in buffer   */
0137 } tsd_t;
0138
0139
0140 /* transmit PDU descriptor */
0141
0142 typedef struct tpd {
0143     struct atm_header atm_header;        /* ATM header minus HEC byte    */
0144     struct tpd_spec   spec;              /* tpd specification            */
0145     struct tpd_rate   rate;              /* tpd rate control             */
0146     u32               pad;               /* reserved                     */
0147     struct tsd        tsd[ TSD_NBR ];    /* transmit segment descriptors */
0148 } tpd_t;
0149
0150
0151 /* receive segment descriptor */
0152
0153 typedef struct rsd {
0154     u32 handle;    /* host supplied receive buffer handle */
0155     u32 length;    /* number of bytes in buffer           */
0156 } rsd_t;
0157
0158
0159 /* receive PDU descriptor */
0160
0161 typedef struct rpd {
0162     struct atm_header atm_header;        /* ATM header minus HEC byte   */
0163     u32               nseg;              /* number of receive segments  */
0164     struct rsd        rsd[ RSD_NBR ];    /* receive segment descriptors */
0165 } rpd_t;
0166
0167
0168 /* buffer scheme */
0169
0170 typedef enum buffer_scheme {
0171     BUFFER_SCHEME_ONE,
0172     BUFFER_SCHEME_TWO,
0173     BUFFER_SCHEME_NBR    /* always last */
0174 } buffer_scheme_t;
0175
0176
0177 /* buffer magnitude */
0178
0179 typedef enum buffer_magn {
0180     BUFFER_MAGN_SMALL,
0181     BUFFER_MAGN_LARGE,
0182     BUFFER_MAGN_NBR    /* always last */
0183 } buffer_magn_t;
0184
0185
0186 /* receive buffer descriptor */
0187
0188 typedef struct rbd {
0189     u32 handle;          /* host supplied handle            */
0190     u32 buffer_haddr;    /* host DMA address of host buffer */
0191 } rbd_t;
0192
0193
0194 /* receive buffer descriptor block */
0195
0196 typedef struct rbd_block {
0197     struct rbd rbd[ RBD_BLK_SIZE ];    /* receive buffer descriptor */
0198 } rbd_block_t;
0199
0200
0201 /* tpd DMA address */
0202
0203 typedef struct tpd_haddr {
0204     BITFIELD3(
0205         u32 size  :  4,    /* tpd size expressed in 32 byte blocks     */
0206         u32 pad   :  1,    /* reserved                                 */
0207         u32 haddr : 27     /* tpd DMA addr aligned on 32 byte boundary */
0208     )
0209 } tpd_haddr_t;
0210
0211 #define TPD_HADDR_SHIFT 5  /* addr aligned on 32 byte boundary */
0212
0213 /* cp resident transmit queue entry */
0214
0215 typedef struct cp_txq_entry {
0216     struct tpd_haddr tpd_haddr;       /* host DMA address of tpd                */
0217     u32              status_haddr;    /* host DMA address of completion status  */
0218 } cp_txq_entry_t;
0219
0220
0221 /* cp resident receive queue entry */
0222
0223 typedef struct cp_rxq_entry {
0224     u32 rpd_haddr;       /* host DMA address of rpd                */
0225     u32 status_haddr;    /* host DMA address of completion status  */
0226 } cp_rxq_entry_t;
0227
0228
0229 /* cp resident buffer supply queue entry */
0230
0231 typedef struct cp_bsq_entry {
0232     u32 rbd_block_haddr;    /* host DMA address of rbd block          */
0233     u32 status_haddr;       /* host DMA address of completion status  */
0234 } cp_bsq_entry_t;
0235
0236
0237 /* completion status */
0238
0239 typedef volatile enum status {
0240     STATUS_PENDING  = (1<<0),    /* initial status (written by host)  */
0241     STATUS_COMPLETE = (1<<1),    /* completion status (written by cp) */
0242     STATUS_FREE     = (1<<2),    /* initial status (written by host)  */
0243     STATUS_ERROR    = (1<<3)     /* completion status (written by cp) */
0244 } status_t;
0245
0246
0247 /* cp operation code */
0248
0249 typedef enum opcode {
0250     OPCODE_INITIALIZE = 1,          /* initialize board                       */
0251     OPCODE_ACTIVATE_VCIN,           /* activate incoming VCI                  */
0252     OPCODE_ACTIVATE_VCOUT,          /* activate outgoing VCI                  */
0253     OPCODE_DEACTIVATE_VCIN,         /* deactivate incoming VCI                */
0254     OPCODE_DEACTIVATE_VCOUT,        /* deactivate incoing VCI                 */
0255     OPCODE_GET_STATS,               /* get board statistics                   */
0256     OPCODE_SET_OC3,                 /* set OC-3 registers                     */
0257     OPCODE_GET_OC3,                 /* get OC-3 registers                     */
0258     OPCODE_RESET_STATS,             /* reset board statistics                 */
0259     OPCODE_GET_PROM,                /* get expansion PROM data (PCI specific) */
0260     OPCODE_SET_VPI_BITS,            /* set x bits of those decoded by the
0261                        firmware to be low order bits from
0262                        the VPI field of the ATM cell header   */
0263     OPCODE_REQUEST_INTR = (1<<7)    /* request interrupt                      */
0264 } opcode_t;
0265
0266
0267 /* virtual path / virtual channel identifiers */
0268
0269 typedef struct vpvc {
0270     BITFIELD3(
0271         u32 vci : 16,    /* virtual channel identifier */
0272         u32 vpi :  8,    /* virtual path identifier    */
0273         u32 pad :  8     /* reserved                   */
0274     )
0275 } vpvc_t;
0276
0277
0278 /* activate VC command opcode */
0279
0280 typedef struct activate_opcode {
0281     BITFIELD4(
0282         enum opcode        opcode : 8,    /* cp opcode        */
0283         enum fore200e_aal  aal    : 8,    /* adaptation layer */
0284         enum buffer_scheme scheme : 8,    /* buffer scheme    */
0285         u32  pad                  : 8     /* reserved         */
0286    )
0287 } activate_opcode_t;
0288
0289
0290 /* activate VC command block */
0291
0292 typedef struct activate_block {
0293     struct activate_opcode  opcode;    /* activate VC command opcode */
0294     struct vpvc             vpvc;      /* VPI/VCI                    */
0295     u32                     mtu;       /* for AAL0 only              */
0296
0297 } activate_block_t;
0298
0299
0300 /* deactivate VC command opcode */
0301
0302 typedef struct deactivate_opcode {
0303     BITFIELD2(
0304         enum opcode opcode :  8,    /* cp opcode */
0305         u32         pad    : 24     /* reserved  */
0306     )
0307 } deactivate_opcode_t;
0308
0309
0310 /* deactivate VC command block */
0311
0312 typedef struct deactivate_block {
0313     struct deactivate_opcode opcode;    /* deactivate VC command opcode */
0314     struct vpvc              vpvc;      /* VPI/VCI                      */
0315 } deactivate_block_t;
0316
0317
0318 /* OC-3 registers */
0319
0320 typedef struct oc3_regs {
0321     u32 reg[ 128 ];    /* see the PMC Sierra PC5346 S/UNI-155-Lite
0322               Saturn User Network Interface documentation
0323               for a description of the OC-3 chip registers */
0324 } oc3_regs_t;
0325
0326
0327 /* set/get OC-3 regs command opcode */
0328
0329 typedef struct oc3_opcode {
0330     BITFIELD4(
0331         enum opcode opcode : 8,    /* cp opcode                           */
0332     u32         reg    : 8,    /* register index                      */
0333     u32         value  : 8,    /* register value                      */
0334     u32         mask   : 8     /* register mask that specifies which
0335                       bits of the register value field
0336                       are significant                     */
0337     )
0338 } oc3_opcode_t;
0339
0340
0341 /* set/get OC-3 regs command block */
0342
0343 typedef struct oc3_block {
0344     struct oc3_opcode opcode;        /* set/get OC-3 regs command opcode     */
0345     u32               regs_haddr;    /* host DMA address of OC-3 regs buffer */
0346 } oc3_block_t;
0347
0348
0349 /* physical encoding statistics */
0350
0351 typedef struct stats_phy {
0352     __be32 crc_header_errors;    /* cells received with bad header CRC */
0353     __be32 framing_errors;       /* cells received with bad framing    */
0354     __be32 pad[ 2 ];             /* i960 padding                       */
0355 } stats_phy_t;
0356
0357
0358 /* OC-3 statistics */
0359
0360 typedef struct stats_oc3 {
0361     __be32 section_bip8_errors;    /* section 8 bit interleaved parity    */
0362     __be32 path_bip8_errors;       /* path 8 bit interleaved parity       */
0363     __be32 line_bip24_errors;      /* line 24 bit interleaved parity      */
0364     __be32 line_febe_errors;       /* line far end block errors           */
0365     __be32 path_febe_errors;       /* path far end block errors           */
0366     __be32 corr_hcs_errors;        /* correctable header check sequence   */
0367     __be32 ucorr_hcs_errors;       /* uncorrectable header check sequence */
0368     __be32 pad[ 1 ];               /* i960 padding                        */
0369 } stats_oc3_t;
0370
0371
0372 /* ATM statistics */
0373
0374 typedef struct stats_atm {
0375     __be32  cells_transmitted;    /* cells transmitted                 */
0376     __be32  cells_received;       /* cells received                    */
0377     __be32  vpi_bad_range;        /* cell drops: VPI out of range      */
0378     __be32  vpi_no_conn;          /* cell drops: no connection for VPI */
0379     __be32  vci_bad_range;        /* cell drops: VCI out of range      */
0380     __be32  vci_no_conn;          /* cell drops: no connection for VCI */
0381     __be32  pad[ 2 ];             /* i960 padding                      */
0382 } stats_atm_t;
0383
0384 /* AAL0 statistics */
0385
0386 typedef struct stats_aal0 {
0387     __be32  cells_transmitted;    /* cells transmitted */
0388     __be32  cells_received;       /* cells received    */
0389     __be32  cells_dropped;        /* cells dropped     */
0390     __be32  pad[ 1 ];             /* i960 padding      */
0391 } stats_aal0_t;
0392
0393
0394 /* AAL3/4 statistics */
0395
0396 typedef struct stats_aal34 {
0397     __be32  cells_transmitted;         /* cells transmitted from segmented PDUs */
0398     __be32  cells_received;            /* cells reassembled into PDUs           */
0399     __be32  cells_crc_errors;          /* payload CRC error count               */
0400     __be32  cells_protocol_errors;     /* SAR or CS layer protocol errors       */
0401     __be32  cells_dropped;             /* cells dropped: partial reassembly     */
0402     __be32  cspdus_transmitted;        /* CS PDUs transmitted                   */
0403     __be32  cspdus_received;           /* CS PDUs received                      */
0404     __be32  cspdus_protocol_errors;    /* CS layer protocol errors              */
0405     __be32  cspdus_dropped;            /* reassembled PDUs drop'd (in cells)    */
0406     __be32  pad[ 3 ];                  /* i960 padding                          */
0407 } stats_aal34_t;
0408
0409
0410 /* AAL5 statistics */
0411
0412 typedef struct stats_aal5 {
0413     __be32  cells_transmitted;         /* cells transmitted from segmented SDUs */
0414     __be32  cells_received;        /* cells reassembled into SDUs           */
0415     __be32  cells_dropped;         /* reassembled PDUs dropped (in cells)   */
0416     __be32  congestion_experienced;    /* CRC error and length wrong            */
0417     __be32  cspdus_transmitted;        /* CS PDUs transmitted                   */
0418     __be32  cspdus_received;           /* CS PDUs received                      */
0419     __be32  cspdus_crc_errors;         /* CS PDUs CRC errors                    */
0420     __be32  cspdus_protocol_errors;    /* CS layer protocol errors              */
0421     __be32  cspdus_dropped;            /* reassembled PDUs dropped              */
0422     __be32  pad[ 3 ];                  /* i960 padding                          */
0423 } stats_aal5_t;
0424
0425
0426 /* auxiliary statistics */
0427
0428 typedef struct stats_aux {
0429     __be32  small_b1_failed;     /* receive BD allocation failures  */
0430     __be32  large_b1_failed;     /* receive BD allocation failures  */
0431     __be32  small_b2_failed;     /* receive BD allocation failures  */
0432     __be32  large_b2_failed;     /* receive BD allocation failures  */
0433     __be32  rpd_alloc_failed;    /* receive PDU allocation failures */
0434     __be32  receive_carrier;     /* no carrier = 0, carrier = 1     */
0435     __be32  pad[ 2 ];            /* i960 padding                    */
0436 } stats_aux_t;
0437
0438
0439 /* whole statistics buffer */
0440
0441 typedef struct stats {
0442     struct stats_phy   phy;      /* physical encoding statistics */
0443     struct stats_oc3   oc3;      /* OC-3 statistics              */
0444     struct stats_atm   atm;      /* ATM statistics               */
0445     struct stats_aal0  aal0;     /* AAL0 statistics              */
0446     struct stats_aal34 aal34;    /* AAL3/4 statistics            */
0447     struct stats_aal5  aal5;     /* AAL5 statistics              */
0448     struct stats_aux   aux;      /* auxiliary statistics         */
0449 } stats_t;
0450
0451
0452 /* get statistics command opcode */
0453
0454 typedef struct stats_opcode {
0455     BITFIELD2(
0456         enum opcode opcode :  8,    /* cp opcode */
0457         u32         pad    : 24     /* reserved  */
0458     )
0459 } stats_opcode_t;
0460
0461
0462 /* get statistics command block */
0463
0464 typedef struct stats_block {
0465     struct stats_opcode opcode;         /* get statistics command opcode    */
0466     u32                 stats_haddr;    /* host DMA address of stats buffer */
0467 } stats_block_t;
0468
0469
0470 /* expansion PROM data (PCI specific) */
0471
0472 typedef struct prom_data {
0473     u32 hw_revision;      /* hardware revision   */
0474     u32 serial_number;    /* board serial number */
0475     u8  mac_addr[ 8 ];    /* board MAC address   */
0476 } prom_data_t;
0477
0478
0479 /* get expansion PROM data command opcode */
0480
0481 typedef struct prom_opcode {
0482     BITFIELD2(
0483         enum opcode opcode :  8,    /* cp opcode */
0484         u32         pad    : 24     /* reserved  */
0485     )
0486 } prom_opcode_t;
0487
0488
0489 /* get expansion PROM data command block */
0490
0491 typedef struct prom_block {
0492     struct prom_opcode opcode;        /* get PROM data command opcode    */
0493     u32                prom_haddr;    /* host DMA address of PROM buffer */
0494 } prom_block_t;
0495
0496
0497 /* cp command */
0498
0499 typedef union cmd {
0500     enum   opcode           opcode;           /* operation code          */
0501     struct activate_block   activate_block;   /* activate VC             */
0502     struct deactivate_block deactivate_block; /* deactivate VC           */
0503     struct stats_block      stats_block;      /* get statistics          */
0504     struct prom_block       prom_block;       /* get expansion PROM data */
0505     struct oc3_block        oc3_block;        /* get/set OC-3 registers  */
0506     u32                     pad[ 4 ];         /* i960 padding            */
0507 } cmd_t;
0508
0509
0510 /* cp resident command queue */
0511
0512 typedef struct cp_cmdq_entry {
0513     union cmd cmd;             /* command                               */
0514     u32       status_haddr;    /* host DMA address of completion status */
0515     u32       pad[ 3 ];        /* i960 padding                          */
0516 } cp_cmdq_entry_t;
0517
0518
0519 /* host resident transmit queue entry */
0520
0521 typedef struct host_txq_entry {
0522     struct cp_txq_entry __iomem *cp_entry;    /* addr of cp resident tx queue entry       */
0523     enum   status*          status;      /* addr of host resident status             */
0524     struct tpd*             tpd;         /* addr of transmit PDU descriptor          */
0525     u32                     tpd_dma;     /* DMA address of tpd                       */
0526     struct sk_buff*         skb;         /* related skb                              */
0527     void*                   data;        /* copy of misaligned data                  */
0528     unsigned long           incarn;      /* vc_map incarnation when submitted for tx */
0529     struct fore200e_vc_map* vc_map;
0530
0531 } host_txq_entry_t;
0532
0533
0534 /* host resident receive queue entry */
0535
0536 typedef struct host_rxq_entry {
0537     struct cp_rxq_entry __iomem *cp_entry;    /* addr of cp resident rx queue entry */
0538     enum   status*       status;      /* addr of host resident status       */
0539     struct rpd*          rpd;         /* addr of receive PDU descriptor     */
0540     u32                  rpd_dma;     /* DMA address of rpd                 */
0541 } host_rxq_entry_t;
0542
0543
0544 /* host resident buffer supply queue entry */
0545
0546 typedef struct host_bsq_entry {
0547     struct cp_bsq_entry __iomem *cp_entry;         /* addr of cp resident buffer supply queue entry */
0548     enum   status*       status;           /* addr of host resident status                  */
0549     struct rbd_block*    rbd_block;        /* addr of receive buffer descriptor block       */
0550     u32                  rbd_block_dma;    /* DMA address od rdb                            */
0551 } host_bsq_entry_t;
0552
0553
0554 /* host resident command queue entry */
0555
0556 typedef struct host_cmdq_entry {
0557     struct cp_cmdq_entry __iomem *cp_entry;    /* addr of cp resident cmd queue entry */
0558     enum status *status;           /* addr of host resident status        */
0559 } host_cmdq_entry_t;
0560
0561
0562 /* chunk of memory */
0563
0564 typedef struct chunk {
0565     void* alloc_addr;    /* base address of allocated chunk */
0566     void* align_addr;    /* base address of aligned chunk   */
0567     dma_addr_t dma_addr; /* DMA address of aligned chunk    */
0568     int   direction;     /* direction of DMA mapping        */
0569     u32   alloc_size;    /* length of allocated chunk       */
0570     u32   align_size;    /* length of aligned chunk         */
0571 } chunk_t;
0572
0573 #define dma_size align_size             /* DMA useable size */
0574
0575
0576 /* host resident receive buffer */
0577
0578 typedef struct buffer {
0579     struct buffer*       next;        /* next receive buffer     */
0580     enum   buffer_scheme scheme;      /* buffer scheme           */
0581     enum   buffer_magn   magn;        /* buffer magnitude        */
0582     struct chunk         data;        /* data buffer             */
0583 #ifdef FORE200E_BSQ_DEBUG
0584     unsigned long        index;       /* buffer # in queue       */
0585     int                  supplied;    /* 'buffer supplied' flag  */
0586 #endif
0587 } buffer_t;
0588
0589
0590 #if (BITS_PER_LONG == 32)
0591 #define FORE200E_BUF2HDL(buffer)    ((u32)(buffer))
0592 #define FORE200E_HDL2BUF(handle)    ((struct buffer*)(handle))
0593 #else   /* deal with 64 bit pointers */
0594 #define FORE200E_BUF2HDL(buffer)    ((u32)((u64)(buffer)))
0595 #define FORE200E_HDL2BUF(handle)    ((struct buffer*)(((u64)(handle)) | PAGE_OFFSET))
0596 #endif
0597
0598
0599 /* host resident command queue */
0600
0601 typedef struct host_cmdq {
0602     struct host_cmdq_entry host_entry[ QUEUE_SIZE_CMD ];    /* host resident cmd queue entries        */
0603     int                    head;                            /* head of cmd queue                      */
0604     struct chunk           status;                          /* array of completion status      */
0605 } host_cmdq_t;
0606
0607
0608 /* host resident transmit queue */
0609
0610 typedef struct host_txq {
0611     struct host_txq_entry host_entry[ QUEUE_SIZE_TX ];    /* host resident tx queue entries         */
0612     int                   head;                           /* head of tx queue                       */
0613     int                   tail;                           /* tail of tx queue                       */
0614     struct chunk          tpd;                            /* array of tpds                          */
0615     struct chunk          status;                         /* arry of completion status              */
0616     int                   txing;                          /* number of pending PDUs in tx queue     */
0617 } host_txq_t;
0618
0619
0620 /* host resident receive queue */
0621
0622 typedef struct host_rxq {
0623     struct host_rxq_entry  host_entry[ QUEUE_SIZE_RX ];    /* host resident rx queue entries         */
0624     int                    head;                           /* head of rx queue                       */
0625     struct chunk           rpd;                            /* array of rpds                          */
0626     struct chunk           status;                         /* array of completion status             */
0627 } host_rxq_t;
0628
0629
0630 /* host resident buffer supply queues */
0631
0632 typedef struct host_bsq {
0633     struct host_bsq_entry host_entry[ QUEUE_SIZE_BS ];    /* host resident buffer supply queue entries */
0634     int                   head;                           /* head of buffer supply queue               */
0635     struct chunk          rbd_block;                      /* array of rbds                             */
0636     struct chunk          status;                         /* array of completion status                */
0637     struct buffer*        buffer;                         /* array of rx buffers                       */
0638     struct buffer*        freebuf;                        /* list of free rx buffers                   */
0639     volatile int          freebuf_count;                  /* count of free rx buffers                  */
0640 } host_bsq_t;
0641
0642
0643 /* header of the firmware image */
0644
0645 typedef struct fw_header {
0646     __le32 magic;           /* magic number                               */
0647     __le32 version;         /* firmware version id                        */
0648     __le32 load_offset;     /* fw load offset in board memory             */
0649     __le32 start_offset;    /* fw execution start address in board memory */
0650 } fw_header_t;
0651
0652 #define FW_HEADER_MAGIC  0x65726f66    /* 'fore' */
0653
0654
0655 /* receive buffer supply queues scheme specification */
0656
0657 typedef struct bs_spec {
0658     u32 queue_length;      /* queue capacity                     */
0659     u32 buffer_size;       /* host buffer size           */
0660     u32 pool_size;     /* number of rbds             */
0661     u32 supply_blksize;    /* num of rbds in I/O block (multiple
0662                   of 4 between 4 and 124 inclusive)  */
0663 } bs_spec_t;
0664
0665
0666 /* initialization command block (one-time command, not in cmd queue) */
0667
0668 typedef struct init_block {
0669     enum opcode  opcode;               /* initialize command             */
0670     enum status  status;           /* related status word            */
0671     u32          receive_threshold;    /* not used                       */
0672     u32          num_connect;          /* ATM connections                */
0673     u32          cmd_queue_len;        /* length of command queue        */
0674     u32          tx_queue_len;         /* length of transmit queue       */
0675     u32          rx_queue_len;         /* length of receive queue        */
0676     u32          rsd_extension;        /* number of extra 32 byte blocks */
0677     u32          tsd_extension;        /* number of extra 32 byte blocks */
0678     u32          conless_vpvc;         /* not used                       */
0679     u32          pad[ 2 ];             /* force quad alignment           */
0680     struct bs_spec bs_spec[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ];      /* buffer supply queues spec */
0681 } init_block_t;
0682
0683
0684 typedef enum media_type {
0685     MEDIA_TYPE_CAT5_UTP  = 0x06,    /* unshielded twisted pair */
0686     MEDIA_TYPE_MM_OC3_ST = 0x16,    /* multimode fiber ST      */
0687     MEDIA_TYPE_MM_OC3_SC = 0x26,    /* multimode fiber SC      */
0688     MEDIA_TYPE_SM_OC3_ST = 0x36,    /* single-mode fiber ST    */
0689     MEDIA_TYPE_SM_OC3_SC = 0x46     /* single-mode fiber SC    */
0690 } media_type_t;
0691
0692 #define FORE200E_MEDIA_INDEX(media_type)   ((media_type)>>4)
0693
0694
0695 /* cp resident queues */
0696
0697 typedef struct cp_queues {
0698     u32               cp_cmdq;         /* command queue                      */
0699     u32               cp_txq;          /* transmit queue                     */
0700     u32               cp_rxq;          /* receive queue                      */
0701     u32               cp_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ];        /* buffer supply queues */
0702     u32               imask;             /* 1 enables cp to host interrupts  */
0703     u32               istat;             /* 1 for interrupt posted           */
0704     u32               heap_base;         /* offset form beginning of ram     */
0705     u32               heap_size;         /* space available for queues       */
0706     u32               hlogger;           /* non zero for host logging        */
0707     u32               heartbeat;         /* cp heartbeat                     */
0708     u32               fw_release;        /* firmware version                 */
0709     u32               mon960_release;    /* i960 monitor version             */
0710     u32               tq_plen;           /* transmit throughput measurements */
0711     /* make sure the init block remains on a quad word boundary              */
0712     struct init_block init;              /* one time cmd, not in cmd queue   */
0713     enum   media_type media_type;        /* media type id                    */
0714     u32               oc3_revision;      /* OC-3 revision number             */
0715 } cp_queues_t;
0716
0717
0718 /* boot status */
0719
0720 typedef enum boot_status {
0721     BSTAT_COLD_START    = (u32) 0xc01dc01d,    /* cold start              */
0722     BSTAT_SELFTEST_OK   = (u32) 0x02201958,    /* self-test ok            */
0723     BSTAT_SELFTEST_FAIL = (u32) 0xadbadbad,    /* self-test failed        */
0724     BSTAT_CP_RUNNING    = (u32) 0xce11feed,    /* cp is running           */
0725     BSTAT_MON_TOO_BIG   = (u32) 0x10aded00     /* i960 monitor is too big */
0726 } boot_status_t;
0727
0728
0729 /* software UART */
0730
0731 typedef struct soft_uart {
0732     u32 send;    /* write register */
0733     u32 recv;    /* read register  */
0734 } soft_uart_t;
0735
0736 #define FORE200E_CP_MONITOR_UART_FREE     0x00000000
0737 #define FORE200E_CP_MONITOR_UART_AVAIL    0x01000000
0738
0739
0740 /* i960 monitor */
0741
0742 typedef struct cp_monitor {
0743     struct soft_uart    soft_uart;      /* software UART           */
0744     enum boot_status    bstat;          /* boot status             */
0745     u32         app_base;       /* application base offset */
0746     u32         mon_version;    /* i960 monitor version    */
0747 } cp_monitor_t;
0748
0749
0750 /* device state */
0751
0752 typedef enum fore200e_state {
0753     FORE200E_STATE_BLANK,         /* initial state                     */
0754     FORE200E_STATE_REGISTER,      /* device registered                 */
0755     FORE200E_STATE_CONFIGURE,     /* bus interface configured          */
0756     FORE200E_STATE_MAP,           /* board space mapped in host memory */
0757     FORE200E_STATE_RESET,         /* board resetted                    */
0758     FORE200E_STATE_START_FW,      /* firmware started                  */
0759     FORE200E_STATE_INITIALIZE,    /* initialize command successful     */
0760     FORE200E_STATE_INIT_CMDQ,     /* command queue initialized         */
0761     FORE200E_STATE_INIT_TXQ,      /* transmit queue initialized        */
0762     FORE200E_STATE_INIT_RXQ,      /* receive queue initialized         */
0763     FORE200E_STATE_INIT_BSQ,      /* buffer supply queue initialized   */
0764     FORE200E_STATE_ALLOC_BUF,     /* receive buffers allocated         */
0765     FORE200E_STATE_IRQ,           /* host interrupt requested          */
0766     FORE200E_STATE_COMPLETE       /* initialization completed          */
0767 } fore200e_state;
0768
0769
0770 /* PCA-200E registers */
0771
0772 typedef struct fore200e_pca_regs {
0773     volatile u32 __iomem * hcr;    /* address of host control register        */
0774     volatile u32 __iomem * imr;    /* address of host interrupt mask register */
0775     volatile u32 __iomem * psr;    /* address of PCI specific register        */
0776 } fore200e_pca_regs_t;
0777
0778
0779 /* SBA-200E registers */
0780
0781 typedef struct fore200e_sba_regs {
0782     u32 __iomem *hcr;    /* address of host control register              */
0783     u32 __iomem *bsr;    /* address of burst transfer size register       */
0784     u32 __iomem *isr;    /* address of interrupt level selection register */
0785 } fore200e_sba_regs_t;
0786
0787
0788 /* model-specific registers */
0789
0790 typedef union fore200e_regs {
0791     struct fore200e_pca_regs pca;    /* PCA-200E registers */
0792     struct fore200e_sba_regs sba;    /* SBA-200E registers */
0793 } fore200e_regs;
0794
0795
0796 struct fore200e;
0797
0798 /* bus-dependent data */
0799
0800 typedef struct fore200e_bus {
0801     char*                model_name;          /* board model name                       */
0802     char*                proc_name;           /* board name under /proc/atm             */
0803     int                  descr_alignment;     /* tpd/rpd/rbd DMA alignment requirement  */
0804     int                  buffer_alignment;    /* rx buffers DMA alignment requirement   */
0805     int                  status_alignment;    /* status words DMA alignment requirement */
0806     u32                  (*read)(volatile u32 __iomem *);
0807     void                 (*write)(u32, volatile u32 __iomem *);
0808     int                  (*configure)(struct fore200e*);
0809     int                  (*map)(struct fore200e*);
0810     void                 (*reset)(struct fore200e*);
0811     int                  (*prom_read)(struct fore200e*, struct prom_data*);
0812     void                 (*unmap)(struct fore200e*);
0813     void                 (*irq_enable)(struct fore200e*);
0814     int                  (*irq_check)(struct fore200e*);
0815     void                 (*irq_ack)(struct fore200e*);
0816     int                  (*proc_read)(struct fore200e*, char*);
0817 } fore200e_bus_t;
0818
0819 /* vc mapping */
0820
0821 typedef struct fore200e_vc_map {
0822     struct atm_vcc* vcc;       /* vcc entry              */
0823     unsigned long   incarn;    /* vcc incarnation number */
0824 } fore200e_vc_map_t;
0825
0826 #define FORE200E_VC_MAP(fore200e, vpi, vci)  \
0827         (& (fore200e)->vc_map[ ((vpi) << FORE200E_VCI_BITS) | (vci) ])
0828
0829
0830 /* per-device data */
0831
0832 typedef struct fore200e {
0833     struct       list_head     entry;                  /* next device                        */
0834     const struct fore200e_bus* bus;                    /* bus-dependent code and data        */
0835     union        fore200e_regs regs;                   /* bus-dependent registers            */
0836     struct       atm_dev*      atm_dev;                /* ATM device                         */
0837
0838     enum fore200e_state        state;                  /* device state                       */
0839
0840     char                       name[16];               /* device name                        */
0841     struct device          *dev;
0842     int                        irq;                    /* irq number                         */
0843     unsigned long              phys_base;              /* physical base address              */
0844     void __iomem *             virt_base;              /* virtual base address               */
0845
0846     unsigned char              esi[ ESI_LEN ];         /* end system identifier              */
0847
0848     struct cp_monitor __iomem *         cp_monitor;    /* i960 monitor address               */
0849     struct cp_queues __iomem *          cp_queues;              /* cp resident queues                 */
0850     struct host_cmdq           host_cmdq;              /* host resident cmd queue            */
0851     struct host_txq            host_txq;               /* host resident tx queue             */
0852     struct host_rxq            host_rxq;               /* host resident rx queue             */
0853                                                        /* host resident buffer supply queues */
0854     struct host_bsq            host_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ];
0855
0856     u32                        available_cell_rate;    /* remaining pseudo-CBR bw on link    */
0857
0858     int                        loop_mode;              /* S/UNI loopback mode                */
0859
0860     struct stats*              stats;                  /* last snapshot of the stats         */
0861
0862     struct mutex               rate_mtx;               /* protects rate reservation ops      */
0863     spinlock_t                 q_lock;                 /* protects queue ops                 */
0864 #ifdef FORE200E_USE_TASKLET
0865     struct tasklet_struct      tx_tasklet;             /* performs tx interrupt work         */
0866     struct tasklet_struct      rx_tasklet;             /* performs rx interrupt work         */
0867 #endif
0868     unsigned long              tx_sat;                 /* tx queue saturation count          */
0869
0870     unsigned long              incarn_count;
0871     struct fore200e_vc_map     vc_map[ NBR_CONNECT ];  /* vc mapping                         */
0872 } fore200e_t;
0873
0874
0875 /* per-vcc data */
0876
0877 typedef struct fore200e_vcc {
0878     enum buffer_scheme     scheme;             /* rx buffer scheme                   */
0879     struct tpd_rate        rate;               /* tx rate control data               */
0880     int                    rx_min_pdu;         /* size of smallest PDU received      */
0881     int                    rx_max_pdu;         /* size of largest PDU received       */
0882     int                    tx_min_pdu;         /* size of smallest PDU transmitted   */
0883     int                    tx_max_pdu;         /* size of largest PDU transmitted    */
0884     unsigned long          tx_pdu;             /* nbr of tx pdus                     */
0885     unsigned long          rx_pdu;             /* nbr of rx pdus                     */
0886 } fore200e_vcc_t;
0887
0888
0889
0890 /* 200E-series common memory layout */
0891
0892 #define FORE200E_CP_MONITOR_OFFSET  0x00000400    /* i960 monitor interface */
0893 #define FORE200E_CP_QUEUES_OFFSET   0x00004d40    /* cp resident queues     */
0894
0895
0896 /* PCA-200E memory layout */
0897
0898 #define PCA200E_IOSPACE_LENGTH          0x00200000
0899
0900 #define PCA200E_HCR_OFFSET      0x00100000    /* board control register */
0901 #define PCA200E_IMR_OFFSET      0x00100004    /* host IRQ mask register */
0902 #define PCA200E_PSR_OFFSET      0x00100008    /* PCI specific register  */
0903
0904
0905 /* PCA-200E host control register */
0906
0907 #define PCA200E_HCR_RESET     (1<<0)    /* read / write */
0908 #define PCA200E_HCR_HOLD_LOCK (1<<1)    /* read / write */
0909 #define PCA200E_HCR_I960FAIL  (1<<2)    /* read         */
0910 #define PCA200E_HCR_INTRB     (1<<2)    /* write        */
0911 #define PCA200E_HCR_HOLD_ACK  (1<<3)    /* read         */
0912 #define PCA200E_HCR_INTRA     (1<<3)    /* write        */
0913 #define PCA200E_HCR_OUTFULL   (1<<4)    /* read         */
0914 #define PCA200E_HCR_CLRINTR   (1<<4)    /* write        */
0915 #define PCA200E_HCR_ESPHOLD   (1<<5)    /* read         */
0916 #define PCA200E_HCR_INFULL    (1<<6)    /* read         */
0917 #define PCA200E_HCR_TESTMODE  (1<<7)    /* read         */
0918
0919
0920 /* PCA-200E PCI bus interface regs (offsets in PCI config space) */
0921
0922 #define PCA200E_PCI_LATENCY      0x40    /* maximum slave latenty            */
0923 #define PCA200E_PCI_MASTER_CTRL  0x41    /* master control                   */
0924 #define PCA200E_PCI_THRESHOLD    0x42    /* burst / continuous req threshold  */
0925
0926 /* PBI master control register */
0927
0928 #define PCA200E_CTRL_DIS_CACHE_RD      (1<<0)    /* disable cache-line reads                         */
0929 #define PCA200E_CTRL_DIS_WRT_INVAL     (1<<1)    /* disable writes and invalidates                   */
0930 #define PCA200E_CTRL_2_CACHE_WRT_INVAL (1<<2)    /* require 2 cache-lines for writes and invalidates */
0931 #define PCA200E_CTRL_IGN_LAT_TIMER     (1<<3)    /* ignore the latency timer                         */
0932 #define PCA200E_CTRL_ENA_CONT_REQ_MODE (1<<4)    /* enable continuous request mode                   */
0933 #define PCA200E_CTRL_LARGE_PCI_BURSTS  (1<<5)    /* force large PCI bus bursts                       */
0934 #define PCA200E_CTRL_CONVERT_ENDIAN    (1<<6)    /* convert endianess of slave RAM accesses          */
0935
0936
0937
0938 #define SBA200E_PROM_NAME  "FORE,sba-200e"    /* device name in openprom tree */
0939
0940
0941 /* size of SBA-200E registers */
0942
0943 #define SBA200E_HCR_LENGTH        4
0944 #define SBA200E_BSR_LENGTH        4
0945 #define SBA200E_ISR_LENGTH        4
0946 #define SBA200E_RAM_LENGTH  0x40000
0947
0948
0949 /* SBA-200E SBUS burst transfer size register */
0950
0951 #define SBA200E_BSR_BURST4   0x04
0952 #define SBA200E_BSR_BURST8   0x08
0953 #define SBA200E_BSR_BURST16  0x10
0954
0955
0956 /* SBA-200E host control register */
0957
0958 #define SBA200E_HCR_RESET        (1<<0)    /* read / write (sticky) */
0959 #define SBA200E_HCR_HOLD_LOCK    (1<<1)    /* read / write (sticky) */
0960 #define SBA200E_HCR_I960FAIL     (1<<2)    /* read                  */
0961 #define SBA200E_HCR_I960SETINTR  (1<<2)    /* write                 */
0962 #define SBA200E_HCR_OUTFULL      (1<<3)    /* read                  */
0963 #define SBA200E_HCR_INTR_CLR     (1<<3)    /* write                 */
0964 #define SBA200E_HCR_INTR_ENA     (1<<4)    /* read / write (sticky) */
0965 #define SBA200E_HCR_ESPHOLD      (1<<5)    /* read                  */
0966 #define SBA200E_HCR_INFULL       (1<<6)    /* read                  */
0967 #define SBA200E_HCR_TESTMODE     (1<<7)    /* read                  */
0968 #define SBA200E_HCR_INTR_REQ     (1<<8)    /* read                  */
0969
0970 #define SBA200E_HCR_STICKY       (SBA200E_HCR_RESET | SBA200E_HCR_HOLD_LOCK | SBA200E_HCR_INTR_ENA)
0971
0972
0973 #endif /* __KERNEL__ */
0974 #endif /* _FORE200E_H */