drivers/atm/eni.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* drivers/atm/eni.h - Efficient Networks ENI155P device driver declarations */
0003
0004 /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
0005
0006
0007 #ifndef DRIVER_ATM_ENI_H
0008 #define DRIVER_ATM_ENI_H
0009
0010 #include <linux/atm.h>
0011 #include <linux/atmdev.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/sonet.h>
0014 #include <linux/skbuff.h>
0015 #include <linux/time.h>
0016 #include <linux/pci.h>
0017 #include <linux/spinlock.h>
0018 #include <linux/atomic.h>
0019
0020 #include "midway.h"
0021
0022
0023 #define DEV_LABEL   "eni"
0024
0025 #define UBR_BUFFER  (128*1024)  /* UBR buffer size */
0026
0027 #define RX_DMA_BUF    8     /* burst and skip a few things */
0028 #define TX_DMA_BUF  100     /* should be enough for 64 kB */
0029
0030 #define DEFAULT_RX_MULT 300     /* max_sdu*3 */
0031 #define DEFAULT_TX_MULT 300     /* max_sdu*3 */
0032
0033 #define ENI_ZEROES_SIZE   4     /* need that many DMA-able zero bytes */
0034
0035
0036 struct eni_free {
0037     void __iomem *start;        /* counting in bytes */
0038     int order;
0039 };
0040
0041 struct eni_tx {
0042     void __iomem *send;     /* base, 0 if unused */
0043     int prescaler;          /* shaping prescaler */
0044     int resolution;         /* shaping divider */
0045     unsigned long tx_pos;       /* current TX write position */
0046     unsigned long words;        /* size of TX queue */
0047     int index;          /* TX channel number */
0048     int reserved;           /* reserved peak cell rate */
0049     int shaping;            /* shaped peak cell rate */
0050     struct sk_buff_head backlog;    /* queue of waiting TX buffers */
0051 };
0052
0053 struct eni_vcc {
0054     int (*rx)(struct atm_vcc *vcc); /* RX function, NULL if none */
0055     void __iomem *recv;     /* receive buffer */
0056     unsigned long words;        /* its size in words */
0057     unsigned long descr;        /* next descriptor (RX) */
0058     unsigned long rx_pos;       /* current RX descriptor pos */
0059     struct eni_tx *tx;      /* TXer, NULL if none */
0060     int rxing;          /* number of pending PDUs */
0061     int servicing;          /* number of waiting VCs (0 or 1) */
0062     int txing;          /* number of pending TX bytes */
0063     ktime_t timestamp;      /* for RX timing */
0064     struct atm_vcc *next;       /* next pending RX */
0065     struct sk_buff *last;       /* last PDU being DMAed (used to carry
0066                        discard information) */
0067 };
0068
0069 struct eni_dev {
0070     /*-------------------------------- spinlock */
0071     spinlock_t lock;        /* sync with interrupt */
0072     struct tasklet_struct task; /* tasklet for interrupt work */
0073     u32 events;         /* pending events */
0074     /*-------------------------------- base pointers into Midway address
0075                        space */
0076     void __iomem *ioaddr;
0077     void __iomem *phy;      /* PHY interface chip registers */
0078     void __iomem *reg;      /* register base */
0079     void __iomem *ram;      /* RAM base */
0080     void __iomem *vci;      /* VCI table */
0081     void __iomem *rx_dma;       /* RX DMA queue */
0082     void __iomem *tx_dma;       /* TX DMA queue */
0083     void __iomem *service;      /* service list */
0084     /*-------------------------------- TX part */
0085     struct eni_tx tx[NR_CHAN];  /* TX channels */
0086     struct eni_tx *ubr;     /* UBR channel */
0087     struct sk_buff_head tx_queue;   /* PDUs currently being TX DMAed*/
0088     wait_queue_head_t tx_wait;  /* for close */
0089     int tx_bw;          /* remaining bandwidth */
0090     u32 dma[TX_DMA_BUF*2];      /* DMA request scratch area */
0091     struct eni_zero {       /* aligned "magic" zeroes */
0092         u32 *addr;
0093         dma_addr_t dma;
0094     } zero;
0095     int tx_mult;            /* buffer size multiplier (percent) */
0096     /*-------------------------------- RX part */
0097     u32 serv_read;          /* host service read index */
0098     struct atm_vcc *fast,*last_fast;/* queues of VCCs with pending PDUs */
0099     struct atm_vcc *slow,*last_slow;
0100     struct atm_vcc **rx_map;    /* for fast lookups */
0101     struct sk_buff_head rx_queue;   /* PDUs currently being RX-DMAed */
0102     wait_queue_head_t rx_wait;  /* for close */
0103     int rx_mult;            /* buffer size multiplier (percent) */
0104     /*-------------------------------- statistics */
0105     unsigned long lost;     /* number of lost cells (RX) */
0106     /*-------------------------------- memory management */
0107     unsigned long base_diff;    /* virtual-real base address */
0108     int free_len;           /* free list length */
0109     struct eni_free *free_list; /* free list */
0110     int free_list_size;     /* maximum size of free list */
0111     /*-------------------------------- ENI links */
0112     struct atm_dev *more;       /* other ENI devices */
0113     /*-------------------------------- general information */
0114     int mem;            /* RAM on board (in bytes) */
0115     int asic;           /* PCI interface type, 0 for FPGA */
0116     unsigned int irq;       /* IRQ */
0117     struct pci_dev *pci_dev;    /* PCI stuff */
0118 };
0119
0120
0121 #define ENI_DEV(d) ((struct eni_dev *) (d)->dev_data)
0122 #define ENI_VCC(d) ((struct eni_vcc *) (d)->dev_data)
0123
0124
0125 struct eni_skb_prv {
0126     struct atm_skb_data _;      /* reserved */
0127     unsigned long pos;      /* position of next descriptor */
0128     int size;           /* PDU size in reassembly buffer */
0129     dma_addr_t paddr;       /* DMA handle */
0130 };
0131
0132 #define ENI_PRV_SIZE(skb) (((struct eni_skb_prv *) (skb)->cb)->size)
0133 #define ENI_PRV_POS(skb) (((struct eni_skb_prv *) (skb)->cb)->pos)
0134 #define ENI_PRV_PADDR(skb) (((struct eni_skb_prv *) (skb)->cb)->paddr)
0135
0136 #endif