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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  sata_via.c - VIA Serial ATA controllers
0004  *
0005  *  Maintained by:  Tejun Heo <tj@kernel.org>
0006  *         Please ALWAYS copy linux-ide@vger.kernel.org
0007  *         on emails.
0008  *
0009  *  Copyright 2003-2004 Red Hat, Inc.  All rights reserved.
0010  *  Copyright 2003-2004 Jeff Garzik
0011  *
0012  *  libata documentation is available via 'make {ps|pdf}docs',
0013  *  as Documentation/driver-api/libata.rst
0014  *
0015  *  Hardware documentation available under NDA.
0016  */
0017 
0018 #include <linux/kernel.h>
0019 #include <linux/module.h>
0020 #include <linux/pci.h>
0021 #include <linux/blkdev.h>
0022 #include <linux/delay.h>
0023 #include <linux/device.h>
0024 #include <scsi/scsi.h>
0025 #include <scsi/scsi_cmnd.h>
0026 #include <scsi/scsi_host.h>
0027 #include <linux/libata.h>
0028 
0029 #define DRV_NAME    "sata_via"
0030 #define DRV_VERSION "2.6"
0031 
0032 /*
0033  * vt8251 is different from other sata controllers of VIA.  It has two
0034  * channels, each channel has both Master and Slave slot.
0035  */
0036 enum board_ids_enum {
0037     vt6420,
0038     vt6421,
0039     vt8251,
0040 };
0041 
0042 enum {
0043     SATA_CHAN_ENAB      = 0x40, /* SATA channel enable */
0044     SATA_INT_GATE       = 0x41, /* SATA interrupt gating */
0045     SATA_NATIVE_MODE    = 0x42, /* Native mode enable */
0046     SVIA_MISC_3     = 0x46, /* Miscellaneous Control III */
0047     PATA_UDMA_TIMING    = 0xB3, /* PATA timing for DMA/ cable detect */
0048     PATA_PIO_TIMING     = 0xAB, /* PATA timing register */
0049 
0050     PORT0           = (1 << 1),
0051     PORT1           = (1 << 0),
0052     ALL_PORTS       = PORT0 | PORT1,
0053 
0054     NATIVE_MODE_ALL     = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4),
0055 
0056     SATA_EXT_PHY        = (1 << 6), /* 0==use PATA, 1==ext phy */
0057 
0058     SATA_HOTPLUG        = (1 << 5), /* enable IRQ on hotplug */
0059 };
0060 
0061 struct svia_priv {
0062     bool            wd_workaround;
0063 };
0064 
0065 static int vt6420_hotplug;
0066 module_param_named(vt6420_hotplug, vt6420_hotplug, int, 0644);
0067 MODULE_PARM_DESC(vt6420_hotplug, "Enable hot-plug support for VT6420 (0=Don't support, 1=support)");
0068 
0069 static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
0070 #ifdef CONFIG_PM_SLEEP
0071 static int svia_pci_device_resume(struct pci_dev *pdev);
0072 #endif
0073 static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
0074 static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
0075 static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val);
0076 static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val);
0077 static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf);
0078 static void svia_noop_freeze(struct ata_port *ap);
0079 static int vt6420_prereset(struct ata_link *link, unsigned long deadline);
0080 static void vt6420_bmdma_start(struct ata_queued_cmd *qc);
0081 static int vt6421_pata_cable_detect(struct ata_port *ap);
0082 static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev);
0083 static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev);
0084 static void vt6421_error_handler(struct ata_port *ap);
0085 
0086 static const struct pci_device_id svia_pci_tbl[] = {
0087     { PCI_VDEVICE(VIA, 0x5337), vt6420 },
0088     { PCI_VDEVICE(VIA, 0x0591), vt6420 }, /* 2 sata chnls (Master) */
0089     { PCI_VDEVICE(VIA, 0x3149), vt6420 }, /* 2 sata chnls (Master) */
0090     { PCI_VDEVICE(VIA, 0x3249), vt6421 }, /* 2 sata chnls, 1 pata chnl */
0091     { PCI_VDEVICE(VIA, 0x5372), vt6420 },
0092     { PCI_VDEVICE(VIA, 0x7372), vt6420 },
0093     { PCI_VDEVICE(VIA, 0x5287), vt8251 }, /* 2 sata chnls (Master/Slave) */
0094     { PCI_VDEVICE(VIA, 0x9000), vt8251 },
0095 
0096     { } /* terminate list */
0097 };
0098 
0099 static struct pci_driver svia_pci_driver = {
0100     .name           = DRV_NAME,
0101     .id_table       = svia_pci_tbl,
0102     .probe          = svia_init_one,
0103 #ifdef CONFIG_PM_SLEEP
0104     .suspend        = ata_pci_device_suspend,
0105     .resume         = svia_pci_device_resume,
0106 #endif
0107     .remove         = ata_pci_remove_one,
0108 };
0109 
0110 static struct scsi_host_template svia_sht = {
0111     ATA_BMDMA_SHT(DRV_NAME),
0112 };
0113 
0114 static struct ata_port_operations svia_base_ops = {
0115     .inherits       = &ata_bmdma_port_ops,
0116     .sff_tf_load        = svia_tf_load,
0117 };
0118 
0119 static struct ata_port_operations vt6420_sata_ops = {
0120     .inherits       = &svia_base_ops,
0121     .freeze         = svia_noop_freeze,
0122     .prereset       = vt6420_prereset,
0123     .bmdma_start        = vt6420_bmdma_start,
0124 };
0125 
0126 static struct ata_port_operations vt6421_pata_ops = {
0127     .inherits       = &svia_base_ops,
0128     .cable_detect       = vt6421_pata_cable_detect,
0129     .set_piomode        = vt6421_set_pio_mode,
0130     .set_dmamode        = vt6421_set_dma_mode,
0131 };
0132 
0133 static struct ata_port_operations vt6421_sata_ops = {
0134     .inherits       = &svia_base_ops,
0135     .scr_read       = svia_scr_read,
0136     .scr_write      = svia_scr_write,
0137     .error_handler      = vt6421_error_handler,
0138 };
0139 
0140 static struct ata_port_operations vt8251_ops = {
0141     .inherits       = &svia_base_ops,
0142     .hardreset      = sata_std_hardreset,
0143     .scr_read       = vt8251_scr_read,
0144     .scr_write      = vt8251_scr_write,
0145 };
0146 
0147 static const struct ata_port_info vt6420_port_info = {
0148     .flags      = ATA_FLAG_SATA,
0149     .pio_mask   = ATA_PIO4,
0150     .mwdma_mask = ATA_MWDMA2,
0151     .udma_mask  = ATA_UDMA6,
0152     .port_ops   = &vt6420_sata_ops,
0153 };
0154 
0155 static const struct ata_port_info vt6421_sport_info = {
0156     .flags      = ATA_FLAG_SATA,
0157     .pio_mask   = ATA_PIO4,
0158     .mwdma_mask = ATA_MWDMA2,
0159     .udma_mask  = ATA_UDMA6,
0160     .port_ops   = &vt6421_sata_ops,
0161 };
0162 
0163 static const struct ata_port_info vt6421_pport_info = {
0164     .flags      = ATA_FLAG_SLAVE_POSS,
0165     .pio_mask   = ATA_PIO4,
0166     /* No MWDMA */
0167     .udma_mask  = ATA_UDMA6,
0168     .port_ops   = &vt6421_pata_ops,
0169 };
0170 
0171 static const struct ata_port_info vt8251_port_info = {
0172     .flags      = ATA_FLAG_SATA | ATA_FLAG_SLAVE_POSS,
0173     .pio_mask   = ATA_PIO4,
0174     .mwdma_mask = ATA_MWDMA2,
0175     .udma_mask  = ATA_UDMA6,
0176     .port_ops   = &vt8251_ops,
0177 };
0178 
0179 MODULE_AUTHOR("Jeff Garzik");
0180 MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers");
0181 MODULE_LICENSE("GPL");
0182 MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
0183 MODULE_VERSION(DRV_VERSION);
0184 
0185 static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
0186 {
0187     if (sc_reg > SCR_CONTROL)
0188         return -EINVAL;
0189     *val = ioread32(link->ap->ioaddr.scr_addr + (4 * sc_reg));
0190     return 0;
0191 }
0192 
0193 static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
0194 {
0195     if (sc_reg > SCR_CONTROL)
0196         return -EINVAL;
0197     iowrite32(val, link->ap->ioaddr.scr_addr + (4 * sc_reg));
0198     return 0;
0199 }
0200 
0201 static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
0202 {
0203     static const u8 ipm_tbl[] = { 1, 2, 6, 0 };
0204     struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
0205     int slot = 2 * link->ap->port_no + link->pmp;
0206     u32 v = 0;
0207     u8 raw;
0208 
0209     switch (scr) {
0210     case SCR_STATUS:
0211         pci_read_config_byte(pdev, 0xA0 + slot, &raw);
0212 
0213         /* read the DET field, bit0 and 1 of the config byte */
0214         v |= raw & 0x03;
0215 
0216         /* read the SPD field, bit4 of the configure byte */
0217         if (raw & (1 << 4))
0218             v |= 0x02 << 4;
0219         else
0220             v |= 0x01 << 4;
0221 
0222         /* read the IPM field, bit2 and 3 of the config byte */
0223         v |= ipm_tbl[(raw >> 2) & 0x3];
0224         break;
0225 
0226     case SCR_ERROR:
0227         /* devices other than 5287 uses 0xA8 as base */
0228         WARN_ON(pdev->device != 0x5287);
0229         pci_read_config_dword(pdev, 0xB0 + slot * 4, &v);
0230         break;
0231 
0232     case SCR_CONTROL:
0233         pci_read_config_byte(pdev, 0xA4 + slot, &raw);
0234 
0235         /* read the DET field, bit0 and bit1 */
0236         v |= ((raw & 0x02) << 1) | (raw & 0x01);
0237 
0238         /* read the IPM field, bit2 and bit3 */
0239         v |= ((raw >> 2) & 0x03) << 8;
0240         break;
0241 
0242     default:
0243         return -EINVAL;
0244     }
0245 
0246     *val = v;
0247     return 0;
0248 }
0249 
0250 static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val)
0251 {
0252     struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
0253     int slot = 2 * link->ap->port_no + link->pmp;
0254     u32 v = 0;
0255 
0256     switch (scr) {
0257     case SCR_ERROR:
0258         /* devices other than 5287 uses 0xA8 as base */
0259         WARN_ON(pdev->device != 0x5287);
0260         pci_write_config_dword(pdev, 0xB0 + slot * 4, val);
0261         return 0;
0262 
0263     case SCR_CONTROL:
0264         /* set the DET field */
0265         v |= ((val & 0x4) >> 1) | (val & 0x1);
0266 
0267         /* set the IPM field */
0268         v |= ((val >> 8) & 0x3) << 2;
0269 
0270         pci_write_config_byte(pdev, 0xA4 + slot, v);
0271         return 0;
0272 
0273     default:
0274         return -EINVAL;
0275     }
0276 }
0277 
0278 /**
0279  *  svia_tf_load - send taskfile registers to host controller
0280  *  @ap: Port to which output is sent
0281  *  @tf: ATA taskfile register set
0282  *
0283  *  Outputs ATA taskfile to standard ATA host controller.
0284  *
0285  *  This is to fix the internal bug of via chipsets, which will
0286  *  reset the device register after changing the IEN bit on ctl
0287  *  register.
0288  */
0289 static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
0290 {
0291     struct ata_taskfile ttf;
0292 
0293     if (tf->ctl != ap->last_ctl)  {
0294         ttf = *tf;
0295         ttf.flags |= ATA_TFLAG_DEVICE;
0296         tf = &ttf;
0297     }
0298     ata_sff_tf_load(ap, tf);
0299 }
0300 
0301 static void svia_noop_freeze(struct ata_port *ap)
0302 {
0303     /* Some VIA controllers choke if ATA_NIEN is manipulated in
0304      * certain way.  Leave it alone and just clear pending IRQ.
0305      */
0306     ap->ops->sff_check_status(ap);
0307     ata_bmdma_irq_clear(ap);
0308 }
0309 
0310 /**
0311  *  vt6420_prereset - prereset for vt6420
0312  *  @link: target ATA link
0313  *  @deadline: deadline jiffies for the operation
0314  *
0315  *  SCR registers on vt6420 are pieces of shit and may hang the
0316  *  whole machine completely if accessed with the wrong timing.
0317  *  To avoid such catastrophe, vt6420 doesn't provide generic SCR
0318  *  access operations, but uses SStatus and SControl only during
0319  *  boot probing in controlled way.
0320  *
0321  *  As the old (pre EH update) probing code is proven to work, we
0322  *  strictly follow the access pattern.
0323  *
0324  *  LOCKING:
0325  *  Kernel thread context (may sleep)
0326  *
0327  *  RETURNS:
0328  *  0 on success, -errno otherwise.
0329  */
0330 static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
0331 {
0332     struct ata_port *ap = link->ap;
0333     struct ata_eh_context *ehc = &ap->link.eh_context;
0334     unsigned long timeout = jiffies + (HZ * 5);
0335     u32 sstatus, scontrol;
0336     int online;
0337 
0338     /* don't do any SCR stuff if we're not loading */
0339     if (!(ap->pflags & ATA_PFLAG_LOADING))
0340         goto skip_scr;
0341 
0342     /* Resume phy.  This is the old SATA resume sequence */
0343     svia_scr_write(link, SCR_CONTROL, 0x300);
0344     svia_scr_read(link, SCR_CONTROL, &scontrol); /* flush */
0345 
0346     /* wait for phy to become ready, if necessary */
0347     do {
0348         ata_msleep(link->ap, 200);
0349         svia_scr_read(link, SCR_STATUS, &sstatus);
0350         if ((sstatus & 0xf) != 1)
0351             break;
0352     } while (time_before(jiffies, timeout));
0353 
0354     /* open code sata_print_link_status() */
0355     svia_scr_read(link, SCR_STATUS, &sstatus);
0356     svia_scr_read(link, SCR_CONTROL, &scontrol);
0357 
0358     online = (sstatus & 0xf) == 0x3;
0359 
0360     ata_port_info(ap,
0361               "SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
0362               online ? "up" : "down", sstatus, scontrol);
0363 
0364     /* SStatus is read one more time */
0365     svia_scr_read(link, SCR_STATUS, &sstatus);
0366 
0367     if (!online) {
0368         /* tell EH to bail */
0369         ehc->i.action &= ~ATA_EH_RESET;
0370         return 0;
0371     }
0372 
0373  skip_scr:
0374     /* wait for !BSY */
0375     ata_sff_wait_ready(link, deadline);
0376 
0377     return 0;
0378 }
0379 
0380 static void vt6420_bmdma_start(struct ata_queued_cmd *qc)
0381 {
0382     struct ata_port *ap = qc->ap;
0383     if ((qc->tf.command == ATA_CMD_PACKET) &&
0384         (qc->scsicmd->sc_data_direction == DMA_TO_DEVICE)) {
0385         /* Prevents corruption on some ATAPI burners */
0386         ata_sff_pause(ap);
0387     }
0388     ata_bmdma_start(qc);
0389 }
0390 
0391 static int vt6421_pata_cable_detect(struct ata_port *ap)
0392 {
0393     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0394     u8 tmp;
0395 
0396     pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp);
0397     if (tmp & 0x10)
0398         return ATA_CBL_PATA40;
0399     return ATA_CBL_PATA80;
0400 }
0401 
0402 static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
0403 {
0404     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0405     static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 };
0406     pci_write_config_byte(pdev, PATA_PIO_TIMING - adev->devno,
0407                   pio_bits[adev->pio_mode - XFER_PIO_0]);
0408 }
0409 
0410 static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
0411 {
0412     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0413     static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 };
0414     pci_write_config_byte(pdev, PATA_UDMA_TIMING - adev->devno,
0415                   udma_bits[adev->dma_mode - XFER_UDMA_0]);
0416 }
0417 
0418 static const unsigned int svia_bar_sizes[] = {
0419     8, 4, 8, 4, 16, 256
0420 };
0421 
0422 static const unsigned int vt6421_bar_sizes[] = {
0423     16, 16, 16, 16, 32, 128
0424 };
0425 
0426 static void __iomem *svia_scr_addr(void __iomem *addr, unsigned int port)
0427 {
0428     return addr + (port * 128);
0429 }
0430 
0431 static void __iomem *vt6421_scr_addr(void __iomem *addr, unsigned int port)
0432 {
0433     return addr + (port * 64);
0434 }
0435 
0436 static void vt6421_init_addrs(struct ata_port *ap)
0437 {
0438     void __iomem * const * iomap = ap->host->iomap;
0439     void __iomem *reg_addr = iomap[ap->port_no];
0440     void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8);
0441     struct ata_ioports *ioaddr = &ap->ioaddr;
0442 
0443     ioaddr->cmd_addr = reg_addr;
0444     ioaddr->altstatus_addr =
0445     ioaddr->ctl_addr = (void __iomem *)
0446         ((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS);
0447     ioaddr->bmdma_addr = bmdma_addr;
0448     ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no);
0449 
0450     ata_sff_std_ports(ioaddr);
0451 
0452     ata_port_pbar_desc(ap, ap->port_no, -1, "port");
0453     ata_port_pbar_desc(ap, 4, ap->port_no * 8, "bmdma");
0454 }
0455 
0456 static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
0457 {
0458     const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL };
0459     struct ata_host *host;
0460     int rc;
0461 
0462     if (vt6420_hotplug) {
0463         ppi[0]->port_ops->scr_read = svia_scr_read;
0464         ppi[0]->port_ops->scr_write = svia_scr_write;
0465     }
0466 
0467     rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
0468     if (rc)
0469         return rc;
0470     *r_host = host;
0471 
0472     rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
0473     if (rc) {
0474         dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n");
0475         return rc;
0476     }
0477 
0478     host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0);
0479     host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1);
0480 
0481     return 0;
0482 }
0483 
0484 static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
0485 {
0486     const struct ata_port_info *ppi[] =
0487         { &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info };
0488     struct ata_host *host;
0489     int i, rc;
0490 
0491     *r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi));
0492     if (!host) {
0493         dev_err(&pdev->dev, "failed to allocate host\n");
0494         return -ENOMEM;
0495     }
0496 
0497     rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
0498     if (rc) {
0499         dev_err(&pdev->dev, "failed to request/iomap PCI BARs (errno=%d)\n",
0500             rc);
0501         return rc;
0502     }
0503     host->iomap = pcim_iomap_table(pdev);
0504 
0505     for (i = 0; i < host->n_ports; i++)
0506         vt6421_init_addrs(host->ports[i]);
0507 
0508     return dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
0509 }
0510 
0511 static int vt8251_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
0512 {
0513     const struct ata_port_info *ppi[] = { &vt8251_port_info, NULL };
0514     struct ata_host *host;
0515     int i, rc;
0516 
0517     rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
0518     if (rc)
0519         return rc;
0520     *r_host = host;
0521 
0522     rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
0523     if (rc) {
0524         dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n");
0525         return rc;
0526     }
0527 
0528     /* 8251 hosts four sata ports as M/S of the two channels */
0529     for (i = 0; i < host->n_ports; i++)
0530         ata_slave_link_init(host->ports[i]);
0531 
0532     return 0;
0533 }
0534 
0535 static void svia_wd_fix(struct pci_dev *pdev)
0536 {
0537     u8 tmp8;
0538 
0539     pci_read_config_byte(pdev, 0x52, &tmp8);
0540     pci_write_config_byte(pdev, 0x52, tmp8 | BIT(2));
0541 }
0542 
0543 static irqreturn_t vt642x_interrupt(int irq, void *dev_instance)
0544 {
0545     struct ata_host *host = dev_instance;
0546     irqreturn_t rc = ata_bmdma_interrupt(irq, dev_instance);
0547 
0548     /* if the IRQ was not handled, it might be a hotplug IRQ */
0549     if (rc != IRQ_HANDLED) {
0550         u32 serror;
0551         unsigned long flags;
0552 
0553         spin_lock_irqsave(&host->lock, flags);
0554         /* check for hotplug on port 0 */
0555         svia_scr_read(&host->ports[0]->link, SCR_ERROR, &serror);
0556         if (serror & SERR_PHYRDY_CHG) {
0557             ata_ehi_hotplugged(&host->ports[0]->link.eh_info);
0558             ata_port_freeze(host->ports[0]);
0559             rc = IRQ_HANDLED;
0560         }
0561         /* check for hotplug on port 1 */
0562         svia_scr_read(&host->ports[1]->link, SCR_ERROR, &serror);
0563         if (serror & SERR_PHYRDY_CHG) {
0564             ata_ehi_hotplugged(&host->ports[1]->link.eh_info);
0565             ata_port_freeze(host->ports[1]);
0566             rc = IRQ_HANDLED;
0567         }
0568         spin_unlock_irqrestore(&host->lock, flags);
0569     }
0570 
0571     return rc;
0572 }
0573 
0574 static void vt6421_error_handler(struct ata_port *ap)
0575 {
0576     struct svia_priv *hpriv = ap->host->private_data;
0577     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0578     u32 serror;
0579 
0580     /* see svia_configure() for description */
0581     if (!hpriv->wd_workaround) {
0582         svia_scr_read(&ap->link, SCR_ERROR, &serror);
0583         if (serror == 0x1000500) {
0584             ata_port_warn(ap, "Incompatible drive: enabling workaround. This slows down transfer rate to ~60 MB/s");
0585             svia_wd_fix(pdev);
0586             hpriv->wd_workaround = true;
0587             ap->link.eh_context.i.flags |= ATA_EHI_QUIET;
0588         }
0589     }
0590 
0591     ata_sff_error_handler(ap);
0592 }
0593 
0594 static void svia_configure(struct pci_dev *pdev, int board_id,
0595                struct svia_priv *hpriv)
0596 {
0597     u8 tmp8;
0598 
0599     pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
0600     dev_info(&pdev->dev, "routed to hard irq line %d\n",
0601          (int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f);
0602 
0603     /* make sure SATA channels are enabled */
0604     pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8);
0605     if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
0606         dev_dbg(&pdev->dev, "enabling SATA channels (0x%x)\n",
0607             (int)tmp8);
0608         tmp8 |= ALL_PORTS;
0609         pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
0610     }
0611 
0612     /* make sure interrupts for each channel sent to us */
0613     pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8);
0614     if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
0615         dev_dbg(&pdev->dev, "enabling SATA channel interrupts (0x%x)\n",
0616             (int) tmp8);
0617         tmp8 |= ALL_PORTS;
0618         pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
0619     }
0620 
0621     /* make sure native mode is enabled */
0622     pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8);
0623     if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
0624         dev_dbg(&pdev->dev,
0625             "enabling SATA channel native mode (0x%x)\n",
0626             (int) tmp8);
0627         tmp8 |= NATIVE_MODE_ALL;
0628         pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
0629     }
0630 
0631     if ((board_id == vt6420 && vt6420_hotplug) || board_id == vt6421) {
0632         /* enable IRQ on hotplug */
0633         pci_read_config_byte(pdev, SVIA_MISC_3, &tmp8);
0634         if ((tmp8 & SATA_HOTPLUG) != SATA_HOTPLUG) {
0635             dev_dbg(&pdev->dev,
0636                 "enabling SATA hotplug (0x%x)\n",
0637                 (int) tmp8);
0638             tmp8 |= SATA_HOTPLUG;
0639             pci_write_config_byte(pdev, SVIA_MISC_3, tmp8);
0640         }
0641     }
0642 
0643     /*
0644      * vt6420/1 has problems talking to some drives.  The following
0645      * is the fix from Joseph Chan <JosephChan@via.com.tw>.
0646      *
0647      * When host issues HOLD, device may send up to 20DW of data
0648      * before acknowledging it with HOLDA and the host should be
0649      * able to buffer them in FIFO.  Unfortunately, some WD drives
0650      * send up to 40DW before acknowledging HOLD and, in the
0651      * default configuration, this ends up overflowing vt6421's
0652      * FIFO, making the controller abort the transaction with
0653      * R_ERR.
0654      *
0655      * Rx52[2] is the internal 128DW FIFO Flow control watermark
0656      * adjusting mechanism enable bit and the default value 0
0657      * means host will issue HOLD to device when the left FIFO
0658      * size goes below 32DW.  Setting it to 1 makes the watermark
0659      * 64DW.
0660      *
0661      * https://bugzilla.kernel.org/show_bug.cgi?id=15173
0662      * http://article.gmane.org/gmane.linux.ide/46352
0663      * http://thread.gmane.org/gmane.linux.kernel/1062139
0664      *
0665      * As the fix slows down data transfer, apply it only if the error
0666      * actually appears - see vt6421_error_handler()
0667      * Apply the fix always on vt6420 as we don't know if SCR_ERROR can be
0668      * read safely.
0669      */
0670     if (board_id == vt6420) {
0671         svia_wd_fix(pdev);
0672         hpriv->wd_workaround = true;
0673     }
0674 }
0675 
0676 static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
0677 {
0678     unsigned int i;
0679     int rc;
0680     struct ata_host *host = NULL;
0681     int board_id = (int) ent->driver_data;
0682     const unsigned *bar_sizes;
0683     struct svia_priv *hpriv;
0684 
0685     ata_print_version_once(&pdev->dev, DRV_VERSION);
0686 
0687     rc = pcim_enable_device(pdev);
0688     if (rc)
0689         return rc;
0690 
0691     if (board_id == vt6421)
0692         bar_sizes = &vt6421_bar_sizes[0];
0693     else
0694         bar_sizes = &svia_bar_sizes[0];
0695 
0696     for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++)
0697         if ((pci_resource_start(pdev, i) == 0) ||
0698             (pci_resource_len(pdev, i) < bar_sizes[i])) {
0699             dev_err(&pdev->dev,
0700                 "invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
0701                 i,
0702                 (unsigned long long)pci_resource_start(pdev, i),
0703                 (unsigned long long)pci_resource_len(pdev, i));
0704             return -ENODEV;
0705         }
0706 
0707     switch (board_id) {
0708     case vt6420:
0709         rc = vt6420_prepare_host(pdev, &host);
0710         break;
0711     case vt6421:
0712         rc = vt6421_prepare_host(pdev, &host);
0713         break;
0714     case vt8251:
0715         rc = vt8251_prepare_host(pdev, &host);
0716         break;
0717     default:
0718         rc = -EINVAL;
0719     }
0720     if (rc)
0721         return rc;
0722 
0723     hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
0724     if (!hpriv)
0725         return -ENOMEM;
0726     host->private_data = hpriv;
0727 
0728     svia_configure(pdev, board_id, hpriv);
0729 
0730     pci_set_master(pdev);
0731     if ((board_id == vt6420 && vt6420_hotplug) || board_id == vt6421)
0732         return ata_host_activate(host, pdev->irq, vt642x_interrupt,
0733                      IRQF_SHARED, &svia_sht);
0734     else
0735         return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
0736                      IRQF_SHARED, &svia_sht);
0737 }
0738 
0739 #ifdef CONFIG_PM_SLEEP
0740 static int svia_pci_device_resume(struct pci_dev *pdev)
0741 {
0742     struct ata_host *host = pci_get_drvdata(pdev);
0743     struct svia_priv *hpriv = host->private_data;
0744     int rc;
0745 
0746     rc = ata_pci_device_do_resume(pdev);
0747     if (rc)
0748         return rc;
0749 
0750     if (hpriv->wd_workaround)
0751         svia_wd_fix(pdev);
0752     ata_host_resume(host);
0753 
0754     return 0;
0755 }
0756 #endif
0757 
0758 module_pci_driver(svia_pci_driver);
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