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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  sata_sx4.c - Promise SATA
0004  *
0005  *  Maintained by:  Tejun Heo <tj@kernel.org>
0006  *              Please ALWAYS copy linux-ide@vger.kernel.org
0007  *          on emails.
0008  *
0009  *  Copyright 2003-2004 Red Hat, Inc.
0010  *
0011  *  libata documentation is available via 'make {ps|pdf}docs',
0012  *  as Documentation/driver-api/libata.rst
0013  *
0014  *  Hardware documentation available under NDA.
0015  */
0016 
0017 /*
0018     Theory of operation
0019     -------------------
0020 
0021     The SX4 (PDC20621) chip features a single Host DMA (HDMA) copy
0022     engine, DIMM memory, and four ATA engines (one per SATA port).
0023     Data is copied to/from DIMM memory by the HDMA engine, before
0024     handing off to one (or more) of the ATA engines.  The ATA
0025     engines operate solely on DIMM memory.
0026 
0027     The SX4 behaves like a PATA chip, with no SATA controls or
0028     knowledge whatsoever, leading to the presumption that
0029     PATA<->SATA bridges exist on SX4 boards, external to the
0030     PDC20621 chip itself.
0031 
0032     The chip is quite capable, supporting an XOR engine and linked
0033     hardware commands (permits a string to transactions to be
0034     submitted and waited-on as a single unit), and an optional
0035     microprocessor.
0036 
0037     The limiting factor is largely software.  This Linux driver was
0038     written to multiplex the single HDMA engine to copy disk
0039     transactions into a fixed DIMM memory space, from where an ATA
0040     engine takes over.  As a result, each WRITE looks like this:
0041 
0042         submit HDMA packet to hardware
0043         hardware copies data from system memory to DIMM
0044         hardware raises interrupt
0045 
0046         submit ATA packet to hardware
0047         hardware executes ATA WRITE command, w/ data in DIMM
0048         hardware raises interrupt
0049 
0050     and each READ looks like this:
0051 
0052         submit ATA packet to hardware
0053         hardware executes ATA READ command, w/ data in DIMM
0054         hardware raises interrupt
0055 
0056         submit HDMA packet to hardware
0057         hardware copies data from DIMM to system memory
0058         hardware raises interrupt
0059 
0060     This is a very slow, lock-step way of doing things that can
0061     certainly be improved by motivated kernel hackers.
0062 
0063  */
0064 
0065 #include <linux/kernel.h>
0066 #include <linux/module.h>
0067 #include <linux/pci.h>
0068 #include <linux/slab.h>
0069 #include <linux/blkdev.h>
0070 #include <linux/delay.h>
0071 #include <linux/interrupt.h>
0072 #include <linux/device.h>
0073 #include <scsi/scsi_host.h>
0074 #include <scsi/scsi_cmnd.h>
0075 #include <linux/libata.h>
0076 #include "sata_promise.h"
0077 
0078 #define DRV_NAME    "sata_sx4"
0079 #define DRV_VERSION "0.12"
0080 
0081 static int dimm_test;
0082 module_param(dimm_test, int, 0644);
0083 MODULE_PARM_DESC(dimm_test, "Enable DIMM test during startup (1 = enabled)");
0084 
0085 enum {
0086     PDC_MMIO_BAR        = 3,
0087     PDC_DIMM_BAR        = 4,
0088 
0089     PDC_PRD_TBL     = 0x44, /* Direct command DMA table addr */
0090 
0091     PDC_PKT_SUBMIT      = 0x40, /* Command packet pointer addr */
0092     PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
0093     PDC_INT_SEQMASK     = 0x40, /* Mask of asserted SEQ INTs */
0094     PDC_HDMA_CTLSTAT    = 0x12C, /* Host DMA control / status */
0095 
0096     PDC_CTLSTAT     = 0x60, /* IDEn control / status */
0097 
0098     PDC_20621_SEQCTL    = 0x400,
0099     PDC_20621_SEQMASK   = 0x480,
0100     PDC_20621_GENERAL_CTL   = 0x484,
0101     PDC_20621_PAGE_SIZE = (32 * 1024),
0102 
0103     /* chosen, not constant, values; we design our own DIMM mem map */
0104     PDC_20621_DIMM_WINDOW   = 0x0C, /* page# for 32K DIMM window */
0105     PDC_20621_DIMM_BASE = 0x00200000,
0106     PDC_20621_DIMM_DATA = (64 * 1024),
0107     PDC_DIMM_DATA_STEP  = (256 * 1024),
0108     PDC_DIMM_WINDOW_STEP    = (8 * 1024),
0109     PDC_DIMM_HOST_PRD   = (6 * 1024),
0110     PDC_DIMM_HOST_PKT   = (128 * 0),
0111     PDC_DIMM_HPKT_PRD   = (128 * 1),
0112     PDC_DIMM_ATA_PKT    = (128 * 2),
0113     PDC_DIMM_APKT_PRD   = (128 * 3),
0114     PDC_DIMM_HEADER_SZ  = PDC_DIMM_APKT_PRD + 128,
0115     PDC_PAGE_WINDOW     = 0x40,
0116     PDC_PAGE_DATA       = PDC_PAGE_WINDOW +
0117                   (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
0118     PDC_PAGE_SET        = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
0119 
0120     PDC_CHIP0_OFS       = 0xC0000, /* offset of chip #0 */
0121 
0122     PDC_20621_ERR_MASK  = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
0123                   (1<<23),
0124 
0125     board_20621     = 0,    /* FastTrak S150 SX4 */
0126 
0127     PDC_MASK_INT        = (1 << 10), /* HDMA/ATA mask int */
0128     PDC_RESET       = (1 << 11), /* HDMA/ATA reset */
0129     PDC_DMA_ENABLE      = (1 << 7),  /* DMA start/stop */
0130 
0131     PDC_MAX_HDMA        = 32,
0132     PDC_HDMA_Q_MASK     = (PDC_MAX_HDMA - 1),
0133 
0134     PDC_DIMM0_SPD_DEV_ADDRESS   = 0x50,
0135     PDC_DIMM1_SPD_DEV_ADDRESS   = 0x51,
0136     PDC_I2C_CONTROL         = 0x48,
0137     PDC_I2C_ADDR_DATA       = 0x4C,
0138     PDC_DIMM0_CONTROL       = 0x80,
0139     PDC_DIMM1_CONTROL       = 0x84,
0140     PDC_SDRAM_CONTROL       = 0x88,
0141     PDC_I2C_WRITE           = 0,        /* master -> slave */
0142     PDC_I2C_READ            = (1 << 6), /* master <- slave */
0143     PDC_I2C_START           = (1 << 7), /* start I2C proto */
0144     PDC_I2C_MASK_INT        = (1 << 5), /* mask I2C interrupt */
0145     PDC_I2C_COMPLETE        = (1 << 16),    /* I2C normal compl. */
0146     PDC_I2C_NO_ACK          = (1 << 20),    /* slave no-ack addr */
0147     PDC_DIMM_SPD_SUBADDRESS_START   = 0x00,
0148     PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
0149     PDC_DIMM_SPD_ROW_NUM        = 3,
0150     PDC_DIMM_SPD_COLUMN_NUM     = 4,
0151     PDC_DIMM_SPD_MODULE_ROW     = 5,
0152     PDC_DIMM_SPD_TYPE       = 11,
0153     PDC_DIMM_SPD_FRESH_RATE     = 12,
0154     PDC_DIMM_SPD_BANK_NUM       = 17,
0155     PDC_DIMM_SPD_CAS_LATENCY    = 18,
0156     PDC_DIMM_SPD_ATTRIBUTE      = 21,
0157     PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
0158     PDC_DIMM_SPD_ROW_ACTIVE_DELAY   = 28,
0159     PDC_DIMM_SPD_RAS_CAS_DELAY  = 29,
0160     PDC_DIMM_SPD_ACTIVE_PRECHARGE   = 30,
0161     PDC_DIMM_SPD_SYSTEM_FREQ    = 126,
0162     PDC_CTL_STATUS          = 0x08,
0163     PDC_DIMM_WINDOW_CTLR        = 0x0C,
0164     PDC_TIME_CONTROL        = 0x3C,
0165     PDC_TIME_PERIOD         = 0x40,
0166     PDC_TIME_COUNTER        = 0x44,
0167     PDC_GENERAL_CTLR        = 0x484,
0168     PCI_PLL_INIT            = 0x8A531824,
0169     PCI_X_TCOUNT            = 0xEE1E5CFF,
0170 
0171     /* PDC_TIME_CONTROL bits */
0172     PDC_TIMER_BUZZER        = (1 << 10),
0173     PDC_TIMER_MODE_PERIODIC     = 0,        /* bits 9:8 == 00 */
0174     PDC_TIMER_MODE_ONCE     = (1 << 8), /* bits 9:8 == 01 */
0175     PDC_TIMER_ENABLE        = (1 << 7),
0176     PDC_TIMER_MASK_INT      = (1 << 5),
0177     PDC_TIMER_SEQ_MASK      = 0x1f,     /* SEQ ID for timer */
0178     PDC_TIMER_DEFAULT       = PDC_TIMER_MODE_ONCE |
0179                       PDC_TIMER_ENABLE |
0180                       PDC_TIMER_MASK_INT,
0181 };
0182 
0183 #define ECC_ERASE_BUF_SZ (128 * 1024)
0184 
0185 struct pdc_port_priv {
0186     u8          dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
0187     u8          *pkt;
0188     dma_addr_t      pkt_dma;
0189 };
0190 
0191 struct pdc_host_priv {
0192     unsigned int        doing_hdma;
0193     unsigned int        hdma_prod;
0194     unsigned int        hdma_cons;
0195     struct {
0196         struct ata_queued_cmd *qc;
0197         unsigned int    seq;
0198         unsigned long   pkt_ofs;
0199     } hdma[32];
0200 };
0201 
0202 
0203 static int pdc_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
0204 static void pdc_error_handler(struct ata_port *ap);
0205 static void pdc_freeze(struct ata_port *ap);
0206 static void pdc_thaw(struct ata_port *ap);
0207 static int pdc_port_start(struct ata_port *ap);
0208 static enum ata_completion_errors pdc20621_qc_prep(struct ata_queued_cmd *qc);
0209 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
0210 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
0211 static unsigned int pdc20621_dimm_init(struct ata_host *host);
0212 static int pdc20621_detect_dimm(struct ata_host *host);
0213 static unsigned int pdc20621_i2c_read(struct ata_host *host,
0214                       u32 device, u32 subaddr, u32 *pdata);
0215 static int pdc20621_prog_dimm0(struct ata_host *host);
0216 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host);
0217 static void pdc20621_get_from_dimm(struct ata_host *host,
0218                    void *psource, u32 offset, u32 size);
0219 static void pdc20621_put_to_dimm(struct ata_host *host,
0220                  void *psource, u32 offset, u32 size);
0221 static void pdc20621_irq_clear(struct ata_port *ap);
0222 static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc);
0223 static int pdc_softreset(struct ata_link *link, unsigned int *class,
0224              unsigned long deadline);
0225 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
0226 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
0227 
0228 
0229 static struct scsi_host_template pdc_sata_sht = {
0230     ATA_BASE_SHT(DRV_NAME),
0231     .sg_tablesize       = LIBATA_MAX_PRD,
0232     .dma_boundary       = ATA_DMA_BOUNDARY,
0233 };
0234 
0235 /* TODO: inherit from base port_ops after converting to new EH */
0236 static struct ata_port_operations pdc_20621_ops = {
0237     .inherits       = &ata_sff_port_ops,
0238 
0239     .check_atapi_dma    = pdc_check_atapi_dma,
0240     .qc_prep        = pdc20621_qc_prep,
0241     .qc_issue       = pdc20621_qc_issue,
0242 
0243     .freeze         = pdc_freeze,
0244     .thaw           = pdc_thaw,
0245     .softreset      = pdc_softreset,
0246     .error_handler      = pdc_error_handler,
0247     .lost_interrupt     = ATA_OP_NULL,
0248     .post_internal_cmd  = pdc_post_internal_cmd,
0249 
0250     .port_start     = pdc_port_start,
0251 
0252     .sff_tf_load        = pdc_tf_load_mmio,
0253     .sff_exec_command   = pdc_exec_command_mmio,
0254     .sff_irq_clear      = pdc20621_irq_clear,
0255 };
0256 
0257 static const struct ata_port_info pdc_port_info[] = {
0258     /* board_20621 */
0259     {
0260         .flags      = ATA_FLAG_SATA | ATA_FLAG_NO_ATAPI |
0261                   ATA_FLAG_PIO_POLLING,
0262         .pio_mask   = ATA_PIO4,
0263         .mwdma_mask = ATA_MWDMA2,
0264         .udma_mask  = ATA_UDMA6,
0265         .port_ops   = &pdc_20621_ops,
0266     },
0267 
0268 };
0269 
0270 static const struct pci_device_id pdc_sata_pci_tbl[] = {
0271     { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
0272 
0273     { } /* terminate list */
0274 };
0275 
0276 static struct pci_driver pdc_sata_pci_driver = {
0277     .name           = DRV_NAME,
0278     .id_table       = pdc_sata_pci_tbl,
0279     .probe          = pdc_sata_init_one,
0280     .remove         = ata_pci_remove_one,
0281 };
0282 
0283 
0284 static int pdc_port_start(struct ata_port *ap)
0285 {
0286     struct device *dev = ap->host->dev;
0287     struct pdc_port_priv *pp;
0288 
0289     pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
0290     if (!pp)
0291         return -ENOMEM;
0292 
0293     pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
0294     if (!pp->pkt)
0295         return -ENOMEM;
0296 
0297     ap->private_data = pp;
0298 
0299     return 0;
0300 }
0301 
0302 static inline void pdc20621_ata_sg(u8 *buf, unsigned int portno,
0303                    unsigned int total_len)
0304 {
0305     u32 addr;
0306     unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
0307     __le32 *buf32 = (__le32 *) buf;
0308 
0309     /* output ATA packet S/G table */
0310     addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
0311            (PDC_DIMM_DATA_STEP * portno);
0312 
0313     buf32[dw] = cpu_to_le32(addr);
0314     buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
0315 }
0316 
0317 static inline void pdc20621_host_sg(u8 *buf, unsigned int portno,
0318                     unsigned int total_len)
0319 {
0320     u32 addr;
0321     unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
0322     __le32 *buf32 = (__le32 *) buf;
0323 
0324     /* output Host DMA packet S/G table */
0325     addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
0326            (PDC_DIMM_DATA_STEP * portno);
0327 
0328     buf32[dw] = cpu_to_le32(addr);
0329     buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
0330 }
0331 
0332 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
0333                         unsigned int devno, u8 *buf,
0334                         unsigned int portno)
0335 {
0336     unsigned int i, dw;
0337     __le32 *buf32 = (__le32 *) buf;
0338     u8 dev_reg;
0339 
0340     unsigned int dimm_sg = PDC_20621_DIMM_BASE +
0341                    (PDC_DIMM_WINDOW_STEP * portno) +
0342                    PDC_DIMM_APKT_PRD;
0343 
0344     i = PDC_DIMM_ATA_PKT;
0345 
0346     /*
0347      * Set up ATA packet
0348      */
0349     if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
0350         buf[i++] = PDC_PKT_READ;
0351     else if (tf->protocol == ATA_PROT_NODATA)
0352         buf[i++] = PDC_PKT_NODATA;
0353     else
0354         buf[i++] = 0;
0355     buf[i++] = 0;           /* reserved */
0356     buf[i++] = portno + 1;      /* seq. id */
0357     buf[i++] = 0xff;        /* delay seq. id */
0358 
0359     /* dimm dma S/G, and next-pkt */
0360     dw = i >> 2;
0361     if (tf->protocol == ATA_PROT_NODATA)
0362         buf32[dw] = 0;
0363     else
0364         buf32[dw] = cpu_to_le32(dimm_sg);
0365     buf32[dw + 1] = 0;
0366     i += 8;
0367 
0368     if (devno == 0)
0369         dev_reg = ATA_DEVICE_OBS;
0370     else
0371         dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
0372 
0373     /* select device */
0374     buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
0375     buf[i++] = dev_reg;
0376 
0377     /* device control register */
0378     buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
0379     buf[i++] = tf->ctl;
0380 
0381     return i;
0382 }
0383 
0384 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
0385                      unsigned int portno)
0386 {
0387     unsigned int dw;
0388     u32 tmp;
0389     __le32 *buf32 = (__le32 *) buf;
0390 
0391     unsigned int host_sg = PDC_20621_DIMM_BASE +
0392                    (PDC_DIMM_WINDOW_STEP * portno) +
0393                    PDC_DIMM_HOST_PRD;
0394     unsigned int dimm_sg = PDC_20621_DIMM_BASE +
0395                    (PDC_DIMM_WINDOW_STEP * portno) +
0396                    PDC_DIMM_HPKT_PRD;
0397 
0398     dw = PDC_DIMM_HOST_PKT >> 2;
0399 
0400     /*
0401      * Set up Host DMA packet
0402      */
0403     if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
0404         tmp = PDC_PKT_READ;
0405     else
0406         tmp = 0;
0407     tmp |= ((portno + 1 + 4) << 16);    /* seq. id */
0408     tmp |= (0xff << 24);            /* delay seq. id */
0409     buf32[dw + 0] = cpu_to_le32(tmp);
0410     buf32[dw + 1] = cpu_to_le32(host_sg);
0411     buf32[dw + 2] = cpu_to_le32(dimm_sg);
0412     buf32[dw + 3] = 0;
0413 }
0414 
0415 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
0416 {
0417     struct scatterlist *sg;
0418     struct ata_port *ap = qc->ap;
0419     struct pdc_port_priv *pp = ap->private_data;
0420     void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
0421     void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
0422     unsigned int portno = ap->port_no;
0423     unsigned int i, si, idx, total_len = 0, sgt_len;
0424     __le32 *buf = (__le32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
0425 
0426     WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
0427 
0428     /* hard-code chip #0 */
0429     mmio += PDC_CHIP0_OFS;
0430 
0431     /*
0432      * Build S/G table
0433      */
0434     idx = 0;
0435     for_each_sg(qc->sg, sg, qc->n_elem, si) {
0436         buf[idx++] = cpu_to_le32(sg_dma_address(sg));
0437         buf[idx++] = cpu_to_le32(sg_dma_len(sg));
0438         total_len += sg_dma_len(sg);
0439     }
0440     buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
0441     sgt_len = idx * 4;
0442 
0443     /*
0444      * Build ATA, host DMA packets
0445      */
0446     pdc20621_host_sg(&pp->dimm_buf[0], portno, total_len);
0447     pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
0448 
0449     pdc20621_ata_sg(&pp->dimm_buf[0], portno, total_len);
0450     i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
0451 
0452     if (qc->tf.flags & ATA_TFLAG_LBA48)
0453         i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
0454     else
0455         i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
0456 
0457     pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
0458 
0459     /* copy three S/G tables and two packets to DIMM MMIO window */
0460     memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
0461             &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
0462     memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
0463             PDC_DIMM_HOST_PRD,
0464             &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
0465 
0466     /* force host FIFO dump */
0467     writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
0468 
0469     readl(dimm_mmio);   /* MMIO PCI posting flush */
0470 
0471     ata_port_dbg(ap, "ata pkt buf ofs %u, prd size %u, mmio copied\n",
0472              i, sgt_len);
0473 }
0474 
0475 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
0476 {
0477     struct ata_port *ap = qc->ap;
0478     struct pdc_port_priv *pp = ap->private_data;
0479     void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
0480     void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
0481     unsigned int portno = ap->port_no;
0482     unsigned int i;
0483 
0484     /* hard-code chip #0 */
0485     mmio += PDC_CHIP0_OFS;
0486 
0487     i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
0488 
0489     if (qc->tf.flags & ATA_TFLAG_LBA48)
0490         i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
0491     else
0492         i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
0493 
0494     pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
0495 
0496     /* copy three S/G tables and two packets to DIMM MMIO window */
0497     memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
0498             &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
0499 
0500     /* force host FIFO dump */
0501     writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
0502 
0503     readl(dimm_mmio);   /* MMIO PCI posting flush */
0504 
0505     ata_port_dbg(ap, "ata pkt buf ofs %u, mmio copied\n", i);
0506 }
0507 
0508 static enum ata_completion_errors pdc20621_qc_prep(struct ata_queued_cmd *qc)
0509 {
0510     switch (qc->tf.protocol) {
0511     case ATA_PROT_DMA:
0512         pdc20621_dma_prep(qc);
0513         break;
0514     case ATA_PROT_NODATA:
0515         pdc20621_nodata_prep(qc);
0516         break;
0517     default:
0518         break;
0519     }
0520 
0521     return AC_ERR_OK;
0522 }
0523 
0524 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
0525                  unsigned int seq,
0526                  u32 pkt_ofs)
0527 {
0528     struct ata_port *ap = qc->ap;
0529     struct ata_host *host = ap->host;
0530     void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
0531 
0532     /* hard-code chip #0 */
0533     mmio += PDC_CHIP0_OFS;
0534 
0535     writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
0536     readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
0537 
0538     writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
0539     readl(mmio + PDC_HDMA_PKT_SUBMIT);  /* flush */
0540 }
0541 
0542 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
0543                 unsigned int seq,
0544                 u32 pkt_ofs)
0545 {
0546     struct ata_port *ap = qc->ap;
0547     struct pdc_host_priv *pp = ap->host->private_data;
0548     unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
0549 
0550     if (!pp->doing_hdma) {
0551         __pdc20621_push_hdma(qc, seq, pkt_ofs);
0552         pp->doing_hdma = 1;
0553         return;
0554     }
0555 
0556     pp->hdma[idx].qc = qc;
0557     pp->hdma[idx].seq = seq;
0558     pp->hdma[idx].pkt_ofs = pkt_ofs;
0559     pp->hdma_prod++;
0560 }
0561 
0562 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
0563 {
0564     struct ata_port *ap = qc->ap;
0565     struct pdc_host_priv *pp = ap->host->private_data;
0566     unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
0567 
0568     /* if nothing on queue, we're done */
0569     if (pp->hdma_prod == pp->hdma_cons) {
0570         pp->doing_hdma = 0;
0571         return;
0572     }
0573 
0574     __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
0575                  pp->hdma[idx].pkt_ofs);
0576     pp->hdma_cons++;
0577 }
0578 
0579 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
0580 {
0581     struct ata_port *ap = qc->ap;
0582     unsigned int port_no = ap->port_no;
0583     void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
0584 
0585     dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
0586     dimm_mmio += PDC_DIMM_HOST_PKT;
0587 
0588     ata_port_dbg(ap, "HDMA 0x%08X 0x%08X 0x%08X 0x%08X\n",
0589              readl(dimm_mmio), readl(dimm_mmio + 4),
0590              readl(dimm_mmio + 8), readl(dimm_mmio + 12));
0591 }
0592 
0593 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
0594 {
0595     struct ata_port *ap = qc->ap;
0596     struct ata_host *host = ap->host;
0597     unsigned int port_no = ap->port_no;
0598     void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
0599     unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
0600     u8 seq = (u8) (port_no + 1);
0601     unsigned int port_ofs;
0602 
0603     /* hard-code chip #0 */
0604     mmio += PDC_CHIP0_OFS;
0605 
0606     wmb();          /* flush PRD, pkt writes */
0607 
0608     port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
0609 
0610     /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
0611     if (rw && qc->tf.protocol == ATA_PROT_DMA) {
0612         seq += 4;
0613 
0614         pdc20621_dump_hdma(qc);
0615         pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
0616         ata_port_dbg(ap, "queued ofs 0x%x (%u), seq %u\n",
0617             port_ofs + PDC_DIMM_HOST_PKT,
0618             port_ofs + PDC_DIMM_HOST_PKT,
0619             seq);
0620     } else {
0621         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
0622         readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
0623 
0624         writel(port_ofs + PDC_DIMM_ATA_PKT,
0625                ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
0626         readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
0627         ata_port_dbg(ap, "submitted ofs 0x%x (%u), seq %u\n",
0628             port_ofs + PDC_DIMM_ATA_PKT,
0629             port_ofs + PDC_DIMM_ATA_PKT,
0630             seq);
0631     }
0632 }
0633 
0634 static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc)
0635 {
0636     switch (qc->tf.protocol) {
0637     case ATA_PROT_NODATA:
0638         if (qc->tf.flags & ATA_TFLAG_POLLING)
0639             break;
0640         fallthrough;
0641     case ATA_PROT_DMA:
0642         pdc20621_packet_start(qc);
0643         return 0;
0644 
0645     case ATAPI_PROT_DMA:
0646         BUG();
0647         break;
0648 
0649     default:
0650         break;
0651     }
0652 
0653     return ata_sff_qc_issue(qc);
0654 }
0655 
0656 static inline unsigned int pdc20621_host_intr(struct ata_port *ap,
0657                       struct ata_queued_cmd *qc,
0658                       unsigned int doing_hdma,
0659                       void __iomem *mmio)
0660 {
0661     unsigned int port_no = ap->port_no;
0662     unsigned int port_ofs =
0663         PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
0664     u8 status;
0665     unsigned int handled = 0;
0666 
0667     if ((qc->tf.protocol == ATA_PROT_DMA) &&    /* read */
0668         (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
0669 
0670         /* step two - DMA from DIMM to host */
0671         if (doing_hdma) {
0672             ata_port_dbg(ap, "read hdma, 0x%x 0x%x\n",
0673                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
0674             /* get drive status; clear intr; complete txn */
0675             qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
0676             ata_qc_complete(qc);
0677             pdc20621_pop_hdma(qc);
0678         }
0679 
0680         /* step one - exec ATA command */
0681         else {
0682             u8 seq = (u8) (port_no + 1 + 4);
0683             ata_port_dbg(ap, "read ata, 0x%x 0x%x\n",
0684                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
0685 
0686             /* submit hdma pkt */
0687             pdc20621_dump_hdma(qc);
0688             pdc20621_push_hdma(qc, seq,
0689                        port_ofs + PDC_DIMM_HOST_PKT);
0690         }
0691         handled = 1;
0692 
0693     } else if (qc->tf.protocol == ATA_PROT_DMA) {   /* write */
0694 
0695         /* step one - DMA from host to DIMM */
0696         if (doing_hdma) {
0697             u8 seq = (u8) (port_no + 1);
0698             ata_port_dbg(ap, "write hdma, 0x%x 0x%x\n",
0699                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
0700 
0701             /* submit ata pkt */
0702             writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
0703             readl(mmio + PDC_20621_SEQCTL + (seq * 4));
0704             writel(port_ofs + PDC_DIMM_ATA_PKT,
0705                    ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
0706             readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
0707         }
0708 
0709         /* step two - execute ATA command */
0710         else {
0711             ata_port_dbg(ap, "write ata, 0x%x 0x%x\n",
0712                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
0713             /* get drive status; clear intr; complete txn */
0714             qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
0715             ata_qc_complete(qc);
0716             pdc20621_pop_hdma(qc);
0717         }
0718         handled = 1;
0719 
0720     /* command completion, but no data xfer */
0721     } else if (qc->tf.protocol == ATA_PROT_NODATA) {
0722 
0723         status = ata_sff_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
0724         ata_port_dbg(ap, "BUS_NODATA (drv_stat 0x%X)\n", status);
0725         qc->err_mask |= ac_err_mask(status);
0726         ata_qc_complete(qc);
0727         handled = 1;
0728 
0729     } else {
0730         ap->stats.idle_irq++;
0731     }
0732 
0733     return handled;
0734 }
0735 
0736 static void pdc20621_irq_clear(struct ata_port *ap)
0737 {
0738     ioread8(ap->ioaddr.status_addr);
0739 }
0740 
0741 static irqreturn_t pdc20621_interrupt(int irq, void *dev_instance)
0742 {
0743     struct ata_host *host = dev_instance;
0744     struct ata_port *ap;
0745     u32 mask = 0;
0746     unsigned int i, tmp, port_no;
0747     unsigned int handled = 0;
0748     void __iomem *mmio_base;
0749 
0750     if (!host || !host->iomap[PDC_MMIO_BAR])
0751         return IRQ_NONE;
0752 
0753     mmio_base = host->iomap[PDC_MMIO_BAR];
0754 
0755     /* reading should also clear interrupts */
0756     mmio_base += PDC_CHIP0_OFS;
0757     mask = readl(mmio_base + PDC_20621_SEQMASK);
0758 
0759     if (mask == 0xffffffff)
0760         return IRQ_NONE;
0761 
0762     mask &= 0xffff;     /* only 16 tags possible */
0763     if (!mask)
0764         return IRQ_NONE;
0765 
0766     spin_lock(&host->lock);
0767 
0768     for (i = 1; i < 9; i++) {
0769         port_no = i - 1;
0770         if (port_no > 3)
0771             port_no -= 4;
0772         if (port_no >= host->n_ports)
0773             ap = NULL;
0774         else
0775             ap = host->ports[port_no];
0776         tmp = mask & (1 << i);
0777         if (ap)
0778             ata_port_dbg(ap, "seq %u, tmp %x\n", i, tmp);
0779         if (tmp && ap) {
0780             struct ata_queued_cmd *qc;
0781 
0782             qc = ata_qc_from_tag(ap, ap->link.active_tag);
0783             if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
0784                 handled += pdc20621_host_intr(ap, qc, (i > 4),
0785                                   mmio_base);
0786         }
0787     }
0788 
0789     spin_unlock(&host->lock);
0790 
0791     return IRQ_RETVAL(handled);
0792 }
0793 
0794 static void pdc_freeze(struct ata_port *ap)
0795 {
0796     void __iomem *mmio = ap->ioaddr.cmd_addr;
0797     u32 tmp;
0798 
0799     /* FIXME: if all 4 ATA engines are stopped, also stop HDMA engine */
0800 
0801     tmp = readl(mmio + PDC_CTLSTAT);
0802     tmp |= PDC_MASK_INT;
0803     tmp &= ~PDC_DMA_ENABLE;
0804     writel(tmp, mmio + PDC_CTLSTAT);
0805     readl(mmio + PDC_CTLSTAT); /* flush */
0806 }
0807 
0808 static void pdc_thaw(struct ata_port *ap)
0809 {
0810     void __iomem *mmio = ap->ioaddr.cmd_addr;
0811     u32 tmp;
0812 
0813     /* FIXME: start HDMA engine, if zero ATA engines running */
0814 
0815     /* clear IRQ */
0816     ioread8(ap->ioaddr.status_addr);
0817 
0818     /* turn IRQ back on */
0819     tmp = readl(mmio + PDC_CTLSTAT);
0820     tmp &= ~PDC_MASK_INT;
0821     writel(tmp, mmio + PDC_CTLSTAT);
0822     readl(mmio + PDC_CTLSTAT); /* flush */
0823 }
0824 
0825 static void pdc_reset_port(struct ata_port *ap)
0826 {
0827     void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
0828     unsigned int i;
0829     u32 tmp;
0830 
0831     /* FIXME: handle HDMA copy engine */
0832 
0833     for (i = 11; i > 0; i--) {
0834         tmp = readl(mmio);
0835         if (tmp & PDC_RESET)
0836             break;
0837 
0838         udelay(100);
0839 
0840         tmp |= PDC_RESET;
0841         writel(tmp, mmio);
0842     }
0843 
0844     tmp &= ~PDC_RESET;
0845     writel(tmp, mmio);
0846     readl(mmio);    /* flush */
0847 }
0848 
0849 static int pdc_softreset(struct ata_link *link, unsigned int *class,
0850              unsigned long deadline)
0851 {
0852     pdc_reset_port(link->ap);
0853     return ata_sff_softreset(link, class, deadline);
0854 }
0855 
0856 static void pdc_error_handler(struct ata_port *ap)
0857 {
0858     if (!(ap->pflags & ATA_PFLAG_FROZEN))
0859         pdc_reset_port(ap);
0860 
0861     ata_sff_error_handler(ap);
0862 }
0863 
0864 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
0865 {
0866     struct ata_port *ap = qc->ap;
0867 
0868     /* make DMA engine forget about the failed command */
0869     if (qc->flags & ATA_QCFLAG_FAILED)
0870         pdc_reset_port(ap);
0871 }
0872 
0873 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
0874 {
0875     u8 *scsicmd = qc->scsicmd->cmnd;
0876     int pio = 1; /* atapi dma off by default */
0877 
0878     /* Whitelist commands that may use DMA. */
0879     switch (scsicmd[0]) {
0880     case WRITE_12:
0881     case WRITE_10:
0882     case WRITE_6:
0883     case READ_12:
0884     case READ_10:
0885     case READ_6:
0886     case 0xad: /* READ_DVD_STRUCTURE */
0887     case 0xbe: /* READ_CD */
0888         pio = 0;
0889     }
0890     /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
0891     if (scsicmd[0] == WRITE_10) {
0892         unsigned int lba =
0893             (scsicmd[2] << 24) |
0894             (scsicmd[3] << 16) |
0895             (scsicmd[4] << 8) |
0896             scsicmd[5];
0897         if (lba >= 0xFFFF4FA2)
0898             pio = 1;
0899     }
0900     return pio;
0901 }
0902 
0903 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
0904 {
0905     WARN_ON(tf->protocol == ATA_PROT_DMA ||
0906         tf->protocol == ATAPI_PROT_DMA);
0907     ata_sff_tf_load(ap, tf);
0908 }
0909 
0910 
0911 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
0912 {
0913     WARN_ON(tf->protocol == ATA_PROT_DMA ||
0914         tf->protocol == ATAPI_PROT_DMA);
0915     ata_sff_exec_command(ap, tf);
0916 }
0917 
0918 
0919 static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
0920 {
0921     port->cmd_addr      = base;
0922     port->data_addr     = base;
0923     port->feature_addr  =
0924     port->error_addr    = base + 0x4;
0925     port->nsect_addr    = base + 0x8;
0926     port->lbal_addr     = base + 0xc;
0927     port->lbam_addr     = base + 0x10;
0928     port->lbah_addr     = base + 0x14;
0929     port->device_addr   = base + 0x18;
0930     port->command_addr  =
0931     port->status_addr   = base + 0x1c;
0932     port->altstatus_addr    =
0933     port->ctl_addr      = base + 0x38;
0934 }
0935 
0936 
0937 static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
0938                    u32 offset, u32 size)
0939 {
0940     u32 window_size;
0941     u16 idx;
0942     u8 page_mask;
0943     long dist;
0944     void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
0945     void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
0946 
0947     /* hard-code chip #0 */
0948     mmio += PDC_CHIP0_OFS;
0949 
0950     page_mask = 0x00;
0951     window_size = 0x2000 * 4; /* 32K byte uchar size */
0952     idx = (u16) (offset / window_size);
0953 
0954     writel(0x01, mmio + PDC_GENERAL_CTLR);
0955     readl(mmio + PDC_GENERAL_CTLR);
0956     writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
0957     readl(mmio + PDC_DIMM_WINDOW_CTLR);
0958 
0959     offset -= (idx * window_size);
0960     idx++;
0961     dist = ((long) (window_size - (offset + size))) >= 0 ? size :
0962         (long) (window_size - offset);
0963     memcpy_fromio(psource, dimm_mmio + offset / 4, dist);
0964 
0965     psource += dist;
0966     size -= dist;
0967     for (; (long) size >= (long) window_size ;) {
0968         writel(0x01, mmio + PDC_GENERAL_CTLR);
0969         readl(mmio + PDC_GENERAL_CTLR);
0970         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
0971         readl(mmio + PDC_DIMM_WINDOW_CTLR);
0972         memcpy_fromio(psource, dimm_mmio, window_size / 4);
0973         psource += window_size;
0974         size -= window_size;
0975         idx++;
0976     }
0977 
0978     if (size) {
0979         writel(0x01, mmio + PDC_GENERAL_CTLR);
0980         readl(mmio + PDC_GENERAL_CTLR);
0981         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
0982         readl(mmio + PDC_DIMM_WINDOW_CTLR);
0983         memcpy_fromio(psource, dimm_mmio, size / 4);
0984     }
0985 }
0986 
0987 
0988 static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
0989                  u32 offset, u32 size)
0990 {
0991     u32 window_size;
0992     u16 idx;
0993     u8 page_mask;
0994     long dist;
0995     void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
0996     void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
0997 
0998     /* hard-code chip #0 */
0999     mmio += PDC_CHIP0_OFS;
1000 
1001     page_mask = 0x00;
1002     window_size = 0x2000 * 4;       /* 32K byte uchar size */
1003     idx = (u16) (offset / window_size);
1004 
1005     writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1006     readl(mmio + PDC_DIMM_WINDOW_CTLR);
1007     offset -= (idx * window_size);
1008     idx++;
1009     dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1010         (long) (window_size - offset);
1011     memcpy_toio(dimm_mmio + offset / 4, psource, dist);
1012     writel(0x01, mmio + PDC_GENERAL_CTLR);
1013     readl(mmio + PDC_GENERAL_CTLR);
1014 
1015     psource += dist;
1016     size -= dist;
1017     for (; (long) size >= (long) window_size ;) {
1018         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1019         readl(mmio + PDC_DIMM_WINDOW_CTLR);
1020         memcpy_toio(dimm_mmio, psource, window_size / 4);
1021         writel(0x01, mmio + PDC_GENERAL_CTLR);
1022         readl(mmio + PDC_GENERAL_CTLR);
1023         psource += window_size;
1024         size -= window_size;
1025         idx++;
1026     }
1027 
1028     if (size) {
1029         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1030         readl(mmio + PDC_DIMM_WINDOW_CTLR);
1031         memcpy_toio(dimm_mmio, psource, size / 4);
1032         writel(0x01, mmio + PDC_GENERAL_CTLR);
1033         readl(mmio + PDC_GENERAL_CTLR);
1034     }
1035 }
1036 
1037 
1038 static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
1039                       u32 subaddr, u32 *pdata)
1040 {
1041     void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1042     u32 i2creg  = 0;
1043     u32 status;
1044     u32 count = 0;
1045 
1046     /* hard-code chip #0 */
1047     mmio += PDC_CHIP0_OFS;
1048 
1049     i2creg |= device << 24;
1050     i2creg |= subaddr << 16;
1051 
1052     /* Set the device and subaddress */
1053     writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
1054     readl(mmio + PDC_I2C_ADDR_DATA);
1055 
1056     /* Write Control to perform read operation, mask int */
1057     writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1058            mmio + PDC_I2C_CONTROL);
1059 
1060     for (count = 0; count <= 1000; count ++) {
1061         status = readl(mmio + PDC_I2C_CONTROL);
1062         if (status & PDC_I2C_COMPLETE) {
1063             status = readl(mmio + PDC_I2C_ADDR_DATA);
1064             break;
1065         } else if (count == 1000)
1066             return 0;
1067     }
1068 
1069     *pdata = (status >> 8) & 0x000000ff;
1070     return 1;
1071 }
1072 
1073 
1074 static int pdc20621_detect_dimm(struct ata_host *host)
1075 {
1076     u32 data = 0;
1077     if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1078                  PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1079         if (data == 100)
1080             return 100;
1081     } else
1082         return 0;
1083 
1084     if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1085         if (data <= 0x75)
1086             return 133;
1087     } else
1088         return 0;
1089 
1090     return 0;
1091 }
1092 
1093 
1094 static int pdc20621_prog_dimm0(struct ata_host *host)
1095 {
1096     u32 spd0[50];
1097     u32 data = 0;
1098     int size, i;
1099     u8 bdimmsize;
1100     void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1101     static const struct {
1102         unsigned int reg;
1103         unsigned int ofs;
1104     } pdc_i2c_read_data [] = {
1105         { PDC_DIMM_SPD_TYPE, 11 },
1106         { PDC_DIMM_SPD_FRESH_RATE, 12 },
1107         { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1108         { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1109         { PDC_DIMM_SPD_ROW_NUM, 3 },
1110         { PDC_DIMM_SPD_BANK_NUM, 17 },
1111         { PDC_DIMM_SPD_MODULE_ROW, 5 },
1112         { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1113         { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1114         { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1115         { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1116         { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1117     };
1118 
1119     /* hard-code chip #0 */
1120     mmio += PDC_CHIP0_OFS;
1121 
1122     for (i = 0; i < ARRAY_SIZE(pdc_i2c_read_data); i++)
1123         pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1124                   pdc_i2c_read_data[i].reg,
1125                   &spd0[pdc_i2c_read_data[i].ofs]);
1126 
1127     data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1128     data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1129         ((((spd0[27] + 9) / 10) - 1) << 8) ;
1130     data |= (((((spd0[29] > spd0[28])
1131             ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1132     data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1133 
1134     if (spd0[18] & 0x08)
1135         data |= ((0x03) << 14);
1136     else if (spd0[18] & 0x04)
1137         data |= ((0x02) << 14);
1138     else if (spd0[18] & 0x01)
1139         data |= ((0x01) << 14);
1140     else
1141         data |= (0 << 14);
1142 
1143     /*
1144        Calculate the size of bDIMMSize (power of 2) and
1145        merge the DIMM size by program start/end address.
1146     */
1147 
1148     bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1149     size = (1 << bdimmsize) >> 20;  /* size = xxx(MB) */
1150     data |= (((size / 16) - 1) << 16);
1151     data |= (0 << 23);
1152     data |= 8;
1153     writel(data, mmio + PDC_DIMM0_CONTROL);
1154     readl(mmio + PDC_DIMM0_CONTROL);
1155     return size;
1156 }
1157 
1158 
1159 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
1160 {
1161     u32 data, spd0;
1162     int error, i;
1163     void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1164 
1165     /* hard-code chip #0 */
1166     mmio += PDC_CHIP0_OFS;
1167 
1168     /*
1169       Set To Default : DIMM Module Global Control Register (0x022259F1)
1170       DIMM Arbitration Disable (bit 20)
1171       DIMM Data/Control Output Driving Selection (bit12 - bit15)
1172       Refresh Enable (bit 17)
1173     */
1174 
1175     data = 0x022259F1;
1176     writel(data, mmio + PDC_SDRAM_CONTROL);
1177     readl(mmio + PDC_SDRAM_CONTROL);
1178 
1179     /* Turn on for ECC */
1180     if (!pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1181                    PDC_DIMM_SPD_TYPE, &spd0)) {
1182         dev_err(host->dev,
1183             "Failed in i2c read: device=%#x, subaddr=%#x\n",
1184             PDC_DIMM0_SPD_DEV_ADDRESS, PDC_DIMM_SPD_TYPE);
1185         return 1;
1186     }
1187     if (spd0 == 0x02) {
1188         data |= (0x01 << 16);
1189         writel(data, mmio + PDC_SDRAM_CONTROL);
1190         readl(mmio + PDC_SDRAM_CONTROL);
1191         dev_err(host->dev, "Local DIMM ECC Enabled\n");
1192     }
1193 
1194     /* DIMM Initialization Select/Enable (bit 18/19) */
1195     data &= (~(1<<18));
1196     data |= (1<<19);
1197     writel(data, mmio + PDC_SDRAM_CONTROL);
1198 
1199     error = 1;
1200     for (i = 1; i <= 10; i++) {   /* polling ~5 secs */
1201         data = readl(mmio + PDC_SDRAM_CONTROL);
1202         if (!(data & (1<<19))) {
1203             error = 0;
1204             break;
1205         }
1206         msleep(i*100);
1207     }
1208     return error;
1209 }
1210 
1211 
1212 static unsigned int pdc20621_dimm_init(struct ata_host *host)
1213 {
1214     int speed, size, length;
1215     u32 addr, spd0, pci_status;
1216     u32 time_period = 0;
1217     u32 tcount = 0;
1218     u32 ticks = 0;
1219     u32 clock = 0;
1220     u32 fparam = 0;
1221     void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1222 
1223     /* hard-code chip #0 */
1224     mmio += PDC_CHIP0_OFS;
1225 
1226     /* Initialize PLL based upon PCI Bus Frequency */
1227 
1228     /* Initialize Time Period Register */
1229     writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1230     time_period = readl(mmio + PDC_TIME_PERIOD);
1231     dev_dbg(host->dev, "Time Period Register (0x40): 0x%x\n", time_period);
1232 
1233     /* Enable timer */
1234     writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
1235     readl(mmio + PDC_TIME_CONTROL);
1236 
1237     /* Wait 3 seconds */
1238     msleep(3000);
1239 
1240     /*
1241        When timer is enabled, counter is decreased every internal
1242        clock cycle.
1243     */
1244 
1245     tcount = readl(mmio + PDC_TIME_COUNTER);
1246     dev_dbg(host->dev, "Time Counter Register (0x44): 0x%x\n", tcount);
1247 
1248     /*
1249        If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1250        register should be >= (0xffffffff - 3x10^8).
1251     */
1252     if (tcount >= PCI_X_TCOUNT) {
1253         ticks = (time_period - tcount);
1254         dev_dbg(host->dev, "Num counters 0x%x (%d)\n", ticks, ticks);
1255 
1256         clock = (ticks / 300000);
1257         dev_dbg(host->dev, "10 * Internal clk = 0x%x (%d)\n",
1258             clock, clock);
1259 
1260         clock = (clock * 33);
1261         dev_dbg(host->dev, "10 * Internal clk * 33 = 0x%x (%d)\n",
1262             clock, clock);
1263 
1264         /* PLL F Param (bit 22:16) */
1265         fparam = (1400000 / clock) - 2;
1266         dev_dbg(host->dev, "PLL F Param: 0x%x (%d)\n", fparam, fparam);
1267 
1268         /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1269         pci_status = (0x8a001824 | (fparam << 16));
1270     } else
1271         pci_status = PCI_PLL_INIT;
1272 
1273     /* Initialize PLL. */
1274     dev_dbg(host->dev, "pci_status: 0x%x\n", pci_status);
1275     writel(pci_status, mmio + PDC_CTL_STATUS);
1276     readl(mmio + PDC_CTL_STATUS);
1277 
1278     /*
1279        Read SPD of DIMM by I2C interface,
1280        and program the DIMM Module Controller.
1281     */
1282     if (!(speed = pdc20621_detect_dimm(host))) {
1283         dev_err(host->dev, "Detect Local DIMM Fail\n");
1284         return 1;   /* DIMM error */
1285     }
1286     dev_dbg(host->dev, "Local DIMM Speed = %d\n", speed);
1287 
1288     /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1289     size = pdc20621_prog_dimm0(host);
1290     dev_dbg(host->dev, "Local DIMM Size = %dMB\n", size);
1291 
1292     /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1293     if (pdc20621_prog_dimm_global(host)) {
1294         dev_err(host->dev,
1295             "Programming DIMM Module Global Control Register Fail\n");
1296         return 1;
1297     }
1298 
1299     if (dimm_test) {
1300         u8 test_parttern1[40] =
1301             {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1302             'N','o','t',' ','Y','e','t',' ',
1303             'D','e','f','i','n','e','d',' ',
1304             '1','.','1','0',
1305             '9','8','0','3','1','6','1','2',0,0};
1306         u8 test_parttern2[40] = {0};
1307 
1308         pdc20621_put_to_dimm(host, test_parttern2, 0x10040, 40);
1309         pdc20621_put_to_dimm(host, test_parttern2, 0x40, 40);
1310 
1311         pdc20621_put_to_dimm(host, test_parttern1, 0x10040, 40);
1312         pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
1313         dev_info(host->dev, "DIMM test pattern 1: %x, %x, %s\n", test_parttern2[0],
1314                test_parttern2[1], &(test_parttern2[2]));
1315         pdc20621_get_from_dimm(host, test_parttern2, 0x10040,
1316                        40);
1317         dev_info(host->dev, "DIMM test pattern 2: %x, %x, %s\n",
1318              test_parttern2[0],
1319              test_parttern2[1], &(test_parttern2[2]));
1320 
1321         pdc20621_put_to_dimm(host, test_parttern1, 0x40, 40);
1322         pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
1323         dev_info(host->dev, "DIMM test pattern 3: %x, %x, %s\n",
1324              test_parttern2[0],
1325              test_parttern2[1], &(test_parttern2[2]));
1326     }
1327 
1328     /* ECC initiliazation. */
1329 
1330     if (!pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1331                    PDC_DIMM_SPD_TYPE, &spd0)) {
1332         dev_err(host->dev,
1333             "Failed in i2c read: device=%#x, subaddr=%#x\n",
1334                PDC_DIMM0_SPD_DEV_ADDRESS, PDC_DIMM_SPD_TYPE);
1335         return 1;
1336     }
1337     if (spd0 == 0x02) {
1338         void *buf;
1339         dev_dbg(host->dev, "Start ECC initialization\n");
1340         addr = 0;
1341         length = size * 1024 * 1024;
1342         buf = kzalloc(ECC_ERASE_BUF_SZ, GFP_KERNEL);
1343         if (!buf)
1344             return 1;
1345         while (addr < length) {
1346             pdc20621_put_to_dimm(host, buf, addr,
1347                          ECC_ERASE_BUF_SZ);
1348             addr += ECC_ERASE_BUF_SZ;
1349         }
1350         kfree(buf);
1351         dev_dbg(host->dev, "Finish ECC initialization\n");
1352     }
1353     return 0;
1354 }
1355 
1356 
1357 static void pdc_20621_init(struct ata_host *host)
1358 {
1359     u32 tmp;
1360     void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1361 
1362     /* hard-code chip #0 */
1363     mmio += PDC_CHIP0_OFS;
1364 
1365     /*
1366      * Select page 0x40 for our 32k DIMM window
1367      */
1368     tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1369     tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1370     writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1371 
1372     /*
1373      * Reset Host DMA
1374      */
1375     tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1376     tmp |= PDC_RESET;
1377     writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1378     readl(mmio + PDC_HDMA_CTLSTAT);     /* flush */
1379 
1380     udelay(10);
1381 
1382     tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1383     tmp &= ~PDC_RESET;
1384     writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1385     readl(mmio + PDC_HDMA_CTLSTAT);     /* flush */
1386 }
1387 
1388 static int pdc_sata_init_one(struct pci_dev *pdev,
1389                  const struct pci_device_id *ent)
1390 {
1391     const struct ata_port_info *ppi[] =
1392         { &pdc_port_info[ent->driver_data], NULL };
1393     struct ata_host *host;
1394     struct pdc_host_priv *hpriv;
1395     int i, rc;
1396 
1397     ata_print_version_once(&pdev->dev, DRV_VERSION);
1398 
1399     /* allocate host */
1400     host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
1401     hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1402     if (!host || !hpriv)
1403         return -ENOMEM;
1404 
1405     host->private_data = hpriv;
1406 
1407     /* acquire resources and fill host */
1408     rc = pcim_enable_device(pdev);
1409     if (rc)
1410         return rc;
1411 
1412     rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR),
1413                 DRV_NAME);
1414     if (rc == -EBUSY)
1415         pcim_pin_device(pdev);
1416     if (rc)
1417         return rc;
1418     host->iomap = pcim_iomap_table(pdev);
1419 
1420     for (i = 0; i < 4; i++) {
1421         struct ata_port *ap = host->ports[i];
1422         void __iomem *base = host->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
1423         unsigned int offset = 0x200 + i * 0x80;
1424 
1425         pdc_sata_setup_port(&ap->ioaddr, base + offset);
1426 
1427         ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1428         ata_port_pbar_desc(ap, PDC_DIMM_BAR, -1, "dimm");
1429         ata_port_pbar_desc(ap, PDC_MMIO_BAR, offset, "port");
1430     }
1431 
1432     /* configure and activate */
1433     rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
1434     if (rc)
1435         return rc;
1436 
1437     if (pdc20621_dimm_init(host))
1438         return -ENOMEM;
1439     pdc_20621_init(host);
1440 
1441     pci_set_master(pdev);
1442     return ata_host_activate(host, pdev->irq, pdc20621_interrupt,
1443                  IRQF_SHARED, &pdc_sata_sht);
1444 }
1445 
1446 module_pci_driver(pdc_sata_pci_driver);
1447 
1448 MODULE_AUTHOR("Jeff Garzik");
1449 MODULE_DESCRIPTION("Promise SATA low-level driver");
1450 MODULE_LICENSE("GPL");
1451 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1452 MODULE_VERSION(DRV_VERSION);
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