drivers/ata/sata_svw.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  sata_svw.c - ServerWorks / Apple K2 SATA
0004  *
0005  *  Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
0006  *         Jeff Garzik <jgarzik@pobox.com>
0007  *              Please ALWAYS copy linux-ide@vger.kernel.org
0008  *          on emails.
0009  *
0010  *  Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
0011  *
0012  *  Bits from Jeff Garzik, Copyright RedHat, Inc.
0013  *
0014  *  This driver probably works with non-Apple versions of the
0015  *  Broadcom chipset...
0016  *
0017  *  libata documentation is available via 'make {ps|pdf}docs',
0018  *  as Documentation/driver-api/libata.rst
0019  *
0020  *  Hardware documentation available under NDA.
0021  */
0022
0023 #include <linux/kernel.h>
0024 #include <linux/module.h>
0025 #include <linux/pci.h>
0026 #include <linux/blkdev.h>
0027 #include <linux/delay.h>
0028 #include <linux/interrupt.h>
0029 #include <linux/device.h>
0030 #include <scsi/scsi_host.h>
0031 #include <scsi/scsi_cmnd.h>
0032 #include <scsi/scsi.h>
0033 #include <linux/libata.h>
0034 #include <linux/of.h>
0035
0036 #define DRV_NAME    "sata_svw"
0037 #define DRV_VERSION "2.3"
0038
0039 enum {
0040     /* ap->flags bits */
0041     K2_FLAG_SATA_8_PORTS        = (1 << 24),
0042     K2_FLAG_NO_ATAPI_DMA        = (1 << 25),
0043     K2_FLAG_BAR_POS_3           = (1 << 26),
0044
0045     /* Taskfile registers offsets */
0046     K2_SATA_TF_CMD_OFFSET       = 0x00,
0047     K2_SATA_TF_DATA_OFFSET      = 0x00,
0048     K2_SATA_TF_ERROR_OFFSET     = 0x04,
0049     K2_SATA_TF_NSECT_OFFSET     = 0x08,
0050     K2_SATA_TF_LBAL_OFFSET      = 0x0c,
0051     K2_SATA_TF_LBAM_OFFSET      = 0x10,
0052     K2_SATA_TF_LBAH_OFFSET      = 0x14,
0053     K2_SATA_TF_DEVICE_OFFSET    = 0x18,
0054     K2_SATA_TF_CMDSTAT_OFFSET       = 0x1c,
0055     K2_SATA_TF_CTL_OFFSET       = 0x20,
0056
0057     /* DMA base */
0058     K2_SATA_DMA_CMD_OFFSET      = 0x30,
0059
0060     /* SCRs base */
0061     K2_SATA_SCR_STATUS_OFFSET   = 0x40,
0062     K2_SATA_SCR_ERROR_OFFSET    = 0x44,
0063     K2_SATA_SCR_CONTROL_OFFSET  = 0x48,
0064
0065     /* Others */
0066     K2_SATA_SICR1_OFFSET        = 0x80,
0067     K2_SATA_SICR2_OFFSET        = 0x84,
0068     K2_SATA_SIM_OFFSET      = 0x88,
0069
0070     /* Port stride */
0071     K2_SATA_PORT_OFFSET     = 0x100,
0072
0073     chip_svw4           = 0,
0074     chip_svw8           = 1,
0075     chip_svw42          = 2,    /* bar 3 */
0076     chip_svw43          = 3,    /* bar 5 */
0077 };
0078
0079 static u8 k2_stat_check_status(struct ata_port *ap);
0080
0081
0082 static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
0083 {
0084     u8 cmnd = qc->scsicmd->cmnd[0];
0085
0086     if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
0087         return -1;  /* ATAPI DMA not supported */
0088     else {
0089         switch (cmnd) {
0090         case READ_10:
0091         case READ_12:
0092         case READ_16:
0093         case WRITE_10:
0094         case WRITE_12:
0095         case WRITE_16:
0096             return 0;
0097
0098         default:
0099             return -1;
0100         }
0101
0102     }
0103 }
0104
0105 static int k2_sata_scr_read(struct ata_link *link,
0106                 unsigned int sc_reg, u32 *val)
0107 {
0108     if (sc_reg > SCR_CONTROL)
0109         return -EINVAL;
0110     *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
0111     return 0;
0112 }
0113
0114
0115 static int k2_sata_scr_write(struct ata_link *link,
0116                  unsigned int sc_reg, u32 val)
0117 {
0118     if (sc_reg > SCR_CONTROL)
0119         return -EINVAL;
0120     writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
0121     return 0;
0122 }
0123
0124 static int k2_sata_softreset(struct ata_link *link,
0125                  unsigned int *class, unsigned long deadline)
0126 {
0127     u8 dmactl;
0128     void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
0129
0130     dmactl = readb(mmio + ATA_DMA_CMD);
0131
0132     /* Clear the start bit */
0133     if (dmactl & ATA_DMA_START) {
0134         dmactl &= ~ATA_DMA_START;
0135         writeb(dmactl, mmio + ATA_DMA_CMD);
0136     }
0137
0138     return ata_sff_softreset(link, class, deadline);
0139 }
0140
0141 static int k2_sata_hardreset(struct ata_link *link,
0142                  unsigned int *class, unsigned long deadline)
0143 {
0144     u8 dmactl;
0145     void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
0146
0147     dmactl = readb(mmio + ATA_DMA_CMD);
0148
0149     /* Clear the start bit */
0150     if (dmactl & ATA_DMA_START) {
0151         dmactl &= ~ATA_DMA_START;
0152         writeb(dmactl, mmio + ATA_DMA_CMD);
0153     }
0154
0155     return sata_sff_hardreset(link, class, deadline);
0156 }
0157
0158 static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
0159 {
0160     struct ata_ioports *ioaddr = &ap->ioaddr;
0161     unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
0162
0163     if (tf->ctl != ap->last_ctl) {
0164         writeb(tf->ctl, ioaddr->ctl_addr);
0165         ap->last_ctl = tf->ctl;
0166         ata_wait_idle(ap);
0167     }
0168     if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
0169         writew(tf->feature | (((u16)tf->hob_feature) << 8),
0170                ioaddr->feature_addr);
0171         writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
0172                ioaddr->nsect_addr);
0173         writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
0174                ioaddr->lbal_addr);
0175         writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
0176                ioaddr->lbam_addr);
0177         writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
0178                ioaddr->lbah_addr);
0179     } else if (is_addr) {
0180         writew(tf->feature, ioaddr->feature_addr);
0181         writew(tf->nsect, ioaddr->nsect_addr);
0182         writew(tf->lbal, ioaddr->lbal_addr);
0183         writew(tf->lbam, ioaddr->lbam_addr);
0184         writew(tf->lbah, ioaddr->lbah_addr);
0185     }
0186
0187     if (tf->flags & ATA_TFLAG_DEVICE)
0188         writeb(tf->device, ioaddr->device_addr);
0189
0190     ata_wait_idle(ap);
0191 }
0192
0193
0194 static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
0195 {
0196     struct ata_ioports *ioaddr = &ap->ioaddr;
0197     u16 nsect, lbal, lbam, lbah, error;
0198
0199     tf->status = k2_stat_check_status(ap);
0200     tf->device = readw(ioaddr->device_addr);
0201     error = readw(ioaddr->error_addr);
0202     nsect = readw(ioaddr->nsect_addr);
0203     lbal = readw(ioaddr->lbal_addr);
0204     lbam = readw(ioaddr->lbam_addr);
0205     lbah = readw(ioaddr->lbah_addr);
0206
0207     tf->error = error;
0208     tf->nsect = nsect;
0209     tf->lbal = lbal;
0210     tf->lbam = lbam;
0211     tf->lbah = lbah;
0212
0213     if (tf->flags & ATA_TFLAG_LBA48) {
0214         tf->hob_feature = error >> 8;
0215         tf->hob_nsect = nsect >> 8;
0216         tf->hob_lbal = lbal >> 8;
0217         tf->hob_lbam = lbam >> 8;
0218         tf->hob_lbah = lbah >> 8;
0219     }
0220 }
0221
0222 /**
0223  *  k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
0224  *  @qc: Info associated with this ATA transaction.
0225  *
0226  *  LOCKING:
0227  *  spin_lock_irqsave(host lock)
0228  */
0229
0230 static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
0231 {
0232     struct ata_port *ap = qc->ap;
0233     unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
0234     u8 dmactl;
0235     void __iomem *mmio = ap->ioaddr.bmdma_addr;
0236
0237     /* load PRD table addr. */
0238     mb();   /* make sure PRD table writes are visible to controller */
0239     writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
0240
0241     /* specify data direction, triple-check start bit is clear */
0242     dmactl = readb(mmio + ATA_DMA_CMD);
0243     dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
0244     if (!rw)
0245         dmactl |= ATA_DMA_WR;
0246     writeb(dmactl, mmio + ATA_DMA_CMD);
0247
0248     /* issue r/w command if this is not a ATA DMA command*/
0249     if (qc->tf.protocol != ATA_PROT_DMA)
0250         ap->ops->sff_exec_command(ap, &qc->tf);
0251 }
0252
0253 /**
0254  *  k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
0255  *  @qc: Info associated with this ATA transaction.
0256  *
0257  *  LOCKING:
0258  *  spin_lock_irqsave(host lock)
0259  */
0260
0261 static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
0262 {
0263     struct ata_port *ap = qc->ap;
0264     void __iomem *mmio = ap->ioaddr.bmdma_addr;
0265     u8 dmactl;
0266
0267     /* start host DMA transaction */
0268     dmactl = readb(mmio + ATA_DMA_CMD);
0269     writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
0270     /* This works around possible data corruption.
0271
0272        On certain SATA controllers that can be seen when the r/w
0273        command is given to the controller before the host DMA is
0274        started.
0275
0276        On a Read command, the controller would initiate the
0277        command to the drive even before it sees the DMA
0278        start. When there are very fast drives connected to the
0279        controller, or when the data request hits in the drive
0280        cache, there is the possibility that the drive returns a
0281        part or all of the requested data to the controller before
0282        the DMA start is issued.  In this case, the controller
0283        would become confused as to what to do with the data.  In
0284        the worst case when all the data is returned back to the
0285        controller, the controller could hang. In other cases it
0286        could return partial data returning in data
0287        corruption. This problem has been seen in PPC systems and
0288        can also appear on an system with very fast disks, where
0289        the SATA controller is sitting behind a number of bridges,
0290        and hence there is significant latency between the r/w
0291        command and the start command. */
0292     /* issue r/w command if the access is to ATA */
0293     if (qc->tf.protocol == ATA_PROT_DMA)
0294         ap->ops->sff_exec_command(ap, &qc->tf);
0295 }
0296
0297
0298 static u8 k2_stat_check_status(struct ata_port *ap)
0299 {
0300     return readl(ap->ioaddr.status_addr);
0301 }
0302
0303 static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost)
0304 {
0305     struct ata_port *ap;
0306     struct device_node *np;
0307     int index;
0308
0309     /* Find  the ata_port */
0310     ap = ata_shost_to_port(shost);
0311     if (ap == NULL)
0312         return 0;
0313
0314     /* Find the OF node for the PCI device proper */
0315     np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
0316     if (np == NULL)
0317         return 0;
0318
0319     /* Match it to a port node */
0320     index = (ap == ap->host->ports[0]) ? 0 : 1;
0321     for (np = np->child; np != NULL; np = np->sibling) {
0322         const u32 *reg = of_get_property(np, "reg", NULL);
0323         if (!reg)
0324             continue;
0325         if (index == *reg) {
0326             seq_printf(m, "devspec: %pOF\n", np);
0327             break;
0328         }
0329     }
0330     return 0;
0331 }
0332
0333 static struct scsi_host_template k2_sata_sht = {
0334     ATA_BMDMA_SHT(DRV_NAME),
0335     .show_info      = k2_sata_show_info,
0336 };
0337
0338
0339 static struct ata_port_operations k2_sata_ops = {
0340     .inherits       = &ata_bmdma_port_ops,
0341     .softreset              = k2_sata_softreset,
0342     .hardreset              = k2_sata_hardreset,
0343     .sff_tf_load        = k2_sata_tf_load,
0344     .sff_tf_read        = k2_sata_tf_read,
0345     .sff_check_status   = k2_stat_check_status,
0346     .check_atapi_dma    = k2_sata_check_atapi_dma,
0347     .bmdma_setup        = k2_bmdma_setup_mmio,
0348     .bmdma_start        = k2_bmdma_start_mmio,
0349     .scr_read       = k2_sata_scr_read,
0350     .scr_write      = k2_sata_scr_write,
0351 };
0352
0353 static const struct ata_port_info k2_port_info[] = {
0354     /* chip_svw4 */
0355     {
0356         .flags      = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA,
0357         .pio_mask   = ATA_PIO4,
0358         .mwdma_mask = ATA_MWDMA2,
0359         .udma_mask  = ATA_UDMA6,
0360         .port_ops   = &k2_sata_ops,
0361     },
0362     /* chip_svw8 */
0363     {
0364         .flags      = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA |
0365                   K2_FLAG_SATA_8_PORTS,
0366         .pio_mask   = ATA_PIO4,
0367         .mwdma_mask = ATA_MWDMA2,
0368         .udma_mask  = ATA_UDMA6,
0369         .port_ops   = &k2_sata_ops,
0370     },
0371     /* chip_svw42 */
0372     {
0373         .flags      = ATA_FLAG_SATA | K2_FLAG_BAR_POS_3,
0374         .pio_mask   = ATA_PIO4,
0375         .mwdma_mask = ATA_MWDMA2,
0376         .udma_mask  = ATA_UDMA6,
0377         .port_ops   = &k2_sata_ops,
0378     },
0379     /* chip_svw43 */
0380     {
0381         .flags      = ATA_FLAG_SATA,
0382         .pio_mask   = ATA_PIO4,
0383         .mwdma_mask = ATA_MWDMA2,
0384         .udma_mask  = ATA_UDMA6,
0385         .port_ops   = &k2_sata_ops,
0386     },
0387 };
0388
0389 static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
0390 {
0391     port->cmd_addr      = base + K2_SATA_TF_CMD_OFFSET;
0392     port->data_addr     = base + K2_SATA_TF_DATA_OFFSET;
0393     port->feature_addr  =
0394     port->error_addr    = base + K2_SATA_TF_ERROR_OFFSET;
0395     port->nsect_addr    = base + K2_SATA_TF_NSECT_OFFSET;
0396     port->lbal_addr     = base + K2_SATA_TF_LBAL_OFFSET;
0397     port->lbam_addr     = base + K2_SATA_TF_LBAM_OFFSET;
0398     port->lbah_addr     = base + K2_SATA_TF_LBAH_OFFSET;
0399     port->device_addr   = base + K2_SATA_TF_DEVICE_OFFSET;
0400     port->command_addr  =
0401     port->status_addr   = base + K2_SATA_TF_CMDSTAT_OFFSET;
0402     port->altstatus_addr    =
0403     port->ctl_addr      = base + K2_SATA_TF_CTL_OFFSET;
0404     port->bmdma_addr    = base + K2_SATA_DMA_CMD_OFFSET;
0405     port->scr_addr      = base + K2_SATA_SCR_STATUS_OFFSET;
0406 }
0407
0408
0409 static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
0410 {
0411     const struct ata_port_info *ppi[] =
0412         { &k2_port_info[ent->driver_data], NULL };
0413     struct ata_host *host;
0414     void __iomem *mmio_base;
0415     int n_ports, i, rc, bar_pos;
0416
0417     ata_print_version_once(&pdev->dev, DRV_VERSION);
0418
0419     /* allocate host */
0420     n_ports = 4;
0421     if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
0422         n_ports = 8;
0423
0424     host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
0425     if (!host)
0426         return -ENOMEM;
0427
0428     bar_pos = 5;
0429     if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
0430         bar_pos = 3;
0431     /*
0432      * If this driver happens to only be useful on Apple's K2, then
0433      * we should check that here as it has a normal Serverworks ID
0434      */
0435     rc = pcim_enable_device(pdev);
0436     if (rc)
0437         return rc;
0438
0439     /*
0440      * Check if we have resources mapped at all (second function may
0441      * have been disabled by firmware)
0442      */
0443     if (pci_resource_len(pdev, bar_pos) == 0) {
0444         /* In IDE mode we need to pin the device to ensure that
0445             pcim_release does not clear the busmaster bit in config
0446             space, clearing causes busmaster DMA to fail on
0447             ports 3 & 4 */
0448         pcim_pin_device(pdev);
0449         return -ENODEV;
0450     }
0451
0452     /* Request and iomap PCI regions */
0453     rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
0454     if (rc == -EBUSY)
0455         pcim_pin_device(pdev);
0456     if (rc)
0457         return rc;
0458     host->iomap = pcim_iomap_table(pdev);
0459     mmio_base = host->iomap[bar_pos];
0460
0461     /* different controllers have different number of ports - currently 4 or 8 */
0462     /* All ports are on the same function. Multi-function device is no
0463      * longer available. This should not be seen in any system. */
0464     for (i = 0; i < host->n_ports; i++) {
0465         struct ata_port *ap = host->ports[i];
0466         unsigned int offset = i * K2_SATA_PORT_OFFSET;
0467
0468         k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
0469
0470         ata_port_pbar_desc(ap, 5, -1, "mmio");
0471         ata_port_pbar_desc(ap, 5, offset, "port");
0472     }
0473
0474     rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
0475     if (rc)
0476         return rc;
0477
0478     /* Clear a magic bit in SCR1 according to Darwin, those help
0479      * some funky seagate drives (though so far, those were already
0480      * set by the firmware on the machines I had access to)
0481      */
0482     writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
0483            mmio_base + K2_SATA_SICR1_OFFSET);
0484
0485     /* Clear SATA error & interrupts we don't use */
0486     writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
0487     writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
0488
0489     pci_set_master(pdev);
0490     return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
0491                  IRQF_SHARED, &k2_sata_sht);
0492 }
0493
0494 /* 0x240 is device ID for Apple K2 device
0495  * 0x241 is device ID for Serverworks Frodo4
0496  * 0x242 is device ID for Serverworks Frodo8
0497  * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
0498  * controller
0499  * */
0500 static const struct pci_device_id k2_sata_pci_tbl[] = {
0501     { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
0502     { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
0503     { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
0504     { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
0505     { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
0506     { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
0507     { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
0508
0509     { }
0510 };
0511
0512 static struct pci_driver k2_sata_pci_driver = {
0513     .name           = DRV_NAME,
0514     .id_table       = k2_sata_pci_tbl,
0515     .probe          = k2_sata_init_one,
0516     .remove         = ata_pci_remove_one,
0517 };
0518
0519 module_pci_driver(k2_sata_pci_driver);
0520
0521 MODULE_AUTHOR("Benjamin Herrenschmidt");
0522 MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
0523 MODULE_LICENSE("GPL");
0524 MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
0525 MODULE_VERSION(DRV_VERSION);