drivers/ata/sata_sis.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  sata_sis.c - Silicon Integrated Systems SATA
0004  *
0005  *  Maintained by:  Uwe Koziolek
0006  *              Please ALWAYS copy linux-ide@vger.kernel.org
0007  *          on emails.
0008  *
0009  *  Copyright 2004 Uwe Koziolek
0010  *
0011  *  libata documentation is available via 'make {ps|pdf}docs',
0012  *  as Documentation/driver-api/libata.rst
0013  *
0014  *  Hardware documentation available under NDA.
0015  */
0016
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/pci.h>
0020 #include <linux/blkdev.h>
0021 #include <linux/delay.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/device.h>
0024 #include <scsi/scsi_host.h>
0025 #include <linux/libata.h>
0026 #include "sis.h"
0027
0028 #define DRV_NAME    "sata_sis"
0029 #define DRV_VERSION "1.0"
0030
0031 enum {
0032     sis_180         = 0,
0033     SIS_SCR_PCI_BAR     = 5,
0034
0035     /* PCI configuration registers */
0036     SIS_GENCTL      = 0x54, /* IDE General Control register */
0037     SIS_SCR_BASE        = 0xc0, /* sata0 phy SCR registers */
0038     SIS180_SATA1_OFS    = 0x10, /* offset from sata0->sata1 phy regs */
0039     SIS182_SATA1_OFS    = 0x20, /* offset from sata0->sata1 phy regs */
0040     SIS_PMR         = 0x90, /* port mapping register */
0041     SIS_PMR_COMBINED    = 0x30,
0042
0043     /* random bits */
0044     SIS_FLAG_CFGSCR     = (1 << 30), /* host flag: SCRs via PCI cfg */
0045
0046     GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
0047 };
0048
0049 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
0050 static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
0051 static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
0052
0053 static const struct pci_device_id sis_pci_tbl[] = {
0054     { PCI_VDEVICE(SI, 0x0180), sis_180 },   /* SiS 964/180 */
0055     { PCI_VDEVICE(SI, 0x0181), sis_180 },   /* SiS 964/180 */
0056     { PCI_VDEVICE(SI, 0x0182), sis_180 },   /* SiS 965/965L */
0057     { PCI_VDEVICE(SI, 0x0183), sis_180 },   /* SiS 965/965L */
0058     { PCI_VDEVICE(SI, 0x1182), sis_180 },   /* SiS 966/680 */
0059     { PCI_VDEVICE(SI, 0x1183), sis_180 },   /* SiS 966/966L/968/680 */
0060
0061     { } /* terminate list */
0062 };
0063
0064 static struct pci_driver sis_pci_driver = {
0065     .name           = DRV_NAME,
0066     .id_table       = sis_pci_tbl,
0067     .probe          = sis_init_one,
0068     .remove         = ata_pci_remove_one,
0069 #ifdef CONFIG_PM_SLEEP
0070     .suspend        = ata_pci_device_suspend,
0071     .resume         = ata_pci_device_resume,
0072 #endif
0073 };
0074
0075 static struct scsi_host_template sis_sht = {
0076     ATA_BMDMA_SHT(DRV_NAME),
0077 };
0078
0079 static struct ata_port_operations sis_ops = {
0080     .inherits       = &ata_bmdma_port_ops,
0081     .scr_read       = sis_scr_read,
0082     .scr_write      = sis_scr_write,
0083 };
0084
0085 static const struct ata_port_info sis_port_info = {
0086     .flags      = ATA_FLAG_SATA,
0087     .pio_mask   = ATA_PIO4,
0088     .mwdma_mask = ATA_MWDMA2,
0089     .udma_mask  = ATA_UDMA6,
0090     .port_ops   = &sis_ops,
0091 };
0092
0093 MODULE_AUTHOR("Uwe Koziolek");
0094 MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller");
0095 MODULE_LICENSE("GPL");
0096 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
0097 MODULE_VERSION(DRV_VERSION);
0098
0099 static unsigned int get_scr_cfg_addr(struct ata_link *link, unsigned int sc_reg)
0100 {
0101     struct ata_port *ap = link->ap;
0102     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0103     unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
0104     u8 pmr;
0105
0106     if (ap->port_no)  {
0107         switch (pdev->device) {
0108         case 0x0180:
0109         case 0x0181:
0110             pci_read_config_byte(pdev, SIS_PMR, &pmr);
0111             if ((pmr & SIS_PMR_COMBINED) == 0)
0112                 addr += SIS180_SATA1_OFS;
0113             break;
0114
0115         case 0x0182:
0116         case 0x0183:
0117         case 0x1182:
0118             addr += SIS182_SATA1_OFS;
0119             break;
0120         }
0121     }
0122     if (link->pmp)
0123         addr += 0x10;
0124
0125     return addr;
0126 }
0127
0128 static u32 sis_scr_cfg_read(struct ata_link *link,
0129                 unsigned int sc_reg, u32 *val)
0130 {
0131     struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
0132     unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
0133
0134     if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
0135         return -EINVAL;
0136
0137     pci_read_config_dword(pdev, cfg_addr, val);
0138     return 0;
0139 }
0140
0141 static int sis_scr_cfg_write(struct ata_link *link,
0142                  unsigned int sc_reg, u32 val)
0143 {
0144     struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
0145     unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
0146
0147     pci_write_config_dword(pdev, cfg_addr, val);
0148     return 0;
0149 }
0150
0151 static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
0152 {
0153     struct ata_port *ap = link->ap;
0154     void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;
0155
0156     if (sc_reg > SCR_CONTROL)
0157         return -EINVAL;
0158
0159     if (ap->flags & SIS_FLAG_CFGSCR)
0160         return sis_scr_cfg_read(link, sc_reg, val);
0161
0162     *val = ioread32(base + sc_reg * 4);
0163     return 0;
0164 }
0165
0166 static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
0167 {
0168     struct ata_port *ap = link->ap;
0169     void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;
0170
0171     if (sc_reg > SCR_CONTROL)
0172         return -EINVAL;
0173
0174     if (ap->flags & SIS_FLAG_CFGSCR)
0175         return sis_scr_cfg_write(link, sc_reg, val);
0176
0177     iowrite32(val, base + (sc_reg * 4));
0178     return 0;
0179 }
0180
0181 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
0182 {
0183     struct ata_port_info pi = sis_port_info;
0184     const struct ata_port_info *ppi[] = { &pi, &pi };
0185     struct ata_host *host;
0186     u32 genctl, val;
0187     u8 pmr;
0188     u8 port2_start = 0x20;
0189     int i, rc;
0190
0191     ata_print_version_once(&pdev->dev, DRV_VERSION);
0192
0193     rc = pcim_enable_device(pdev);
0194     if (rc)
0195         return rc;
0196
0197     /* check and see if the SCRs are in IO space or PCI cfg space */
0198     pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
0199     if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
0200         pi.flags |= SIS_FLAG_CFGSCR;
0201
0202     /* if hardware thinks SCRs are in IO space, but there are
0203      * no IO resources assigned, change to PCI cfg space.
0204      */
0205     if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
0206         ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
0207          (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
0208         genctl &= ~GENCTL_IOMAPPED_SCR;
0209         pci_write_config_dword(pdev, SIS_GENCTL, genctl);
0210         pi.flags |= SIS_FLAG_CFGSCR;
0211     }
0212
0213     pci_read_config_byte(pdev, SIS_PMR, &pmr);
0214     switch (ent->device) {
0215     case 0x0180:
0216     case 0x0181:
0217
0218         /* The PATA-handling is provided by pata_sis */
0219         switch (pmr & 0x30) {
0220         case 0x10:
0221             ppi[1] = &sis_info133_for_sata;
0222             break;
0223
0224         case 0x30:
0225             ppi[0] = &sis_info133_for_sata;
0226             break;
0227         }
0228         if ((pmr & SIS_PMR_COMBINED) == 0) {
0229             dev_info(&pdev->dev,
0230                  "Detected SiS 180/181/964 chipset in SATA mode\n");
0231             port2_start = 64;
0232         } else {
0233             dev_info(&pdev->dev,
0234                  "Detected SiS 180/181 chipset in combined mode\n");
0235             port2_start = 0;
0236             pi.flags |= ATA_FLAG_SLAVE_POSS;
0237         }
0238         break;
0239
0240     case 0x0182:
0241     case 0x0183:
0242         pci_read_config_dword(pdev, 0x6C, &val);
0243         if (val & (1L << 31)) {
0244             dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n");
0245             pi.flags |= ATA_FLAG_SLAVE_POSS;
0246         } else {
0247             dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n");
0248         }
0249         break;
0250
0251     case 0x1182:
0252         dev_info(&pdev->dev,
0253              "Detected SiS 1182/966/680 SATA controller\n");
0254         pi.flags |= ATA_FLAG_SLAVE_POSS;
0255         break;
0256
0257     case 0x1183:
0258         dev_info(&pdev->dev,
0259              "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
0260         ppi[0] = &sis_info133_for_sata;
0261         ppi[1] = &sis_info133_for_sata;
0262         break;
0263     }
0264
0265     rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
0266     if (rc)
0267         return rc;
0268
0269     for (i = 0; i < 2; i++) {
0270         struct ata_port *ap = host->ports[i];
0271
0272         if (ap->flags & ATA_FLAG_SATA &&
0273             ap->flags & ATA_FLAG_SLAVE_POSS) {
0274             rc = ata_slave_link_init(ap);
0275             if (rc)
0276                 return rc;
0277         }
0278     }
0279
0280     if (!(pi.flags & SIS_FLAG_CFGSCR)) {
0281         void __iomem *mmio;
0282
0283         rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
0284         if (rc)
0285             return rc;
0286         mmio = host->iomap[SIS_SCR_PCI_BAR];
0287
0288         host->ports[0]->ioaddr.scr_addr = mmio;
0289         host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
0290     }
0291
0292     pci_set_master(pdev);
0293     pci_intx(pdev, 1);
0294     return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
0295                  IRQF_SHARED, &sis_sht);
0296 }
0297
0298 module_pci_driver(sis_pci_driver);