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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
0004  *
0005  * Copyright 2005  Tejun Heo
0006  *
0007  * Based on preview driver from Silicon Image.
0008  */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/gfp.h>
0013 #include <linux/pci.h>
0014 #include <linux/blkdev.h>
0015 #include <linux/delay.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/dma-mapping.h>
0018 #include <linux/device.h>
0019 #include <scsi/scsi_host.h>
0020 #include <scsi/scsi_cmnd.h>
0021 #include <linux/libata.h>
0022 
0023 #define DRV_NAME    "sata_sil24"
0024 #define DRV_VERSION "1.1"
0025 
0026 /*
0027  * Port request block (PRB) 32 bytes
0028  */
0029 struct sil24_prb {
0030     __le16  ctrl;
0031     __le16  prot;
0032     __le32  rx_cnt;
0033     u8  fis[6 * 4];
0034 };
0035 
0036 /*
0037  * Scatter gather entry (SGE) 16 bytes
0038  */
0039 struct sil24_sge {
0040     __le64  addr;
0041     __le32  cnt;
0042     __le32  flags;
0043 };
0044 
0045 
0046 enum {
0047     SIL24_HOST_BAR      = 0,
0048     SIL24_PORT_BAR      = 2,
0049 
0050     /* sil24 fetches in chunks of 64bytes.  The first block
0051      * contains the PRB and two SGEs.  From the second block, it's
0052      * consisted of four SGEs and called SGT.  Calculate the
0053      * number of SGTs that fit into one page.
0054      */
0055     SIL24_PRB_SZ        = sizeof(struct sil24_prb)
0056                   + 2 * sizeof(struct sil24_sge),
0057     SIL24_MAX_SGT       = (PAGE_SIZE - SIL24_PRB_SZ)
0058                   / (4 * sizeof(struct sil24_sge)),
0059 
0060     /* This will give us one unused SGEs for ATA.  This extra SGE
0061      * will be used to store CDB for ATAPI devices.
0062      */
0063     SIL24_MAX_SGE       = 4 * SIL24_MAX_SGT + 1,
0064 
0065     /*
0066      * Global controller registers (128 bytes @ BAR0)
0067      */
0068         /* 32 bit regs */
0069     HOST_SLOT_STAT      = 0x00, /* 32 bit slot stat * 4 */
0070     HOST_CTRL       = 0x40,
0071     HOST_IRQ_STAT       = 0x44,
0072     HOST_PHY_CFG        = 0x48,
0073     HOST_BIST_CTRL      = 0x50,
0074     HOST_BIST_PTRN      = 0x54,
0075     HOST_BIST_STAT      = 0x58,
0076     HOST_MEM_BIST_STAT  = 0x5c,
0077     HOST_FLASH_CMD      = 0x70,
0078         /* 8 bit regs */
0079     HOST_FLASH_DATA     = 0x74,
0080     HOST_TRANSITION_DETECT  = 0x75,
0081     HOST_GPIO_CTRL      = 0x76,
0082     HOST_I2C_ADDR       = 0x78, /* 32 bit */
0083     HOST_I2C_DATA       = 0x7c,
0084     HOST_I2C_XFER_CNT   = 0x7e,
0085     HOST_I2C_CTRL       = 0x7f,
0086 
0087     /* HOST_SLOT_STAT bits */
0088     HOST_SSTAT_ATTN     = (1 << 31),
0089 
0090     /* HOST_CTRL bits */
0091     HOST_CTRL_M66EN     = (1 << 16), /* M66EN PCI bus signal */
0092     HOST_CTRL_TRDY      = (1 << 17), /* latched PCI TRDY */
0093     HOST_CTRL_STOP      = (1 << 18), /* latched PCI STOP */
0094     HOST_CTRL_DEVSEL    = (1 << 19), /* latched PCI DEVSEL */
0095     HOST_CTRL_REQ64     = (1 << 20), /* latched PCI REQ64 */
0096     HOST_CTRL_GLOBAL_RST    = (1 << 31), /* global reset */
0097 
0098     /*
0099      * Port registers
0100      * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
0101      */
0102     PORT_REGS_SIZE      = 0x2000,
0103 
0104     PORT_LRAM       = 0x0000, /* 31 LRAM slots and PMP regs */
0105     PORT_LRAM_SLOT_SZ   = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
0106 
0107     PORT_PMP        = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
0108     PORT_PMP_STATUS     = 0x0000, /* port device status offset */
0109     PORT_PMP_QACTIVE    = 0x0004, /* port device QActive offset */
0110     PORT_PMP_SIZE       = 0x0008, /* 8 bytes per PMP */
0111 
0112         /* 32 bit regs */
0113     PORT_CTRL_STAT      = 0x1000, /* write: ctrl-set, read: stat */
0114     PORT_CTRL_CLR       = 0x1004, /* write: ctrl-clear */
0115     PORT_IRQ_STAT       = 0x1008, /* high: status, low: interrupt */
0116     PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
0117     PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
0118     PORT_ACTIVATE_UPPER_ADDR= 0x101c,
0119     PORT_EXEC_FIFO      = 0x1020, /* command execution fifo */
0120     PORT_CMD_ERR        = 0x1024, /* command error number */
0121     PORT_FIS_CFG        = 0x1028,
0122     PORT_FIFO_THRES     = 0x102c,
0123         /* 16 bit regs */
0124     PORT_DECODE_ERR_CNT = 0x1040,
0125     PORT_DECODE_ERR_THRESH  = 0x1042,
0126     PORT_CRC_ERR_CNT    = 0x1044,
0127     PORT_CRC_ERR_THRESH = 0x1046,
0128     PORT_HSHK_ERR_CNT   = 0x1048,
0129     PORT_HSHK_ERR_THRESH    = 0x104a,
0130         /* 32 bit regs */
0131     PORT_PHY_CFG        = 0x1050,
0132     PORT_SLOT_STAT      = 0x1800,
0133     PORT_CMD_ACTIVATE   = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
0134     PORT_CONTEXT        = 0x1e04,
0135     PORT_EXEC_DIAG      = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
0136     PORT_PSD_DIAG       = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
0137     PORT_SCONTROL       = 0x1f00,
0138     PORT_SSTATUS        = 0x1f04,
0139     PORT_SERROR     = 0x1f08,
0140     PORT_SACTIVE        = 0x1f0c,
0141 
0142     /* PORT_CTRL_STAT bits */
0143     PORT_CS_PORT_RST    = (1 << 0), /* port reset */
0144     PORT_CS_DEV_RST     = (1 << 1), /* device reset */
0145     PORT_CS_INIT        = (1 << 2), /* port initialize */
0146     PORT_CS_IRQ_WOC     = (1 << 3), /* interrupt write one to clear */
0147     PORT_CS_CDB16       = (1 << 5), /* 0=12b cdb, 1=16b cdb */
0148     PORT_CS_PMP_RESUME  = (1 << 6), /* PMP resume */
0149     PORT_CS_32BIT_ACTV  = (1 << 10), /* 32-bit activation */
0150     PORT_CS_PMP_EN      = (1 << 13), /* port multiplier enable */
0151     PORT_CS_RDY     = (1 << 31), /* port ready to accept commands */
0152 
0153     /* PORT_IRQ_STAT/ENABLE_SET/CLR */
0154     /* bits[11:0] are masked */
0155     PORT_IRQ_COMPLETE   = (1 << 0), /* command(s) completed */
0156     PORT_IRQ_ERROR      = (1 << 1), /* command execution error */
0157     PORT_IRQ_PORTRDY_CHG    = (1 << 2), /* port ready change */
0158     PORT_IRQ_PWR_CHG    = (1 << 3), /* power management change */
0159     PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
0160     PORT_IRQ_COMWAKE    = (1 << 5), /* COMWAKE received */
0161     PORT_IRQ_UNK_FIS    = (1 << 6), /* unknown FIS received */
0162     PORT_IRQ_DEV_XCHG   = (1 << 7), /* device exchanged */
0163     PORT_IRQ_8B10B      = (1 << 8), /* 8b/10b decode error threshold */
0164     PORT_IRQ_CRC        = (1 << 9), /* CRC error threshold */
0165     PORT_IRQ_HANDSHAKE  = (1 << 10), /* handshake error threshold */
0166     PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
0167 
0168     DEF_PORT_IRQ        = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
0169                   PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
0170                   PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
0171 
0172     /* bits[27:16] are unmasked (raw) */
0173     PORT_IRQ_RAW_SHIFT  = 16,
0174     PORT_IRQ_MASKED_MASK    = 0x7ff,
0175     PORT_IRQ_RAW_MASK   = (0x7ff << PORT_IRQ_RAW_SHIFT),
0176 
0177     /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
0178     PORT_IRQ_STEER_SHIFT    = 30,
0179     PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
0180 
0181     /* PORT_CMD_ERR constants */
0182     PORT_CERR_DEV       = 1, /* Error bit in D2H Register FIS */
0183     PORT_CERR_SDB       = 2, /* Error bit in SDB FIS */
0184     PORT_CERR_DATA      = 3, /* Error in data FIS not detected by dev */
0185     PORT_CERR_SEND      = 4, /* Initial cmd FIS transmission failure */
0186     PORT_CERR_INCONSISTENT  = 5, /* Protocol mismatch */
0187     PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
0188     PORT_CERR_UNDERRUN  = 7, /* Ran out of SGEs while writing */
0189     PORT_CERR_OVERRUN   = 8, /* Ran out of SGEs while reading */
0190     PORT_CERR_PKT_PROT  = 11, /* DIR invalid in 1st PIO setup of ATAPI */
0191     PORT_CERR_SGT_BOUNDARY  = 16, /* PLD ecode 00 - SGT not on qword boundary */
0192     PORT_CERR_SGT_TGTABRT   = 17, /* PLD ecode 01 - target abort */
0193     PORT_CERR_SGT_MSTABRT   = 18, /* PLD ecode 10 - master abort */
0194     PORT_CERR_SGT_PCIPERR   = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
0195     PORT_CERR_CMD_BOUNDARY  = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
0196     PORT_CERR_CMD_TGTABRT   = 25, /* ctrl[15:13] 010 - target abort */
0197     PORT_CERR_CMD_MSTABRT   = 26, /* ctrl[15:13] 100 - master abort */
0198     PORT_CERR_CMD_PCIPERR   = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
0199     PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
0200     PORT_CERR_XFR_TGTABRT   = 33, /* PSD ecode 01 - target abort */
0201     PORT_CERR_XFR_MSTABRT   = 34, /* PSD ecode 10 - master abort */
0202     PORT_CERR_XFR_PCIPERR   = 35, /* PSD ecode 11 - PCI prity err during transfer */
0203     PORT_CERR_SENDSERVICE   = 36, /* FIS received while sending service */
0204 
0205     /* bits of PRB control field */
0206     PRB_CTRL_PROTOCOL   = (1 << 0), /* override def. ATA protocol */
0207     PRB_CTRL_PACKET_READ    = (1 << 4), /* PACKET cmd read */
0208     PRB_CTRL_PACKET_WRITE   = (1 << 5), /* PACKET cmd write */
0209     PRB_CTRL_NIEN       = (1 << 6), /* Mask completion irq */
0210     PRB_CTRL_SRST       = (1 << 7), /* Soft reset request (ign BSY?) */
0211 
0212     /* PRB protocol field */
0213     PRB_PROT_PACKET     = (1 << 0),
0214     PRB_PROT_TCQ        = (1 << 1),
0215     PRB_PROT_NCQ        = (1 << 2),
0216     PRB_PROT_READ       = (1 << 3),
0217     PRB_PROT_WRITE      = (1 << 4),
0218     PRB_PROT_TRANSPARENT    = (1 << 5),
0219 
0220     /*
0221      * Other constants
0222      */
0223     SGE_TRM         = (1 << 31), /* Last SGE in chain */
0224     SGE_LNK         = (1 << 30), /* linked list
0225                         Points to SGT, not SGE */
0226     SGE_DRD         = (1 << 29), /* discard data read (/dev/null)
0227                         data address ignored */
0228 
0229     SIL24_MAX_CMDS      = 31,
0230 
0231     /* board id */
0232     BID_SIL3124     = 0,
0233     BID_SIL3132     = 1,
0234     BID_SIL3131     = 2,
0235 
0236     /* host flags */
0237     SIL24_COMMON_FLAGS  = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
0238                   ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
0239                   ATA_FLAG_AN | ATA_FLAG_PMP,
0240     SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
0241 
0242     IRQ_STAT_4PORTS     = 0xf,
0243 };
0244 
0245 struct sil24_ata_block {
0246     struct sil24_prb prb;
0247     struct sil24_sge sge[SIL24_MAX_SGE];
0248 };
0249 
0250 struct sil24_atapi_block {
0251     struct sil24_prb prb;
0252     u8 cdb[16];
0253     struct sil24_sge sge[SIL24_MAX_SGE];
0254 };
0255 
0256 union sil24_cmd_block {
0257     struct sil24_ata_block ata;
0258     struct sil24_atapi_block atapi;
0259 };
0260 
0261 static const struct sil24_cerr_info {
0262     unsigned int err_mask, action;
0263     const char *desc;
0264 } sil24_cerr_db[] = {
0265     [0]         = { AC_ERR_DEV, 0,
0266                     "device error" },
0267     [PORT_CERR_DEV]     = { AC_ERR_DEV, 0,
0268                     "device error via D2H FIS" },
0269     [PORT_CERR_SDB]     = { AC_ERR_DEV, 0,
0270                     "device error via SDB FIS" },
0271     [PORT_CERR_DATA]    = { AC_ERR_ATA_BUS, ATA_EH_RESET,
0272                     "error in data FIS" },
0273     [PORT_CERR_SEND]    = { AC_ERR_ATA_BUS, ATA_EH_RESET,
0274                     "failed to transmit command FIS" },
0275     [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
0276                      "protocol mismatch" },
0277     [PORT_CERR_DIRECTION]   = { AC_ERR_HSM, ATA_EH_RESET,
0278                     "data direction mismatch" },
0279     [PORT_CERR_UNDERRUN]    = { AC_ERR_HSM, ATA_EH_RESET,
0280                     "ran out of SGEs while writing" },
0281     [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
0282                     "ran out of SGEs while reading" },
0283     [PORT_CERR_PKT_PROT]    = { AC_ERR_HSM, ATA_EH_RESET,
0284                     "invalid data direction for ATAPI CDB" },
0285     [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
0286                      "SGT not on qword boundary" },
0287     [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
0288                     "PCI target abort while fetching SGT" },
0289     [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
0290                     "PCI master abort while fetching SGT" },
0291     [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
0292                     "PCI parity error while fetching SGT" },
0293     [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
0294                      "PRB not on qword boundary" },
0295     [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
0296                     "PCI target abort while fetching PRB" },
0297     [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
0298                     "PCI master abort while fetching PRB" },
0299     [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
0300                     "PCI parity error while fetching PRB" },
0301     [PORT_CERR_XFR_UNDEF]   = { AC_ERR_HOST_BUS, ATA_EH_RESET,
0302                     "undefined error while transferring data" },
0303     [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
0304                     "PCI target abort while transferring data" },
0305     [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
0306                     "PCI master abort while transferring data" },
0307     [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
0308                     "PCI parity error while transferring data" },
0309     [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
0310                     "FIS received while sending service FIS" },
0311 };
0312 
0313 /*
0314  * ap->private_data
0315  *
0316  * The preview driver always returned 0 for status.  We emulate it
0317  * here from the previous interrupt.
0318  */
0319 struct sil24_port_priv {
0320     union sil24_cmd_block *cmd_block;   /* 32 cmd blocks */
0321     dma_addr_t cmd_block_dma;       /* DMA base addr for them */
0322     int do_port_rst;
0323 };
0324 
0325 static void sil24_dev_config(struct ata_device *dev);
0326 static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val);
0327 static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val);
0328 static int sil24_qc_defer(struct ata_queued_cmd *qc);
0329 static enum ata_completion_errors sil24_qc_prep(struct ata_queued_cmd *qc);
0330 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
0331 static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
0332 static void sil24_pmp_attach(struct ata_port *ap);
0333 static void sil24_pmp_detach(struct ata_port *ap);
0334 static void sil24_freeze(struct ata_port *ap);
0335 static void sil24_thaw(struct ata_port *ap);
0336 static int sil24_softreset(struct ata_link *link, unsigned int *class,
0337                unsigned long deadline);
0338 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
0339                unsigned long deadline);
0340 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
0341                    unsigned long deadline);
0342 static void sil24_error_handler(struct ata_port *ap);
0343 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
0344 static int sil24_port_start(struct ata_port *ap);
0345 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
0346 #ifdef CONFIG_PM_SLEEP
0347 static int sil24_pci_device_resume(struct pci_dev *pdev);
0348 #endif
0349 #ifdef CONFIG_PM
0350 static int sil24_port_resume(struct ata_port *ap);
0351 #endif
0352 
0353 static const struct pci_device_id sil24_pci_tbl[] = {
0354     { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
0355     { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
0356     { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
0357     { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
0358     { PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 },
0359     { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
0360     { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
0361 
0362     { } /* terminate list */
0363 };
0364 
0365 static struct pci_driver sil24_pci_driver = {
0366     .name           = DRV_NAME,
0367     .id_table       = sil24_pci_tbl,
0368     .probe          = sil24_init_one,
0369     .remove         = ata_pci_remove_one,
0370 #ifdef CONFIG_PM_SLEEP
0371     .suspend        = ata_pci_device_suspend,
0372     .resume         = sil24_pci_device_resume,
0373 #endif
0374 };
0375 
0376 static struct scsi_host_template sil24_sht = {
0377     __ATA_BASE_SHT(DRV_NAME),
0378     .can_queue      = SIL24_MAX_CMDS,
0379     .sg_tablesize       = SIL24_MAX_SGE,
0380     .dma_boundary       = ATA_DMA_BOUNDARY,
0381     .tag_alloc_policy   = BLK_TAG_ALLOC_FIFO,
0382     .sdev_groups        = ata_ncq_sdev_groups,
0383     .change_queue_depth = ata_scsi_change_queue_depth,
0384     .slave_configure    = ata_scsi_slave_config
0385 };
0386 
0387 static struct ata_port_operations sil24_ops = {
0388     .inherits       = &sata_pmp_port_ops,
0389 
0390     .qc_defer       = sil24_qc_defer,
0391     .qc_prep        = sil24_qc_prep,
0392     .qc_issue       = sil24_qc_issue,
0393     .qc_fill_rtf        = sil24_qc_fill_rtf,
0394 
0395     .freeze         = sil24_freeze,
0396     .thaw           = sil24_thaw,
0397     .softreset      = sil24_softreset,
0398     .hardreset      = sil24_hardreset,
0399     .pmp_softreset      = sil24_softreset,
0400     .pmp_hardreset      = sil24_pmp_hardreset,
0401     .error_handler      = sil24_error_handler,
0402     .post_internal_cmd  = sil24_post_internal_cmd,
0403     .dev_config     = sil24_dev_config,
0404 
0405     .scr_read       = sil24_scr_read,
0406     .scr_write      = sil24_scr_write,
0407     .pmp_attach     = sil24_pmp_attach,
0408     .pmp_detach     = sil24_pmp_detach,
0409 
0410     .port_start     = sil24_port_start,
0411 #ifdef CONFIG_PM
0412     .port_resume        = sil24_port_resume,
0413 #endif
0414 };
0415 
0416 static bool sata_sil24_msi;    /* Disable MSI */
0417 module_param_named(msi, sata_sil24_msi, bool, S_IRUGO);
0418 MODULE_PARM_DESC(msi, "Enable MSI (Default: false)");
0419 
0420 /*
0421  * Use bits 30-31 of port_flags to encode available port numbers.
0422  * Current maxium is 4.
0423  */
0424 #define SIL24_NPORTS2FLAG(nports)   ((((unsigned)(nports) - 1) & 0x3) << 30)
0425 #define SIL24_FLAG2NPORTS(flag)     ((((flag) >> 30) & 0x3) + 1)
0426 
0427 static const struct ata_port_info sil24_port_info[] = {
0428     /* sil_3124 */
0429     {
0430         .flags      = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
0431                   SIL24_FLAG_PCIX_IRQ_WOC,
0432         .pio_mask   = ATA_PIO4,
0433         .mwdma_mask = ATA_MWDMA2,
0434         .udma_mask  = ATA_UDMA5,
0435         .port_ops   = &sil24_ops,
0436     },
0437     /* sil_3132 */
0438     {
0439         .flags      = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
0440         .pio_mask   = ATA_PIO4,
0441         .mwdma_mask = ATA_MWDMA2,
0442         .udma_mask  = ATA_UDMA5,
0443         .port_ops   = &sil24_ops,
0444     },
0445     /* sil_3131/sil_3531 */
0446     {
0447         .flags      = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
0448         .pio_mask   = ATA_PIO4,
0449         .mwdma_mask = ATA_MWDMA2,
0450         .udma_mask  = ATA_UDMA5,
0451         .port_ops   = &sil24_ops,
0452     },
0453 };
0454 
0455 static int sil24_tag(int tag)
0456 {
0457     if (unlikely(ata_tag_internal(tag)))
0458         return 0;
0459     return tag;
0460 }
0461 
0462 static unsigned long sil24_port_offset(struct ata_port *ap)
0463 {
0464     return ap->port_no * PORT_REGS_SIZE;
0465 }
0466 
0467 static void __iomem *sil24_port_base(struct ata_port *ap)
0468 {
0469     return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap);
0470 }
0471 
0472 static void sil24_dev_config(struct ata_device *dev)
0473 {
0474     void __iomem *port = sil24_port_base(dev->link->ap);
0475 
0476     if (dev->cdb_len == 16)
0477         writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
0478     else
0479         writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
0480 }
0481 
0482 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
0483 {
0484     void __iomem *port = sil24_port_base(ap);
0485     struct sil24_prb __iomem *prb;
0486     u8 fis[6 * 4];
0487 
0488     prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
0489     memcpy_fromio(fis, prb->fis, sizeof(fis));
0490     ata_tf_from_fis(fis, tf);
0491 }
0492 
0493 static int sil24_scr_map[] = {
0494     [SCR_CONTROL]   = 0,
0495     [SCR_STATUS]    = 1,
0496     [SCR_ERROR] = 2,
0497     [SCR_ACTIVE]    = 3,
0498 };
0499 
0500 static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
0501 {
0502     void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
0503 
0504     if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
0505         *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
0506         return 0;
0507     }
0508     return -EINVAL;
0509 }
0510 
0511 static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
0512 {
0513     void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
0514 
0515     if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
0516         writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
0517         return 0;
0518     }
0519     return -EINVAL;
0520 }
0521 
0522 static void sil24_config_port(struct ata_port *ap)
0523 {
0524     void __iomem *port = sil24_port_base(ap);
0525 
0526     /* configure IRQ WoC */
0527     if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
0528         writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
0529     else
0530         writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
0531 
0532     /* zero error counters. */
0533     writew(0x8000, port + PORT_DECODE_ERR_THRESH);
0534     writew(0x8000, port + PORT_CRC_ERR_THRESH);
0535     writew(0x8000, port + PORT_HSHK_ERR_THRESH);
0536     writew(0x0000, port + PORT_DECODE_ERR_CNT);
0537     writew(0x0000, port + PORT_CRC_ERR_CNT);
0538     writew(0x0000, port + PORT_HSHK_ERR_CNT);
0539 
0540     /* always use 64bit activation */
0541     writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
0542 
0543     /* clear port multiplier enable and resume bits */
0544     writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
0545 }
0546 
0547 static void sil24_config_pmp(struct ata_port *ap, int attached)
0548 {
0549     void __iomem *port = sil24_port_base(ap);
0550 
0551     if (attached)
0552         writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
0553     else
0554         writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
0555 }
0556 
0557 static void sil24_clear_pmp(struct ata_port *ap)
0558 {
0559     void __iomem *port = sil24_port_base(ap);
0560     int i;
0561 
0562     writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
0563 
0564     for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
0565         void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
0566 
0567         writel(0, pmp_base + PORT_PMP_STATUS);
0568         writel(0, pmp_base + PORT_PMP_QACTIVE);
0569     }
0570 }
0571 
0572 static int sil24_init_port(struct ata_port *ap)
0573 {
0574     void __iomem *port = sil24_port_base(ap);
0575     struct sil24_port_priv *pp = ap->private_data;
0576     u32 tmp;
0577 
0578     /* clear PMP error status */
0579     if (sata_pmp_attached(ap))
0580         sil24_clear_pmp(ap);
0581 
0582     writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
0583     ata_wait_register(ap, port + PORT_CTRL_STAT,
0584               PORT_CS_INIT, PORT_CS_INIT, 10, 100);
0585     tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
0586                 PORT_CS_RDY, 0, 10, 100);
0587 
0588     if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
0589         pp->do_port_rst = 1;
0590         ap->link.eh_context.i.action |= ATA_EH_RESET;
0591         return -EIO;
0592     }
0593 
0594     return 0;
0595 }
0596 
0597 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
0598                  const struct ata_taskfile *tf,
0599                  int is_cmd, u32 ctrl,
0600                  unsigned long timeout_msec)
0601 {
0602     void __iomem *port = sil24_port_base(ap);
0603     struct sil24_port_priv *pp = ap->private_data;
0604     struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
0605     dma_addr_t paddr = pp->cmd_block_dma;
0606     u32 irq_enabled, irq_mask, irq_stat;
0607     int rc;
0608 
0609     prb->ctrl = cpu_to_le16(ctrl);
0610     ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
0611 
0612     /* temporarily plug completion and error interrupts */
0613     irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
0614     writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
0615 
0616     /*
0617      * The barrier is required to ensure that writes to cmd_block reach
0618      * the memory before the write to PORT_CMD_ACTIVATE.
0619      */
0620     wmb();
0621     writel((u32)paddr, port + PORT_CMD_ACTIVATE);
0622     writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
0623 
0624     irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
0625     irq_stat = ata_wait_register(ap, port + PORT_IRQ_STAT, irq_mask, 0x0,
0626                      10, timeout_msec);
0627 
0628     writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
0629     irq_stat >>= PORT_IRQ_RAW_SHIFT;
0630 
0631     if (irq_stat & PORT_IRQ_COMPLETE)
0632         rc = 0;
0633     else {
0634         /* force port into known state */
0635         sil24_init_port(ap);
0636 
0637         if (irq_stat & PORT_IRQ_ERROR)
0638             rc = -EIO;
0639         else
0640             rc = -EBUSY;
0641     }
0642 
0643     /* restore IRQ enabled */
0644     writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
0645 
0646     return rc;
0647 }
0648 
0649 static int sil24_softreset(struct ata_link *link, unsigned int *class,
0650                unsigned long deadline)
0651 {
0652     struct ata_port *ap = link->ap;
0653     int pmp = sata_srst_pmp(link);
0654     unsigned long timeout_msec = 0;
0655     struct ata_taskfile tf;
0656     const char *reason;
0657     int rc;
0658 
0659     /* put the port into known state */
0660     if (sil24_init_port(ap)) {
0661         reason = "port not ready";
0662         goto err;
0663     }
0664 
0665     /* do SRST */
0666     if (time_after(deadline, jiffies))
0667         timeout_msec = jiffies_to_msecs(deadline - jiffies);
0668 
0669     ata_tf_init(link->device, &tf); /* doesn't really matter */
0670     rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
0671                    timeout_msec);
0672     if (rc == -EBUSY) {
0673         reason = "timeout";
0674         goto err;
0675     } else if (rc) {
0676         reason = "SRST command error";
0677         goto err;
0678     }
0679 
0680     sil24_read_tf(ap, 0, &tf);
0681     *class = ata_port_classify(ap, &tf);
0682 
0683     return 0;
0684 
0685  err:
0686     ata_link_err(link, "softreset failed (%s)\n", reason);
0687     return -EIO;
0688 }
0689 
0690 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
0691                unsigned long deadline)
0692 {
0693     struct ata_port *ap = link->ap;
0694     void __iomem *port = sil24_port_base(ap);
0695     struct sil24_port_priv *pp = ap->private_data;
0696     int did_port_rst = 0;
0697     const char *reason;
0698     int tout_msec, rc;
0699     u32 tmp;
0700 
0701  retry:
0702     /* Sometimes, DEV_RST is not enough to recover the controller.
0703      * This happens often after PM DMA CS errata.
0704      */
0705     if (pp->do_port_rst) {
0706         ata_port_warn(ap,
0707                   "controller in dubious state, performing PORT_RST\n");
0708 
0709         writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
0710         ata_msleep(ap, 10);
0711         writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
0712         ata_wait_register(ap, port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
0713                   10, 5000);
0714 
0715         /* restore port configuration */
0716         sil24_config_port(ap);
0717         sil24_config_pmp(ap, ap->nr_pmp_links);
0718 
0719         pp->do_port_rst = 0;
0720         did_port_rst = 1;
0721     }
0722 
0723     /* sil24 does the right thing(tm) without any protection */
0724     sata_set_spd(link);
0725 
0726     tout_msec = 100;
0727     if (ata_link_online(link))
0728         tout_msec = 5000;
0729 
0730     writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
0731     tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
0732                 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
0733                 tout_msec);
0734 
0735     /* SStatus oscillates between zero and valid status after
0736      * DEV_RST, debounce it.
0737      */
0738     rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
0739     if (rc) {
0740         reason = "PHY debouncing failed";
0741         goto err;
0742     }
0743 
0744     if (tmp & PORT_CS_DEV_RST) {
0745         if (ata_link_offline(link))
0746             return 0;
0747         reason = "link not ready";
0748         goto err;
0749     }
0750 
0751     /* Sil24 doesn't store signature FIS after hardreset, so we
0752      * can't wait for BSY to clear.  Some devices take a long time
0753      * to get ready and those devices will choke if we don't wait
0754      * for BSY clearance here.  Tell libata to perform follow-up
0755      * softreset.
0756      */
0757     return -EAGAIN;
0758 
0759  err:
0760     if (!did_port_rst) {
0761         pp->do_port_rst = 1;
0762         goto retry;
0763     }
0764 
0765     ata_link_err(link, "hardreset failed (%s)\n", reason);
0766     return -EIO;
0767 }
0768 
0769 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
0770                  struct sil24_sge *sge)
0771 {
0772     struct scatterlist *sg;
0773     struct sil24_sge *last_sge = NULL;
0774     unsigned int si;
0775 
0776     for_each_sg(qc->sg, sg, qc->n_elem, si) {
0777         sge->addr = cpu_to_le64(sg_dma_address(sg));
0778         sge->cnt = cpu_to_le32(sg_dma_len(sg));
0779         sge->flags = 0;
0780 
0781         last_sge = sge;
0782         sge++;
0783     }
0784 
0785     last_sge->flags = cpu_to_le32(SGE_TRM);
0786 }
0787 
0788 static int sil24_qc_defer(struct ata_queued_cmd *qc)
0789 {
0790     struct ata_link *link = qc->dev->link;
0791     struct ata_port *ap = link->ap;
0792     u8 prot = qc->tf.protocol;
0793 
0794     /*
0795      * There is a bug in the chip:
0796      * Port LRAM Causes the PRB/SGT Data to be Corrupted
0797      * If the host issues a read request for LRAM and SActive registers
0798      * while active commands are available in the port, PRB/SGT data in
0799      * the LRAM can become corrupted. This issue applies only when
0800      * reading from, but not writing to, the LRAM.
0801      *
0802      * Therefore, reading LRAM when there is no particular error [and
0803      * other commands may be outstanding] is prohibited.
0804      *
0805      * To avoid this bug there are two situations where a command must run
0806      * exclusive of any other commands on the port:
0807      *
0808      * - ATAPI commands which check the sense data
0809      * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
0810      *   set.
0811      *
0812      */
0813     int is_excl = (ata_is_atapi(prot) ||
0814                (qc->flags & ATA_QCFLAG_RESULT_TF));
0815 
0816     if (unlikely(ap->excl_link)) {
0817         if (link == ap->excl_link) {
0818             if (ap->nr_active_links)
0819                 return ATA_DEFER_PORT;
0820             qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
0821         } else
0822             return ATA_DEFER_PORT;
0823     } else if (unlikely(is_excl)) {
0824         ap->excl_link = link;
0825         if (ap->nr_active_links)
0826             return ATA_DEFER_PORT;
0827         qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
0828     }
0829 
0830     return ata_std_qc_defer(qc);
0831 }
0832 
0833 static enum ata_completion_errors sil24_qc_prep(struct ata_queued_cmd *qc)
0834 {
0835     struct ata_port *ap = qc->ap;
0836     struct sil24_port_priv *pp = ap->private_data;
0837     union sil24_cmd_block *cb;
0838     struct sil24_prb *prb;
0839     struct sil24_sge *sge;
0840     u16 ctrl = 0;
0841 
0842     cb = &pp->cmd_block[sil24_tag(qc->hw_tag)];
0843 
0844     if (!ata_is_atapi(qc->tf.protocol)) {
0845         prb = &cb->ata.prb;
0846         sge = cb->ata.sge;
0847         if (ata_is_data(qc->tf.protocol)) {
0848             u16 prot = 0;
0849             ctrl = PRB_CTRL_PROTOCOL;
0850             if (ata_is_ncq(qc->tf.protocol))
0851                 prot |= PRB_PROT_NCQ;
0852             if (qc->tf.flags & ATA_TFLAG_WRITE)
0853                 prot |= PRB_PROT_WRITE;
0854             else
0855                 prot |= PRB_PROT_READ;
0856             prb->prot = cpu_to_le16(prot);
0857         }
0858     } else {
0859         prb = &cb->atapi.prb;
0860         sge = cb->atapi.sge;
0861         memset(cb->atapi.cdb, 0, sizeof(cb->atapi.cdb));
0862         memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
0863 
0864         if (ata_is_data(qc->tf.protocol)) {
0865             if (qc->tf.flags & ATA_TFLAG_WRITE)
0866                 ctrl = PRB_CTRL_PACKET_WRITE;
0867             else
0868                 ctrl = PRB_CTRL_PACKET_READ;
0869         }
0870     }
0871 
0872     prb->ctrl = cpu_to_le16(ctrl);
0873     ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
0874 
0875     if (qc->flags & ATA_QCFLAG_DMAMAP)
0876         sil24_fill_sg(qc, sge);
0877 
0878     return AC_ERR_OK;
0879 }
0880 
0881 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
0882 {
0883     struct ata_port *ap = qc->ap;
0884     struct sil24_port_priv *pp = ap->private_data;
0885     void __iomem *port = sil24_port_base(ap);
0886     unsigned int tag = sil24_tag(qc->hw_tag);
0887     dma_addr_t paddr;
0888     void __iomem *activate;
0889 
0890     paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
0891     activate = port + PORT_CMD_ACTIVATE + tag * 8;
0892 
0893     /*
0894      * The barrier is required to ensure that writes to cmd_block reach
0895      * the memory before the write to PORT_CMD_ACTIVATE.
0896      */
0897     wmb();
0898     writel((u32)paddr, activate);
0899     writel((u64)paddr >> 32, activate + 4);
0900 
0901     return 0;
0902 }
0903 
0904 static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
0905 {
0906     sil24_read_tf(qc->ap, qc->hw_tag, &qc->result_tf);
0907     return true;
0908 }
0909 
0910 static void sil24_pmp_attach(struct ata_port *ap)
0911 {
0912     u32 *gscr = ap->link.device->gscr;
0913 
0914     sil24_config_pmp(ap, 1);
0915     sil24_init_port(ap);
0916 
0917     if (sata_pmp_gscr_vendor(gscr) == 0x11ab &&
0918         sata_pmp_gscr_devid(gscr) == 0x4140) {
0919         ata_port_info(ap,
0920             "disabling NCQ support due to sil24-mv4140 quirk\n");
0921         ap->flags &= ~ATA_FLAG_NCQ;
0922     }
0923 }
0924 
0925 static void sil24_pmp_detach(struct ata_port *ap)
0926 {
0927     sil24_init_port(ap);
0928     sil24_config_pmp(ap, 0);
0929 
0930     ap->flags |= ATA_FLAG_NCQ;
0931 }
0932 
0933 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
0934                    unsigned long deadline)
0935 {
0936     int rc;
0937 
0938     rc = sil24_init_port(link->ap);
0939     if (rc) {
0940         ata_link_err(link, "hardreset failed (port not ready)\n");
0941         return rc;
0942     }
0943 
0944     return sata_std_hardreset(link, class, deadline);
0945 }
0946 
0947 static void sil24_freeze(struct ata_port *ap)
0948 {
0949     void __iomem *port = sil24_port_base(ap);
0950 
0951     /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
0952      * PORT_IRQ_ENABLE instead.
0953      */
0954     writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
0955 }
0956 
0957 static void sil24_thaw(struct ata_port *ap)
0958 {
0959     void __iomem *port = sil24_port_base(ap);
0960     u32 tmp;
0961 
0962     /* clear IRQ */
0963     tmp = readl(port + PORT_IRQ_STAT);
0964     writel(tmp, port + PORT_IRQ_STAT);
0965 
0966     /* turn IRQ back on */
0967     writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
0968 }
0969 
0970 static void sil24_error_intr(struct ata_port *ap)
0971 {
0972     void __iomem *port = sil24_port_base(ap);
0973     struct sil24_port_priv *pp = ap->private_data;
0974     struct ata_queued_cmd *qc = NULL;
0975     struct ata_link *link;
0976     struct ata_eh_info *ehi;
0977     int abort = 0, freeze = 0;
0978     u32 irq_stat;
0979 
0980     /* on error, we need to clear IRQ explicitly */
0981     irq_stat = readl(port + PORT_IRQ_STAT);
0982     writel(irq_stat, port + PORT_IRQ_STAT);
0983 
0984     /* first, analyze and record host port events */
0985     link = &ap->link;
0986     ehi = &link->eh_info;
0987     ata_ehi_clear_desc(ehi);
0988 
0989     ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
0990 
0991     if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
0992         ata_ehi_push_desc(ehi, "SDB notify");
0993         sata_async_notification(ap);
0994     }
0995 
0996     if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
0997         ata_ehi_hotplugged(ehi);
0998         ata_ehi_push_desc(ehi, "%s",
0999                   irq_stat & PORT_IRQ_PHYRDY_CHG ?
1000                   "PHY RDY changed" : "device exchanged");
1001         freeze = 1;
1002     }
1003 
1004     if (irq_stat & PORT_IRQ_UNK_FIS) {
1005         ehi->err_mask |= AC_ERR_HSM;
1006         ehi->action |= ATA_EH_RESET;
1007         ata_ehi_push_desc(ehi, "unknown FIS");
1008         freeze = 1;
1009     }
1010 
1011     /* deal with command error */
1012     if (irq_stat & PORT_IRQ_ERROR) {
1013         const struct sil24_cerr_info *ci = NULL;
1014         unsigned int err_mask = 0, action = 0;
1015         u32 context, cerr;
1016         int pmp;
1017 
1018         abort = 1;
1019 
1020         /* DMA Context Switch Failure in Port Multiplier Mode
1021          * errata.  If we have active commands to 3 or more
1022          * devices, any error condition on active devices can
1023          * corrupt DMA context switching.
1024          */
1025         if (ap->nr_active_links >= 3) {
1026             ehi->err_mask |= AC_ERR_OTHER;
1027             ehi->action |= ATA_EH_RESET;
1028             ata_ehi_push_desc(ehi, "PMP DMA CS errata");
1029             pp->do_port_rst = 1;
1030             freeze = 1;
1031         }
1032 
1033         /* find out the offending link and qc */
1034         if (sata_pmp_attached(ap)) {
1035             context = readl(port + PORT_CONTEXT);
1036             pmp = (context >> 5) & 0xf;
1037 
1038             if (pmp < ap->nr_pmp_links) {
1039                 link = &ap->pmp_link[pmp];
1040                 ehi = &link->eh_info;
1041                 qc = ata_qc_from_tag(ap, link->active_tag);
1042 
1043                 ata_ehi_clear_desc(ehi);
1044                 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1045                           irq_stat);
1046             } else {
1047                 err_mask |= AC_ERR_HSM;
1048                 action |= ATA_EH_RESET;
1049                 freeze = 1;
1050             }
1051         } else
1052             qc = ata_qc_from_tag(ap, link->active_tag);
1053 
1054         /* analyze CMD_ERR */
1055         cerr = readl(port + PORT_CMD_ERR);
1056         if (cerr < ARRAY_SIZE(sil24_cerr_db))
1057             ci = &sil24_cerr_db[cerr];
1058 
1059         if (ci && ci->desc) {
1060             err_mask |= ci->err_mask;
1061             action |= ci->action;
1062             if (action & ATA_EH_RESET)
1063                 freeze = 1;
1064             ata_ehi_push_desc(ehi, "%s", ci->desc);
1065         } else {
1066             err_mask |= AC_ERR_OTHER;
1067             action |= ATA_EH_RESET;
1068             freeze = 1;
1069             ata_ehi_push_desc(ehi, "unknown command error %d",
1070                       cerr);
1071         }
1072 
1073         /* record error info */
1074         if (qc)
1075             qc->err_mask |= err_mask;
1076         else
1077             ehi->err_mask |= err_mask;
1078 
1079         ehi->action |= action;
1080 
1081         /* if PMP, resume */
1082         if (sata_pmp_attached(ap))
1083             writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
1084     }
1085 
1086     /* freeze or abort */
1087     if (freeze)
1088         ata_port_freeze(ap);
1089     else if (abort) {
1090         if (qc)
1091             ata_link_abort(qc->dev->link);
1092         else
1093             ata_port_abort(ap);
1094     }
1095 }
1096 
1097 static inline void sil24_host_intr(struct ata_port *ap)
1098 {
1099     void __iomem *port = sil24_port_base(ap);
1100     u32 slot_stat, qc_active;
1101     int rc;
1102 
1103     /* If PCIX_IRQ_WOC, there's an inherent race window between
1104      * clearing IRQ pending status and reading PORT_SLOT_STAT
1105      * which may cause spurious interrupts afterwards.  This is
1106      * unavoidable and much better than losing interrupts which
1107      * happens if IRQ pending is cleared after reading
1108      * PORT_SLOT_STAT.
1109      */
1110     if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1111         writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1112 
1113     slot_stat = readl(port + PORT_SLOT_STAT);
1114 
1115     if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1116         sil24_error_intr(ap);
1117         return;
1118     }
1119 
1120     qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1121     rc = ata_qc_complete_multiple(ap, qc_active);
1122     if (rc > 0)
1123         return;
1124     if (rc < 0) {
1125         struct ata_eh_info *ehi = &ap->link.eh_info;
1126         ehi->err_mask |= AC_ERR_HSM;
1127         ehi->action |= ATA_EH_RESET;
1128         ata_port_freeze(ap);
1129         return;
1130     }
1131 
1132     /* spurious interrupts are expected if PCIX_IRQ_WOC */
1133     if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
1134         ata_port_info(ap,
1135             "spurious interrupt (slot_stat 0x%x active_tag %d sactive 0x%x)\n",
1136             slot_stat, ap->link.active_tag, ap->link.sactive);
1137 }
1138 
1139 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1140 {
1141     struct ata_host *host = dev_instance;
1142     void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1143     unsigned handled = 0;
1144     u32 status;
1145     int i;
1146 
1147     status = readl(host_base + HOST_IRQ_STAT);
1148 
1149     if (status == 0xffffffff) {
1150         dev_err(host->dev, "IRQ status == 0xffffffff, "
1151             "PCI fault or device removal?\n");
1152         goto out;
1153     }
1154 
1155     if (!(status & IRQ_STAT_4PORTS))
1156         goto out;
1157 
1158     spin_lock(&host->lock);
1159 
1160     for (i = 0; i < host->n_ports; i++)
1161         if (status & (1 << i)) {
1162             sil24_host_intr(host->ports[i]);
1163             handled++;
1164         }
1165 
1166     spin_unlock(&host->lock);
1167  out:
1168     return IRQ_RETVAL(handled);
1169 }
1170 
1171 static void sil24_error_handler(struct ata_port *ap)
1172 {
1173     struct sil24_port_priv *pp = ap->private_data;
1174 
1175     if (sil24_init_port(ap))
1176         ata_eh_freeze_port(ap);
1177 
1178     sata_pmp_error_handler(ap);
1179 
1180     pp->do_port_rst = 0;
1181 }
1182 
1183 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1184 {
1185     struct ata_port *ap = qc->ap;
1186 
1187     /* make DMA engine forget about the failed command */
1188     if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1189         ata_eh_freeze_port(ap);
1190 }
1191 
1192 static int sil24_port_start(struct ata_port *ap)
1193 {
1194     struct device *dev = ap->host->dev;
1195     struct sil24_port_priv *pp;
1196     union sil24_cmd_block *cb;
1197     size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
1198     dma_addr_t cb_dma;
1199 
1200     pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1201     if (!pp)
1202         return -ENOMEM;
1203 
1204     cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1205     if (!cb)
1206         return -ENOMEM;
1207 
1208     pp->cmd_block = cb;
1209     pp->cmd_block_dma = cb_dma;
1210 
1211     ap->private_data = pp;
1212 
1213     ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1214     ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port");
1215 
1216     return 0;
1217 }
1218 
1219 static void sil24_init_controller(struct ata_host *host)
1220 {
1221     void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1222     u32 tmp;
1223     int i;
1224 
1225     /* GPIO off */
1226     writel(0, host_base + HOST_FLASH_CMD);
1227 
1228     /* clear global reset & mask interrupts during initialization */
1229     writel(0, host_base + HOST_CTRL);
1230 
1231     /* init ports */
1232     for (i = 0; i < host->n_ports; i++) {
1233         struct ata_port *ap = host->ports[i];
1234         void __iomem *port = sil24_port_base(ap);
1235 
1236 
1237         /* Initial PHY setting */
1238         writel(0x20c, port + PORT_PHY_CFG);
1239 
1240         /* Clear port RST */
1241         tmp = readl(port + PORT_CTRL_STAT);
1242         if (tmp & PORT_CS_PORT_RST) {
1243             writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1244             tmp = ata_wait_register(NULL, port + PORT_CTRL_STAT,
1245                         PORT_CS_PORT_RST,
1246                         PORT_CS_PORT_RST, 10, 100);
1247             if (tmp & PORT_CS_PORT_RST)
1248                 dev_err(host->dev,
1249                     "failed to clear port RST\n");
1250         }
1251 
1252         /* configure port */
1253         sil24_config_port(ap);
1254     }
1255 
1256     /* Turn on interrupts */
1257     writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1258 }
1259 
1260 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1261 {
1262     extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
1263     struct ata_port_info pi = sil24_port_info[ent->driver_data];
1264     const struct ata_port_info *ppi[] = { &pi, NULL };
1265     void __iomem * const *iomap;
1266     struct ata_host *host;
1267     int rc;
1268     u32 tmp;
1269 
1270     /* cause link error if sil24_cmd_block is sized wrongly */
1271     if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
1272         __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
1273 
1274     ata_print_version_once(&pdev->dev, DRV_VERSION);
1275 
1276     /* acquire resources */
1277     rc = pcim_enable_device(pdev);
1278     if (rc)
1279         return rc;
1280 
1281     rc = pcim_iomap_regions(pdev,
1282                 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1283                 DRV_NAME);
1284     if (rc)
1285         return rc;
1286     iomap = pcim_iomap_table(pdev);
1287 
1288     /* apply workaround for completion IRQ loss on PCI-X errata */
1289     if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1290         tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1291         if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1292             dev_info(&pdev->dev,
1293                  "Applying completion IRQ loss on PCI-X errata fix\n");
1294         else
1295             pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1296     }
1297 
1298     /* allocate and fill host */
1299     host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1300                     SIL24_FLAG2NPORTS(ppi[0]->flags));
1301     if (!host)
1302         return -ENOMEM;
1303     host->iomap = iomap;
1304 
1305     /* configure and activate the device */
1306     rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1307     if (rc) {
1308         dev_err(&pdev->dev, "DMA enable failed\n");
1309         return rc;
1310     }
1311 
1312     /* Set max read request size to 4096.  This slightly increases
1313      * write throughput for pci-e variants.
1314      */
1315     pcie_set_readrq(pdev, 4096);
1316 
1317     sil24_init_controller(host);
1318 
1319     if (sata_sil24_msi && !pci_enable_msi(pdev)) {
1320         dev_info(&pdev->dev, "Using MSI\n");
1321         pci_intx(pdev, 0);
1322     }
1323 
1324     pci_set_master(pdev);
1325     return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1326                  &sil24_sht);
1327 }
1328 
1329 #ifdef CONFIG_PM_SLEEP
1330 static int sil24_pci_device_resume(struct pci_dev *pdev)
1331 {
1332     struct ata_host *host = pci_get_drvdata(pdev);
1333     void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1334     int rc;
1335 
1336     rc = ata_pci_device_do_resume(pdev);
1337     if (rc)
1338         return rc;
1339 
1340     if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1341         writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1342 
1343     sil24_init_controller(host);
1344 
1345     ata_host_resume(host);
1346 
1347     return 0;
1348 }
1349 #endif
1350 
1351 #ifdef CONFIG_PM
1352 static int sil24_port_resume(struct ata_port *ap)
1353 {
1354     sil24_config_pmp(ap, ap->nr_pmp_links);
1355     return 0;
1356 }
1357 #endif
1358 
1359 module_pci_driver(sil24_pci_driver);
1360 
1361 MODULE_AUTHOR("Tejun Heo");
1362 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1363 MODULE_LICENSE("GPL");
1364 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
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