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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  sata_promise.c - Promise SATA
0004  *
0005  *  Maintained by:  Tejun Heo <tj@kernel.org>
0006  *          Mikael Pettersson
0007  *              Please ALWAYS copy linux-ide@vger.kernel.org
0008  *          on emails.
0009  *
0010  *  Copyright 2003-2004 Red Hat, Inc.
0011  *
0012  *  libata documentation is available via 'make {ps|pdf}docs',
0013  *  as Documentation/driver-api/libata.rst
0014  *
0015  *  Hardware information only available under NDA.
0016  */
0017 
0018 #include <linux/kernel.h>
0019 #include <linux/module.h>
0020 #include <linux/gfp.h>
0021 #include <linux/pci.h>
0022 #include <linux/blkdev.h>
0023 #include <linux/delay.h>
0024 #include <linux/interrupt.h>
0025 #include <linux/device.h>
0026 #include <scsi/scsi.h>
0027 #include <scsi/scsi_host.h>
0028 #include <scsi/scsi_cmnd.h>
0029 #include <linux/libata.h>
0030 #include "sata_promise.h"
0031 
0032 #define DRV_NAME    "sata_promise"
0033 #define DRV_VERSION "2.12"
0034 
0035 enum {
0036     PDC_MAX_PORTS       = 4,
0037     PDC_MMIO_BAR        = 3,
0038     PDC_MAX_PRD     = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
0039 
0040     /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
0041     PDC_INT_SEQMASK     = 0x40, /* Mask of asserted SEQ INTs */
0042     PDC_FLASH_CTL       = 0x44, /* Flash control register */
0043     PDC_PCI_CTL     = 0x48, /* PCI control/status reg */
0044     PDC_SATA_PLUG_CSR   = 0x6C, /* SATA Plug control/status reg */
0045     PDC2_SATA_PLUG_CSR  = 0x60, /* SATAII Plug control/status reg */
0046     PDC_TBG_MODE        = 0x41C, /* TBG mode (not SATAII) */
0047     PDC_SLEW_CTL        = 0x470, /* slew rate control reg (not SATAII) */
0048 
0049     /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
0050     PDC_FEATURE     = 0x04, /* Feature/Error reg (per port) */
0051     PDC_SECTOR_COUNT    = 0x08, /* Sector count reg (per port) */
0052     PDC_SECTOR_NUMBER   = 0x0C, /* Sector number reg (per port) */
0053     PDC_CYLINDER_LOW    = 0x10, /* Cylinder low reg (per port) */
0054     PDC_CYLINDER_HIGH   = 0x14, /* Cylinder high reg (per port) */
0055     PDC_DEVICE      = 0x18, /* Device/Head reg (per port) */
0056     PDC_COMMAND     = 0x1C, /* Command/status reg (per port) */
0057     PDC_ALTSTATUS       = 0x38, /* Alternate-status/device-control reg (per port) */
0058     PDC_PKT_SUBMIT      = 0x40, /* Command packet pointer addr */
0059     PDC_GLOBAL_CTL      = 0x48, /* Global control/status (per port) */
0060     PDC_CTLSTAT     = 0x60, /* IDE control and status (per port) */
0061 
0062     /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
0063     PDC_SATA_ERROR      = 0x04,
0064     PDC_PHYMODE4        = 0x14,
0065     PDC_LINK_LAYER_ERRORS   = 0x6C,
0066     PDC_FPDMA_CTLSTAT   = 0xD8,
0067     PDC_INTERNAL_DEBUG_1    = 0xF8, /* also used for PATA */
0068     PDC_INTERNAL_DEBUG_2    = 0xFC, /* also used for PATA */
0069 
0070     /* PDC_FPDMA_CTLSTAT bit definitions */
0071     PDC_FPDMA_CTLSTAT_RESET         = 1 << 3,
0072     PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10,
0073     PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG    = 1 << 11,
0074 
0075     /* PDC_GLOBAL_CTL bit definitions */
0076     PDC_PH_ERR      = (1 <<  8), /* PCI error while loading packet */
0077     PDC_SH_ERR      = (1 <<  9), /* PCI error while loading S/G table */
0078     PDC_DH_ERR      = (1 << 10), /* PCI error while loading data */
0079     PDC2_HTO_ERR        = (1 << 12), /* host bus timeout */
0080     PDC2_ATA_HBA_ERR    = (1 << 13), /* error during SATA DATA FIS transmission */
0081     PDC2_ATA_DMA_CNT_ERR    = (1 << 14), /* DMA DATA FIS size differs from S/G count */
0082     PDC_OVERRUN_ERR     = (1 << 19), /* S/G byte count larger than HD requires */
0083     PDC_UNDERRUN_ERR    = (1 << 20), /* S/G byte count less than HD requires */
0084     PDC_DRIVE_ERR       = (1 << 21), /* drive error */
0085     PDC_PCI_SYS_ERR     = (1 << 22), /* PCI system error */
0086     PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
0087     PDC1_ERR_MASK       = PDC1_PCI_PARITY_ERR,
0088     PDC2_ERR_MASK       = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
0089                   PDC2_ATA_DMA_CNT_ERR,
0090     PDC_ERR_MASK        = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
0091                   PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
0092                   PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
0093                   PDC1_ERR_MASK | PDC2_ERR_MASK,
0094 
0095     board_2037x     = 0,    /* FastTrak S150 TX2plus */
0096     board_2037x_pata    = 1,    /* FastTrak S150 TX2plus PATA port */
0097     board_20319     = 2,    /* FastTrak S150 TX4 */
0098     board_20619     = 3,    /* FastTrak TX4000 */
0099     board_2057x     = 4,    /* SATAII150 Tx2plus */
0100     board_2057x_pata    = 5,    /* SATAII150 Tx2plus PATA port */
0101     board_40518     = 6,    /* SATAII150 Tx4 */
0102 
0103     PDC_HAS_PATA        = (1 << 1), /* PDC20375/20575 has PATA */
0104 
0105     /* Sequence counter control registers bit definitions */
0106     PDC_SEQCNTRL_INT_MASK   = (1 << 5), /* Sequence Interrupt Mask */
0107 
0108     /* Feature register values */
0109     PDC_FEATURE_ATAPI_PIO   = 0x00, /* ATAPI data xfer by PIO */
0110     PDC_FEATURE_ATAPI_DMA   = 0x01, /* ATAPI data xfer by DMA */
0111 
0112     /* Device/Head register values */
0113     PDC_DEVICE_SATA     = 0xE0, /* Device/Head value for SATA devices */
0114 
0115     /* PDC_CTLSTAT bit definitions */
0116     PDC_DMA_ENABLE      = (1 << 7),
0117     PDC_IRQ_DISABLE     = (1 << 10),
0118     PDC_RESET       = (1 << 11), /* HDMA reset */
0119 
0120     PDC_COMMON_FLAGS    = ATA_FLAG_PIO_POLLING,
0121 
0122     /* ap->flags bits */
0123     PDC_FLAG_GEN_II     = (1 << 24),
0124     PDC_FLAG_SATA_PATA  = (1 << 25), /* supports SATA + PATA */
0125     PDC_FLAG_4_PORTS    = (1 << 26), /* 4 ports */
0126 };
0127 
0128 struct pdc_port_priv {
0129     u8          *pkt;
0130     dma_addr_t      pkt_dma;
0131 };
0132 
0133 struct pdc_host_priv {
0134     spinlock_t hard_reset_lock;
0135 };
0136 
0137 static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
0138 static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
0139 static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
0140 static int pdc_common_port_start(struct ata_port *ap);
0141 static int pdc_sata_port_start(struct ata_port *ap);
0142 static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc);
0143 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
0144 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
0145 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
0146 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
0147 static void pdc_irq_clear(struct ata_port *ap);
0148 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
0149 static void pdc_freeze(struct ata_port *ap);
0150 static void pdc_sata_freeze(struct ata_port *ap);
0151 static void pdc_thaw(struct ata_port *ap);
0152 static void pdc_sata_thaw(struct ata_port *ap);
0153 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
0154                   unsigned long deadline);
0155 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
0156                   unsigned long deadline);
0157 static void pdc_error_handler(struct ata_port *ap);
0158 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
0159 static int pdc_pata_cable_detect(struct ata_port *ap);
0160 
0161 static struct scsi_host_template pdc_ata_sht = {
0162     ATA_BASE_SHT(DRV_NAME),
0163     .sg_tablesize       = PDC_MAX_PRD,
0164     .dma_boundary       = ATA_DMA_BOUNDARY,
0165 };
0166 
0167 static const struct ata_port_operations pdc_common_ops = {
0168     .inherits       = &ata_sff_port_ops,
0169 
0170     .sff_tf_load        = pdc_tf_load_mmio,
0171     .sff_exec_command   = pdc_exec_command_mmio,
0172     .check_atapi_dma    = pdc_check_atapi_dma,
0173     .qc_prep        = pdc_qc_prep,
0174     .qc_issue       = pdc_qc_issue,
0175 
0176     .sff_irq_clear      = pdc_irq_clear,
0177     .lost_interrupt     = ATA_OP_NULL,
0178 
0179     .post_internal_cmd  = pdc_post_internal_cmd,
0180     .error_handler      = pdc_error_handler,
0181 };
0182 
0183 static struct ata_port_operations pdc_sata_ops = {
0184     .inherits       = &pdc_common_ops,
0185     .cable_detect       = ata_cable_sata,
0186     .freeze         = pdc_sata_freeze,
0187     .thaw           = pdc_sata_thaw,
0188     .scr_read       = pdc_sata_scr_read,
0189     .scr_write      = pdc_sata_scr_write,
0190     .port_start     = pdc_sata_port_start,
0191     .hardreset      = pdc_sata_hardreset,
0192 };
0193 
0194 /* First-generation chips need a more restrictive ->check_atapi_dma op,
0195    and ->freeze/thaw that ignore the hotplug controls. */
0196 static struct ata_port_operations pdc_old_sata_ops = {
0197     .inherits       = &pdc_sata_ops,
0198     .freeze         = pdc_freeze,
0199     .thaw           = pdc_thaw,
0200     .check_atapi_dma    = pdc_old_sata_check_atapi_dma,
0201 };
0202 
0203 static struct ata_port_operations pdc_pata_ops = {
0204     .inherits       = &pdc_common_ops,
0205     .cable_detect       = pdc_pata_cable_detect,
0206     .freeze         = pdc_freeze,
0207     .thaw           = pdc_thaw,
0208     .port_start     = pdc_common_port_start,
0209     .softreset      = pdc_pata_softreset,
0210 };
0211 
0212 static const struct ata_port_info pdc_port_info[] = {
0213     [board_2037x] =
0214     {
0215         .flags      = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
0216                   PDC_FLAG_SATA_PATA,
0217         .pio_mask   = ATA_PIO4,
0218         .mwdma_mask = ATA_MWDMA2,
0219         .udma_mask  = ATA_UDMA6,
0220         .port_ops   = &pdc_old_sata_ops,
0221     },
0222 
0223     [board_2037x_pata] =
0224     {
0225         .flags      = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
0226         .pio_mask   = ATA_PIO4,
0227         .mwdma_mask = ATA_MWDMA2,
0228         .udma_mask  = ATA_UDMA6,
0229         .port_ops   = &pdc_pata_ops,
0230     },
0231 
0232     [board_20319] =
0233     {
0234         .flags      = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
0235                   PDC_FLAG_4_PORTS,
0236         .pio_mask   = ATA_PIO4,
0237         .mwdma_mask = ATA_MWDMA2,
0238         .udma_mask  = ATA_UDMA6,
0239         .port_ops   = &pdc_old_sata_ops,
0240     },
0241 
0242     [board_20619] =
0243     {
0244         .flags      = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
0245                   PDC_FLAG_4_PORTS,
0246         .pio_mask   = ATA_PIO4,
0247         .mwdma_mask = ATA_MWDMA2,
0248         .udma_mask  = ATA_UDMA6,
0249         .port_ops   = &pdc_pata_ops,
0250     },
0251 
0252     [board_2057x] =
0253     {
0254         .flags      = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
0255                   PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
0256         .pio_mask   = ATA_PIO4,
0257         .mwdma_mask = ATA_MWDMA2,
0258         .udma_mask  = ATA_UDMA6,
0259         .port_ops   = &pdc_sata_ops,
0260     },
0261 
0262     [board_2057x_pata] =
0263     {
0264         .flags      = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
0265                   PDC_FLAG_GEN_II,
0266         .pio_mask   = ATA_PIO4,
0267         .mwdma_mask = ATA_MWDMA2,
0268         .udma_mask  = ATA_UDMA6,
0269         .port_ops   = &pdc_pata_ops,
0270     },
0271 
0272     [board_40518] =
0273     {
0274         .flags      = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
0275                   PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
0276         .pio_mask   = ATA_PIO4,
0277         .mwdma_mask = ATA_MWDMA2,
0278         .udma_mask  = ATA_UDMA6,
0279         .port_ops   = &pdc_sata_ops,
0280     },
0281 };
0282 
0283 static const struct pci_device_id pdc_ata_pci_tbl[] = {
0284     { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
0285     { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
0286     { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
0287     { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
0288     { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
0289     { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
0290     { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
0291     { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
0292     { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
0293     { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
0294 
0295     { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
0296     { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
0297     { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
0298     { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
0299     { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
0300     { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
0301 
0302     { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
0303 
0304     { } /* terminate list */
0305 };
0306 
0307 static struct pci_driver pdc_ata_pci_driver = {
0308     .name           = DRV_NAME,
0309     .id_table       = pdc_ata_pci_tbl,
0310     .probe          = pdc_ata_init_one,
0311     .remove         = ata_pci_remove_one,
0312 };
0313 
0314 static int pdc_common_port_start(struct ata_port *ap)
0315 {
0316     struct device *dev = ap->host->dev;
0317     struct pdc_port_priv *pp;
0318     int rc;
0319 
0320     /* we use the same prd table as bmdma, allocate it */
0321     rc = ata_bmdma_port_start(ap);
0322     if (rc)
0323         return rc;
0324 
0325     pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
0326     if (!pp)
0327         return -ENOMEM;
0328 
0329     pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
0330     if (!pp->pkt)
0331         return -ENOMEM;
0332 
0333     ap->private_data = pp;
0334 
0335     return 0;
0336 }
0337 
0338 static int pdc_sata_port_start(struct ata_port *ap)
0339 {
0340     int rc;
0341 
0342     rc = pdc_common_port_start(ap);
0343     if (rc)
0344         return rc;
0345 
0346     /* fix up PHYMODE4 align timing */
0347     if (ap->flags & PDC_FLAG_GEN_II) {
0348         void __iomem *sata_mmio = ap->ioaddr.scr_addr;
0349         unsigned int tmp;
0350 
0351         tmp = readl(sata_mmio + PDC_PHYMODE4);
0352         tmp = (tmp & ~3) | 1;   /* set bits 1:0 = 0:1 */
0353         writel(tmp, sata_mmio + PDC_PHYMODE4);
0354     }
0355 
0356     return 0;
0357 }
0358 
0359 static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap)
0360 {
0361     void __iomem *sata_mmio = ap->ioaddr.scr_addr;
0362     u32 tmp;
0363 
0364     tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT);
0365     tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG;
0366     tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG;
0367 
0368     /* It's not allowed to write to the entire FPDMA_CTLSTAT register
0369        when NCQ is running. So do a byte-sized write to bits 10 and 11. */
0370     writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1);
0371     readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1); /* flush */
0372 }
0373 
0374 static void pdc_fpdma_reset(struct ata_port *ap)
0375 {
0376     void __iomem *sata_mmio = ap->ioaddr.scr_addr;
0377     u8 tmp;
0378 
0379     tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT);
0380     tmp &= 0x7F;
0381     tmp |= PDC_FPDMA_CTLSTAT_RESET;
0382     writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
0383     readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
0384     udelay(100);
0385     tmp &= ~PDC_FPDMA_CTLSTAT_RESET;
0386     writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
0387     readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
0388 
0389     pdc_fpdma_clear_interrupt_flag(ap);
0390 }
0391 
0392 static void pdc_not_at_command_packet_phase(struct ata_port *ap)
0393 {
0394     void __iomem *sata_mmio = ap->ioaddr.scr_addr;
0395     unsigned int i;
0396     u32 tmp;
0397 
0398     /* check not at ASIC packet command phase */
0399     for (i = 0; i < 100; ++i) {
0400         writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1);
0401         tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2);
0402         if ((tmp & 0xF) != 1)
0403             break;
0404         udelay(100);
0405     }
0406 }
0407 
0408 static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap)
0409 {
0410     void __iomem *sata_mmio = ap->ioaddr.scr_addr;
0411 
0412     writel(0xffffffff, sata_mmio + PDC_SATA_ERROR);
0413     writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS);
0414 }
0415 
0416 static void pdc_reset_port(struct ata_port *ap)
0417 {
0418     void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
0419     unsigned int i;
0420     u32 tmp;
0421 
0422     if (ap->flags & PDC_FLAG_GEN_II)
0423         pdc_not_at_command_packet_phase(ap);
0424 
0425     tmp = readl(ata_ctlstat_mmio);
0426     tmp |= PDC_RESET;
0427     writel(tmp, ata_ctlstat_mmio);
0428 
0429     for (i = 11; i > 0; i--) {
0430         tmp = readl(ata_ctlstat_mmio);
0431         if (tmp & PDC_RESET)
0432             break;
0433 
0434         udelay(100);
0435 
0436         tmp |= PDC_RESET;
0437         writel(tmp, ata_ctlstat_mmio);
0438     }
0439 
0440     tmp &= ~PDC_RESET;
0441     writel(tmp, ata_ctlstat_mmio);
0442     readl(ata_ctlstat_mmio);    /* flush */
0443 
0444     if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) {
0445         pdc_fpdma_reset(ap);
0446         pdc_clear_internal_debug_record_error_register(ap);
0447     }
0448 }
0449 
0450 static int pdc_pata_cable_detect(struct ata_port *ap)
0451 {
0452     u8 tmp;
0453     void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
0454 
0455     tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
0456     if (tmp & 0x01)
0457         return ATA_CBL_PATA40;
0458     return ATA_CBL_PATA80;
0459 }
0460 
0461 static int pdc_sata_scr_read(struct ata_link *link,
0462                  unsigned int sc_reg, u32 *val)
0463 {
0464     if (sc_reg > SCR_CONTROL)
0465         return -EINVAL;
0466     *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
0467     return 0;
0468 }
0469 
0470 static int pdc_sata_scr_write(struct ata_link *link,
0471                   unsigned int sc_reg, u32 val)
0472 {
0473     if (sc_reg > SCR_CONTROL)
0474         return -EINVAL;
0475     writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
0476     return 0;
0477 }
0478 
0479 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
0480 {
0481     struct ata_port *ap = qc->ap;
0482     dma_addr_t sg_table = ap->bmdma_prd_dma;
0483     unsigned int cdb_len = qc->dev->cdb_len;
0484     u8 *cdb = qc->cdb;
0485     struct pdc_port_priv *pp = ap->private_data;
0486     u8 *buf = pp->pkt;
0487     __le32 *buf32 = (__le32 *) buf;
0488     unsigned int dev_sel, feature;
0489 
0490     /* set control bits (byte 0), zero delay seq id (byte 3),
0491      * and seq id (byte 2)
0492      */
0493     switch (qc->tf.protocol) {
0494     case ATAPI_PROT_DMA:
0495         if (!(qc->tf.flags & ATA_TFLAG_WRITE))
0496             buf32[0] = cpu_to_le32(PDC_PKT_READ);
0497         else
0498             buf32[0] = 0;
0499         break;
0500     case ATAPI_PROT_NODATA:
0501         buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
0502         break;
0503     default:
0504         BUG();
0505         break;
0506     }
0507     buf32[1] = cpu_to_le32(sg_table);   /* S/G table addr */
0508     buf32[2] = 0;               /* no next-packet */
0509 
0510     /* select drive */
0511     if (sata_scr_valid(&ap->link))
0512         dev_sel = PDC_DEVICE_SATA;
0513     else
0514         dev_sel = qc->tf.device;
0515 
0516     buf[12] = (1 << 5) | ATA_REG_DEVICE;
0517     buf[13] = dev_sel;
0518     buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
0519     buf[15] = dev_sel; /* once more, waiting for BSY to clear */
0520 
0521     buf[16] = (1 << 5) | ATA_REG_NSECT;
0522     buf[17] = qc->tf.nsect;
0523     buf[18] = (1 << 5) | ATA_REG_LBAL;
0524     buf[19] = qc->tf.lbal;
0525 
0526     /* set feature and byte counter registers */
0527     if (qc->tf.protocol != ATAPI_PROT_DMA)
0528         feature = PDC_FEATURE_ATAPI_PIO;
0529     else
0530         feature = PDC_FEATURE_ATAPI_DMA;
0531 
0532     buf[20] = (1 << 5) | ATA_REG_FEATURE;
0533     buf[21] = feature;
0534     buf[22] = (1 << 5) | ATA_REG_BYTEL;
0535     buf[23] = qc->tf.lbam;
0536     buf[24] = (1 << 5) | ATA_REG_BYTEH;
0537     buf[25] = qc->tf.lbah;
0538 
0539     /* send ATAPI packet command 0xA0 */
0540     buf[26] = (1 << 5) | ATA_REG_CMD;
0541     buf[27] = qc->tf.command;
0542 
0543     /* select drive and check DRQ */
0544     buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
0545     buf[29] = dev_sel;
0546 
0547     /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
0548     BUG_ON(cdb_len & ~0x1E);
0549 
0550     /* append the CDB as the final part */
0551     buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
0552     memcpy(buf+31, cdb, cdb_len);
0553 }
0554 
0555 /**
0556  *  pdc_fill_sg - Fill PCI IDE PRD table
0557  *  @qc: Metadata associated with taskfile to be transferred
0558  *
0559  *  Fill PCI IDE PRD (scatter-gather) table with segments
0560  *  associated with the current disk command.
0561  *  Make sure hardware does not choke on it.
0562  *
0563  *  LOCKING:
0564  *  spin_lock_irqsave(host lock)
0565  *
0566  */
0567 static void pdc_fill_sg(struct ata_queued_cmd *qc)
0568 {
0569     struct ata_port *ap = qc->ap;
0570     struct ata_bmdma_prd *prd = ap->bmdma_prd;
0571     struct scatterlist *sg;
0572     const u32 SG_COUNT_ASIC_BUG = 41*4;
0573     unsigned int si, idx;
0574     u32 len;
0575 
0576     if (!(qc->flags & ATA_QCFLAG_DMAMAP))
0577         return;
0578 
0579     idx = 0;
0580     for_each_sg(qc->sg, sg, qc->n_elem, si) {
0581         u32 addr, offset;
0582         u32 sg_len;
0583 
0584         /* determine if physical DMA addr spans 64K boundary.
0585          * Note h/w doesn't support 64-bit, so we unconditionally
0586          * truncate dma_addr_t to u32.
0587          */
0588         addr = (u32) sg_dma_address(sg);
0589         sg_len = sg_dma_len(sg);
0590 
0591         while (sg_len) {
0592             offset = addr & 0xffff;
0593             len = sg_len;
0594             if ((offset + sg_len) > 0x10000)
0595                 len = 0x10000 - offset;
0596 
0597             prd[idx].addr = cpu_to_le32(addr);
0598             prd[idx].flags_len = cpu_to_le32(len & 0xffff);
0599             ata_port_dbg(ap, "PRD[%u] = (0x%X, 0x%X)\n",
0600                      idx, addr, len);
0601 
0602             idx++;
0603             sg_len -= len;
0604             addr += len;
0605         }
0606     }
0607 
0608     len = le32_to_cpu(prd[idx - 1].flags_len);
0609 
0610     if (len > SG_COUNT_ASIC_BUG) {
0611         u32 addr;
0612 
0613         addr = le32_to_cpu(prd[idx - 1].addr);
0614         prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
0615         ata_port_dbg(ap, "PRD[%u] = (0x%X, 0x%X)\n",
0616                  idx - 1, addr, SG_COUNT_ASIC_BUG);
0617 
0618         addr = addr + len - SG_COUNT_ASIC_BUG;
0619         len = SG_COUNT_ASIC_BUG;
0620         prd[idx].addr = cpu_to_le32(addr);
0621         prd[idx].flags_len = cpu_to_le32(len);
0622         ata_port_dbg(ap, "PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
0623 
0624         idx++;
0625     }
0626 
0627     prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
0628 }
0629 
0630 static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc)
0631 {
0632     struct pdc_port_priv *pp = qc->ap->private_data;
0633     unsigned int i;
0634 
0635     switch (qc->tf.protocol) {
0636     case ATA_PROT_DMA:
0637         pdc_fill_sg(qc);
0638         fallthrough;
0639     case ATA_PROT_NODATA:
0640         i = pdc_pkt_header(&qc->tf, qc->ap->bmdma_prd_dma,
0641                    qc->dev->devno, pp->pkt);
0642         if (qc->tf.flags & ATA_TFLAG_LBA48)
0643             i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
0644         else
0645             i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
0646         pdc_pkt_footer(&qc->tf, pp->pkt, i);
0647         break;
0648     case ATAPI_PROT_PIO:
0649         pdc_fill_sg(qc);
0650         break;
0651     case ATAPI_PROT_DMA:
0652         pdc_fill_sg(qc);
0653         fallthrough;
0654     case ATAPI_PROT_NODATA:
0655         pdc_atapi_pkt(qc);
0656         break;
0657     default:
0658         break;
0659     }
0660 
0661     return AC_ERR_OK;
0662 }
0663 
0664 static int pdc_is_sataii_tx4(unsigned long flags)
0665 {
0666     const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
0667     return (flags & mask) == mask;
0668 }
0669 
0670 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
0671                       int is_sataii_tx4)
0672 {
0673     static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
0674     return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
0675 }
0676 
0677 static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
0678 {
0679     return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
0680 }
0681 
0682 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
0683 {
0684     const struct ata_host *host = ap->host;
0685     unsigned int nr_ports = pdc_sata_nr_ports(ap);
0686     unsigned int i;
0687 
0688     for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
0689         ;
0690     BUG_ON(i >= nr_ports);
0691     return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
0692 }
0693 
0694 static void pdc_freeze(struct ata_port *ap)
0695 {
0696     void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
0697     u32 tmp;
0698 
0699     tmp = readl(ata_mmio + PDC_CTLSTAT);
0700     tmp |= PDC_IRQ_DISABLE;
0701     tmp &= ~PDC_DMA_ENABLE;
0702     writel(tmp, ata_mmio + PDC_CTLSTAT);
0703     readl(ata_mmio + PDC_CTLSTAT); /* flush */
0704 }
0705 
0706 static void pdc_sata_freeze(struct ata_port *ap)
0707 {
0708     struct ata_host *host = ap->host;
0709     void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
0710     unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
0711     unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
0712     u32 hotplug_status;
0713 
0714     /* Disable hotplug events on this port.
0715      *
0716      * Locking:
0717      * 1) hotplug register accesses must be serialised via host->lock
0718      * 2) ap->lock == &ap->host->lock
0719      * 3) ->freeze() and ->thaw() are called with ap->lock held
0720      */
0721     hotplug_status = readl(host_mmio + hotplug_offset);
0722     hotplug_status |= 0x11 << (ata_no + 16);
0723     writel(hotplug_status, host_mmio + hotplug_offset);
0724     readl(host_mmio + hotplug_offset); /* flush */
0725 
0726     pdc_freeze(ap);
0727 }
0728 
0729 static void pdc_thaw(struct ata_port *ap)
0730 {
0731     void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
0732     u32 tmp;
0733 
0734     /* clear IRQ */
0735     readl(ata_mmio + PDC_COMMAND);
0736 
0737     /* turn IRQ back on */
0738     tmp = readl(ata_mmio + PDC_CTLSTAT);
0739     tmp &= ~PDC_IRQ_DISABLE;
0740     writel(tmp, ata_mmio + PDC_CTLSTAT);
0741     readl(ata_mmio + PDC_CTLSTAT); /* flush */
0742 }
0743 
0744 static void pdc_sata_thaw(struct ata_port *ap)
0745 {
0746     struct ata_host *host = ap->host;
0747     void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
0748     unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
0749     unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
0750     u32 hotplug_status;
0751 
0752     pdc_thaw(ap);
0753 
0754     /* Enable hotplug events on this port.
0755      * Locking: see pdc_sata_freeze().
0756      */
0757     hotplug_status = readl(host_mmio + hotplug_offset);
0758     hotplug_status |= 0x11 << ata_no;
0759     hotplug_status &= ~(0x11 << (ata_no + 16));
0760     writel(hotplug_status, host_mmio + hotplug_offset);
0761     readl(host_mmio + hotplug_offset); /* flush */
0762 }
0763 
0764 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
0765                   unsigned long deadline)
0766 {
0767     pdc_reset_port(link->ap);
0768     return ata_sff_softreset(link, class, deadline);
0769 }
0770 
0771 static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap)
0772 {
0773     void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
0774     void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
0775 
0776     /* ata_mmio == host_mmio + 0x200 + ata_no * 0x80 */
0777     return (ata_mmio - host_mmio - 0x200) / 0x80;
0778 }
0779 
0780 static void pdc_hard_reset_port(struct ata_port *ap)
0781 {
0782     void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
0783     void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1;
0784     unsigned int ata_no = pdc_ata_port_to_ata_no(ap);
0785     struct pdc_host_priv *hpriv = ap->host->private_data;
0786     u8 tmp;
0787 
0788     spin_lock(&hpriv->hard_reset_lock);
0789 
0790     tmp = readb(pcictl_b1_mmio);
0791     tmp &= ~(0x10 << ata_no);
0792     writeb(tmp, pcictl_b1_mmio);
0793     readb(pcictl_b1_mmio); /* flush */
0794     udelay(100);
0795     tmp |= (0x10 << ata_no);
0796     writeb(tmp, pcictl_b1_mmio);
0797     readb(pcictl_b1_mmio); /* flush */
0798 
0799     spin_unlock(&hpriv->hard_reset_lock);
0800 }
0801 
0802 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
0803                   unsigned long deadline)
0804 {
0805     if (link->ap->flags & PDC_FLAG_GEN_II)
0806         pdc_not_at_command_packet_phase(link->ap);
0807     /* hotplug IRQs should have been masked by pdc_sata_freeze() */
0808     pdc_hard_reset_port(link->ap);
0809     pdc_reset_port(link->ap);
0810 
0811     /* sata_promise can't reliably acquire the first D2H Reg FIS
0812      * after hardreset.  Do non-waiting hardreset and request
0813      * follow-up SRST.
0814      */
0815     return sata_std_hardreset(link, class, deadline);
0816 }
0817 
0818 static void pdc_error_handler(struct ata_port *ap)
0819 {
0820     if (!(ap->pflags & ATA_PFLAG_FROZEN))
0821         pdc_reset_port(ap);
0822 
0823     ata_sff_error_handler(ap);
0824 }
0825 
0826 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
0827 {
0828     struct ata_port *ap = qc->ap;
0829 
0830     /* make DMA engine forget about the failed command */
0831     if (qc->flags & ATA_QCFLAG_FAILED)
0832         pdc_reset_port(ap);
0833 }
0834 
0835 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
0836                u32 port_status, u32 err_mask)
0837 {
0838     struct ata_eh_info *ehi = &ap->link.eh_info;
0839     unsigned int ac_err_mask = 0;
0840 
0841     ata_ehi_clear_desc(ehi);
0842     ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
0843     port_status &= err_mask;
0844 
0845     if (port_status & PDC_DRIVE_ERR)
0846         ac_err_mask |= AC_ERR_DEV;
0847     if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
0848         ac_err_mask |= AC_ERR_OTHER;
0849     if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
0850         ac_err_mask |= AC_ERR_ATA_BUS;
0851     if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
0852                | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
0853         ac_err_mask |= AC_ERR_HOST_BUS;
0854 
0855     if (sata_scr_valid(&ap->link)) {
0856         u32 serror;
0857 
0858         pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
0859         ehi->serror |= serror;
0860     }
0861 
0862     qc->err_mask |= ac_err_mask;
0863 
0864     pdc_reset_port(ap);
0865 
0866     ata_port_abort(ap);
0867 }
0868 
0869 static unsigned int pdc_host_intr(struct ata_port *ap,
0870                   struct ata_queued_cmd *qc)
0871 {
0872     unsigned int handled = 0;
0873     void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
0874     u32 port_status, err_mask;
0875 
0876     err_mask = PDC_ERR_MASK;
0877     if (ap->flags & PDC_FLAG_GEN_II)
0878         err_mask &= ~PDC1_ERR_MASK;
0879     else
0880         err_mask &= ~PDC2_ERR_MASK;
0881     port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
0882     if (unlikely(port_status & err_mask)) {
0883         pdc_error_intr(ap, qc, port_status, err_mask);
0884         return 1;
0885     }
0886 
0887     switch (qc->tf.protocol) {
0888     case ATA_PROT_DMA:
0889     case ATA_PROT_NODATA:
0890     case ATAPI_PROT_DMA:
0891     case ATAPI_PROT_NODATA:
0892         qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
0893         ata_qc_complete(qc);
0894         handled = 1;
0895         break;
0896     default:
0897         ap->stats.idle_irq++;
0898         break;
0899     }
0900 
0901     return handled;
0902 }
0903 
0904 static void pdc_irq_clear(struct ata_port *ap)
0905 {
0906     void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
0907 
0908     readl(ata_mmio + PDC_COMMAND);
0909 }
0910 
0911 static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
0912 {
0913     struct ata_host *host = dev_instance;
0914     struct ata_port *ap;
0915     u32 mask = 0;
0916     unsigned int i, tmp;
0917     unsigned int handled = 0;
0918     void __iomem *host_mmio;
0919     unsigned int hotplug_offset, ata_no;
0920     u32 hotplug_status;
0921     int is_sataii_tx4;
0922 
0923     if (!host || !host->iomap[PDC_MMIO_BAR])
0924         return IRQ_NONE;
0925 
0926     host_mmio = host->iomap[PDC_MMIO_BAR];
0927 
0928     spin_lock(&host->lock);
0929 
0930     /* read and clear hotplug flags for all ports */
0931     if (host->ports[0]->flags & PDC_FLAG_GEN_II) {
0932         hotplug_offset = PDC2_SATA_PLUG_CSR;
0933         hotplug_status = readl(host_mmio + hotplug_offset);
0934         if (hotplug_status & 0xff)
0935             writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
0936         hotplug_status &= 0xff; /* clear uninteresting bits */
0937     } else
0938         hotplug_status = 0;
0939 
0940     /* reading should also clear interrupts */
0941     mask = readl(host_mmio + PDC_INT_SEQMASK);
0942 
0943     if (mask == 0xffffffff && hotplug_status == 0)
0944         goto done_irq;
0945 
0946     mask &= 0xffff;     /* only 16 SEQIDs possible */
0947     if (mask == 0 && hotplug_status == 0)
0948         goto done_irq;
0949 
0950     writel(mask, host_mmio + PDC_INT_SEQMASK);
0951 
0952     is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
0953 
0954     for (i = 0; i < host->n_ports; i++) {
0955         ap = host->ports[i];
0956 
0957         /* check for a plug or unplug event */
0958         ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
0959         tmp = hotplug_status & (0x11 << ata_no);
0960         if (tmp) {
0961             struct ata_eh_info *ehi = &ap->link.eh_info;
0962             ata_ehi_clear_desc(ehi);
0963             ata_ehi_hotplugged(ehi);
0964             ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
0965             ata_port_freeze(ap);
0966             ++handled;
0967             continue;
0968         }
0969 
0970         /* check for a packet interrupt */
0971         tmp = mask & (1 << (i + 1));
0972         if (tmp) {
0973             struct ata_queued_cmd *qc;
0974 
0975             qc = ata_qc_from_tag(ap, ap->link.active_tag);
0976             if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
0977                 handled += pdc_host_intr(ap, qc);
0978         }
0979     }
0980 
0981 done_irq:
0982     spin_unlock(&host->lock);
0983     return IRQ_RETVAL(handled);
0984 }
0985 
0986 static void pdc_packet_start(struct ata_queued_cmd *qc)
0987 {
0988     struct ata_port *ap = qc->ap;
0989     struct pdc_port_priv *pp = ap->private_data;
0990     void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
0991     void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
0992     unsigned int port_no = ap->port_no;
0993     u8 seq = (u8) (port_no + 1);
0994 
0995     writel(0x00000001, host_mmio + (seq * 4));
0996     readl(host_mmio + (seq * 4));   /* flush */
0997 
0998     pp->pkt[2] = seq;
0999     wmb();          /* flush PRD, pkt writes */
1000     writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
1001     readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */
1002 }
1003 
1004 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
1005 {
1006     switch (qc->tf.protocol) {
1007     case ATAPI_PROT_NODATA:
1008         if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1009             break;
1010         fallthrough;
1011     case ATA_PROT_NODATA:
1012         if (qc->tf.flags & ATA_TFLAG_POLLING)
1013             break;
1014         fallthrough;
1015     case ATAPI_PROT_DMA:
1016     case ATA_PROT_DMA:
1017         pdc_packet_start(qc);
1018         return 0;
1019     default:
1020         break;
1021     }
1022     return ata_sff_qc_issue(qc);
1023 }
1024 
1025 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1026 {
1027     WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1028     ata_sff_tf_load(ap, tf);
1029 }
1030 
1031 static void pdc_exec_command_mmio(struct ata_port *ap,
1032                   const struct ata_taskfile *tf)
1033 {
1034     WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1035     ata_sff_exec_command(ap, tf);
1036 }
1037 
1038 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
1039 {
1040     u8 *scsicmd = qc->scsicmd->cmnd;
1041     int pio = 1; /* atapi dma off by default */
1042 
1043     /* Whitelist commands that may use DMA. */
1044     switch (scsicmd[0]) {
1045     case WRITE_12:
1046     case WRITE_10:
1047     case WRITE_6:
1048     case READ_12:
1049     case READ_10:
1050     case READ_6:
1051     case 0xad: /* READ_DVD_STRUCTURE */
1052     case 0xbe: /* READ_CD */
1053         pio = 0;
1054     }
1055     /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
1056     if (scsicmd[0] == WRITE_10) {
1057         unsigned int lba =
1058             (scsicmd[2] << 24) |
1059             (scsicmd[3] << 16) |
1060             (scsicmd[4] << 8) |
1061             scsicmd[5];
1062         if (lba >= 0xFFFF4FA2)
1063             pio = 1;
1064     }
1065     return pio;
1066 }
1067 
1068 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
1069 {
1070     /* First generation chips cannot use ATAPI DMA on SATA ports */
1071     return 1;
1072 }
1073 
1074 static void pdc_ata_setup_port(struct ata_port *ap,
1075                    void __iomem *base, void __iomem *scr_addr)
1076 {
1077     ap->ioaddr.cmd_addr     = base;
1078     ap->ioaddr.data_addr        = base;
1079     ap->ioaddr.feature_addr     =
1080     ap->ioaddr.error_addr       = base + 0x4;
1081     ap->ioaddr.nsect_addr       = base + 0x8;
1082     ap->ioaddr.lbal_addr        = base + 0xc;
1083     ap->ioaddr.lbam_addr        = base + 0x10;
1084     ap->ioaddr.lbah_addr        = base + 0x14;
1085     ap->ioaddr.device_addr      = base + 0x18;
1086     ap->ioaddr.command_addr     =
1087     ap->ioaddr.status_addr      = base + 0x1c;
1088     ap->ioaddr.altstatus_addr   =
1089     ap->ioaddr.ctl_addr     = base + 0x38;
1090     ap->ioaddr.scr_addr     = scr_addr;
1091 }
1092 
1093 static void pdc_host_init(struct ata_host *host)
1094 {
1095     void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
1096     int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
1097     int hotplug_offset;
1098     u32 tmp;
1099 
1100     if (is_gen2)
1101         hotplug_offset = PDC2_SATA_PLUG_CSR;
1102     else
1103         hotplug_offset = PDC_SATA_PLUG_CSR;
1104 
1105     /*
1106      * Except for the hotplug stuff, this is voodoo from the
1107      * Promise driver.  Label this entire section
1108      * "TODO: figure out why we do this"
1109      */
1110 
1111     /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1112     tmp = readl(host_mmio + PDC_FLASH_CTL);
1113     tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1114     if (!is_gen2)
1115         tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1116     writel(tmp, host_mmio + PDC_FLASH_CTL);
1117 
1118     /* clear plug/unplug flags for all ports */
1119     tmp = readl(host_mmio + hotplug_offset);
1120     writel(tmp | 0xff, host_mmio + hotplug_offset);
1121 
1122     tmp = readl(host_mmio + hotplug_offset);
1123     if (is_gen2)    /* unmask plug/unplug ints */
1124         writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1125     else        /* mask plug/unplug ints */
1126         writel(tmp | 0xff0000, host_mmio + hotplug_offset);
1127 
1128     /* don't initialise TBG or SLEW on 2nd generation chips */
1129     if (is_gen2)
1130         return;
1131 
1132     /* reduce TBG clock to 133 Mhz. */
1133     tmp = readl(host_mmio + PDC_TBG_MODE);
1134     tmp &= ~0x30000; /* clear bit 17, 16*/
1135     tmp |= 0x10000;  /* set bit 17:16 = 0:1 */
1136     writel(tmp, host_mmio + PDC_TBG_MODE);
1137 
1138     readl(host_mmio + PDC_TBG_MODE);    /* flush */
1139     msleep(10);
1140 
1141     /* adjust slew rate control register. */
1142     tmp = readl(host_mmio + PDC_SLEW_CTL);
1143     tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1144     tmp  |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1145     writel(tmp, host_mmio + PDC_SLEW_CTL);
1146 }
1147 
1148 static int pdc_ata_init_one(struct pci_dev *pdev,
1149                 const struct pci_device_id *ent)
1150 {
1151     const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1152     const struct ata_port_info *ppi[PDC_MAX_PORTS];
1153     struct ata_host *host;
1154     struct pdc_host_priv *hpriv;
1155     void __iomem *host_mmio;
1156     int n_ports, i, rc;
1157     int is_sataii_tx4;
1158 
1159     ata_print_version_once(&pdev->dev, DRV_VERSION);
1160 
1161     /* enable and acquire resources */
1162     rc = pcim_enable_device(pdev);
1163     if (rc)
1164         return rc;
1165 
1166     rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1167     if (rc == -EBUSY)
1168         pcim_pin_device(pdev);
1169     if (rc)
1170         return rc;
1171     host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1172 
1173     /* determine port configuration and setup host */
1174     n_ports = 2;
1175     if (pi->flags & PDC_FLAG_4_PORTS)
1176         n_ports = 4;
1177     for (i = 0; i < n_ports; i++)
1178         ppi[i] = pi;
1179 
1180     if (pi->flags & PDC_FLAG_SATA_PATA) {
1181         u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
1182         if (!(tmp & 0x80))
1183             ppi[n_ports++] = pi + 1;
1184     }
1185 
1186     host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1187     if (!host) {
1188         dev_err(&pdev->dev, "failed to allocate host\n");
1189         return -ENOMEM;
1190     }
1191     hpriv = devm_kzalloc(&pdev->dev, sizeof *hpriv, GFP_KERNEL);
1192     if (!hpriv)
1193         return -ENOMEM;
1194     spin_lock_init(&hpriv->hard_reset_lock);
1195     host->private_data = hpriv;
1196     host->iomap = pcim_iomap_table(pdev);
1197 
1198     is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1199     for (i = 0; i < host->n_ports; i++) {
1200         struct ata_port *ap = host->ports[i];
1201         unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1202         unsigned int ata_offset = 0x200 + ata_no * 0x80;
1203         unsigned int scr_offset = 0x400 + ata_no * 0x100;
1204 
1205         pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
1206 
1207         ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1208         ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
1209     }
1210 
1211     /* initialize adapter */
1212     pdc_host_init(host);
1213 
1214     rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
1215     if (rc)
1216         return rc;
1217 
1218     /* start host, request IRQ and attach */
1219     pci_set_master(pdev);
1220     return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1221                  &pdc_ata_sht);
1222 }
1223 
1224 module_pci_driver(pdc_ata_pci_driver);
1225 
1226 MODULE_AUTHOR("Jeff Garzik");
1227 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1228 MODULE_LICENSE("GPL");
1229 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1230 MODULE_VERSION(DRV_VERSION);
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