Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * drivers/ata/sata_fsl.c
0004  *
0005  * Freescale 3.0Gbps SATA device driver
0006  *
0007  * Author: Ashish Kalra <ashish.kalra@freescale.com>
0008  * Li Yang <leoli@freescale.com>
0009  *
0010  * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
0011  */
0012 
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/slab.h>
0017 
0018 #include <scsi/scsi_host.h>
0019 #include <scsi/scsi_cmnd.h>
0020 #include <linux/libata.h>
0021 #include <asm/io.h>
0022 #include <linux/of_address.h>
0023 #include <linux/of_irq.h>
0024 #include <linux/of_platform.h>
0025 
0026 static unsigned int intr_coalescing_count;
0027 module_param(intr_coalescing_count, int, S_IRUGO);
0028 MODULE_PARM_DESC(intr_coalescing_count,
0029                  "INT coalescing count threshold (1..31)");
0030 
0031 static unsigned int intr_coalescing_ticks;
0032 module_param(intr_coalescing_ticks, int, S_IRUGO);
0033 MODULE_PARM_DESC(intr_coalescing_ticks,
0034                  "INT coalescing timer threshold in AHB ticks");
0035 /* Controller information */
0036 enum {
0037     SATA_FSL_QUEUE_DEPTH    = 16,
0038     SATA_FSL_MAX_PRD    = 63,
0039     SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
0040     SATA_FSL_MAX_PRD_DIRECT = 16,   /* Direct PRDT entries */
0041 
0042     SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
0043                    ATA_FLAG_PMP | ATA_FLAG_NCQ |
0044                    ATA_FLAG_AN | ATA_FLAG_NO_LOG_PAGE),
0045 
0046     SATA_FSL_MAX_CMDS   = SATA_FSL_QUEUE_DEPTH,
0047     SATA_FSL_CMD_HDR_SIZE   = 16,   /* 4 DWORDS */
0048     SATA_FSL_CMD_SLOT_SIZE  = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
0049 
0050     /*
0051      * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
0052      * chained indirect PRDEs up to a max count of 63.
0053      * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
0054      * be setup as an indirect descriptor, pointing to it's next
0055      * (contiguous) PRDE. Though chained indirect PRDE arrays are
0056      * supported,it will be more efficient to use a direct PRDT and
0057      * a single chain/link to indirect PRDE array/PRDT.
0058      */
0059 
0060     SATA_FSL_CMD_DESC_CFIS_SZ   = 32,
0061     SATA_FSL_CMD_DESC_SFIS_SZ   = 32,
0062     SATA_FSL_CMD_DESC_ACMD_SZ   = 16,
0063     SATA_FSL_CMD_DESC_RSRVD     = 16,
0064 
0065     SATA_FSL_CMD_DESC_SIZE  = (SATA_FSL_CMD_DESC_CFIS_SZ +
0066                  SATA_FSL_CMD_DESC_SFIS_SZ +
0067                  SATA_FSL_CMD_DESC_ACMD_SZ +
0068                  SATA_FSL_CMD_DESC_RSRVD +
0069                  SATA_FSL_MAX_PRD * 16),
0070 
0071     SATA_FSL_CMD_DESC_OFFSET_TO_PRDT    =
0072                 (SATA_FSL_CMD_DESC_CFIS_SZ +
0073                  SATA_FSL_CMD_DESC_SFIS_SZ +
0074                  SATA_FSL_CMD_DESC_ACMD_SZ +
0075                  SATA_FSL_CMD_DESC_RSRVD),
0076 
0077     SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
0078     SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
0079                     SATA_FSL_CMD_DESC_AR_SZ),
0080 
0081     /*
0082      * MPC8315 has two SATA controllers, SATA1 & SATA2
0083      * (one port per controller)
0084      * MPC837x has 2/4 controllers, one port per controller
0085      */
0086 
0087     SATA_FSL_MAX_PORTS  = 1,
0088 
0089     SATA_FSL_IRQ_FLAG   = IRQF_SHARED,
0090 };
0091 
0092 /*
0093  * Interrupt Coalescing Control Register bitdefs  */
0094 enum {
0095     ICC_MIN_INT_COUNT_THRESHOLD = 1,
0096     ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1),
0097     ICC_MIN_INT_TICKS_THRESHOLD = 0,
0098     ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1),
0099     ICC_SAFE_INT_TICKS      = 1,
0100 };
0101 
0102 /*
0103 * Host Controller command register set - per port
0104 */
0105 enum {
0106     CQ = 0,
0107     CA = 8,
0108     CC = 0x10,
0109     CE = 0x18,
0110     DE = 0x20,
0111     CHBA = 0x24,
0112     HSTATUS = 0x28,
0113     HCONTROL = 0x2C,
0114     CQPMP = 0x30,
0115     SIGNATURE = 0x34,
0116     ICC = 0x38,
0117 
0118     /*
0119      * Host Status Register (HStatus) bitdefs
0120      */
0121     ONLINE = (1 << 31),
0122     GOING_OFFLINE = (1 << 30),
0123     BIST_ERR = (1 << 29),
0124     CLEAR_ERROR = (1 << 27),
0125 
0126     FATAL_ERR_HC_MASTER_ERR = (1 << 18),
0127     FATAL_ERR_PARITY_ERR_TX = (1 << 17),
0128     FATAL_ERR_PARITY_ERR_RX = (1 << 16),
0129     FATAL_ERR_DATA_UNDERRUN = (1 << 13),
0130     FATAL_ERR_DATA_OVERRUN = (1 << 12),
0131     FATAL_ERR_CRC_ERR_TX = (1 << 11),
0132     FATAL_ERR_CRC_ERR_RX = (1 << 10),
0133     FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
0134     FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
0135 
0136     FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
0137         FATAL_ERR_PARITY_ERR_TX |
0138         FATAL_ERR_PARITY_ERR_RX |
0139         FATAL_ERR_DATA_UNDERRUN |
0140         FATAL_ERR_DATA_OVERRUN |
0141         FATAL_ERR_CRC_ERR_TX |
0142         FATAL_ERR_CRC_ERR_RX |
0143         FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
0144 
0145     INT_ON_DATA_LENGTH_MISMATCH = (1 << 12),
0146     INT_ON_FATAL_ERR = (1 << 5),
0147     INT_ON_PHYRDY_CHG = (1 << 4),
0148 
0149     INT_ON_SIGNATURE_UPDATE = (1 << 3),
0150     INT_ON_SNOTIFY_UPDATE = (1 << 2),
0151     INT_ON_SINGL_DEVICE_ERR = (1 << 1),
0152     INT_ON_CMD_COMPLETE = 1,
0153 
0154     INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
0155         INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
0156 
0157     /*
0158      * Host Control Register (HControl) bitdefs
0159      */
0160     HCONTROL_ONLINE_PHY_RST = (1 << 31),
0161     HCONTROL_FORCE_OFFLINE = (1 << 30),
0162     HCONTROL_LEGACY = (1 << 28),
0163     HCONTROL_PARITY_PROT_MOD = (1 << 14),
0164     HCONTROL_DPATH_PARITY = (1 << 12),
0165     HCONTROL_SNOOP_ENABLE = (1 << 10),
0166     HCONTROL_PMP_ATTACHED = (1 << 9),
0167     HCONTROL_COPYOUT_STATFIS = (1 << 8),
0168     IE_ON_FATAL_ERR = (1 << 5),
0169     IE_ON_PHYRDY_CHG = (1 << 4),
0170     IE_ON_SIGNATURE_UPDATE = (1 << 3),
0171     IE_ON_SNOTIFY_UPDATE = (1 << 2),
0172     IE_ON_SINGL_DEVICE_ERR = (1 << 1),
0173     IE_ON_CMD_COMPLETE = 1,
0174 
0175     DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
0176         IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
0177         IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
0178 
0179     EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
0180     DATA_SNOOP_ENABLE_V1 = (1 << 22),
0181     DATA_SNOOP_ENABLE_V2 = (1 << 28),
0182 };
0183 
0184 /*
0185  * SATA Superset Registers
0186  */
0187 enum {
0188     SSTATUS = 0,
0189     SERROR = 4,
0190     SCONTROL = 8,
0191     SNOTIFY = 0xC,
0192 };
0193 
0194 /*
0195  * Control Status Register Set
0196  */
0197 enum {
0198     TRANSCFG = 0,
0199     TRANSSTATUS = 4,
0200     LINKCFG = 8,
0201     LINKCFG1 = 0xC,
0202     LINKCFG2 = 0x10,
0203     LINKSTATUS = 0x14,
0204     LINKSTATUS1 = 0x18,
0205     PHYCTRLCFG = 0x1C,
0206     COMMANDSTAT = 0x20,
0207 };
0208 
0209 /* TRANSCFG (transport-layer) configuration control */
0210 enum {
0211     TRANSCFG_RX_WATER_MARK = (1 << 4),
0212 };
0213 
0214 /* PHY (link-layer) configuration control */
0215 enum {
0216     PHY_BIST_ENABLE = 0x01,
0217 };
0218 
0219 /*
0220  * Command Header Table entry, i.e, command slot
0221  * 4 Dwords per command slot, command header size ==  64 Dwords.
0222  */
0223 struct cmdhdr_tbl_entry {
0224     __le32 cda;
0225     __le32 prde_fis_len;
0226     __le32 ttl;
0227     __le32 desc_info;
0228 };
0229 
0230 /*
0231  * Description information bitdefs
0232  */
0233 enum {
0234     CMD_DESC_RES = (1 << 11),
0235     VENDOR_SPECIFIC_BIST = (1 << 10),
0236     CMD_DESC_SNOOP_ENABLE = (1 << 9),
0237     FPDMA_QUEUED_CMD = (1 << 8),
0238     SRST_CMD = (1 << 7),
0239     BIST = (1 << 6),
0240     ATAPI_CMD = (1 << 5),
0241 };
0242 
0243 /*
0244  * Command Descriptor
0245  */
0246 struct command_desc {
0247     u8 cfis[8 * 4];
0248     u8 sfis[8 * 4];
0249     struct_group(cdb,
0250         u8 acmd[4 * 4];
0251         u8 fill[4 * 4];
0252     );
0253     u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
0254     u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
0255 };
0256 
0257 /*
0258  * Physical region table descriptor(PRD)
0259  */
0260 
0261 struct prde {
0262     __le32 dba;
0263     u8 fill[2 * 4];
0264     __le32 ddc_and_ext;
0265 };
0266 
0267 /*
0268  * ata_port private data
0269  * This is our per-port instance data.
0270  */
0271 struct sata_fsl_port_priv {
0272     struct cmdhdr_tbl_entry *cmdslot;
0273     dma_addr_t cmdslot_paddr;
0274     struct command_desc *cmdentry;
0275     dma_addr_t cmdentry_paddr;
0276 };
0277 
0278 /*
0279  * ata_port->host_set private data
0280  */
0281 struct sata_fsl_host_priv {
0282     void __iomem *hcr_base;
0283     void __iomem *ssr_base;
0284     void __iomem *csr_base;
0285     int irq;
0286     int data_snoop;
0287     struct device_attribute intr_coalescing;
0288     struct device_attribute rx_watermark;
0289 };
0290 
0291 static void fsl_sata_set_irq_coalescing(struct ata_host *host,
0292         unsigned int count, unsigned int ticks)
0293 {
0294     struct sata_fsl_host_priv *host_priv = host->private_data;
0295     void __iomem *hcr_base = host_priv->hcr_base;
0296     unsigned long flags;
0297 
0298     if (count > ICC_MAX_INT_COUNT_THRESHOLD)
0299         count = ICC_MAX_INT_COUNT_THRESHOLD;
0300     else if (count < ICC_MIN_INT_COUNT_THRESHOLD)
0301         count = ICC_MIN_INT_COUNT_THRESHOLD;
0302 
0303     if (ticks > ICC_MAX_INT_TICKS_THRESHOLD)
0304         ticks = ICC_MAX_INT_TICKS_THRESHOLD;
0305     else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) &&
0306             (count > ICC_MIN_INT_COUNT_THRESHOLD))
0307         ticks = ICC_SAFE_INT_TICKS;
0308 
0309     spin_lock_irqsave(&host->lock, flags);
0310     iowrite32((count << 24 | ticks), hcr_base + ICC);
0311 
0312     intr_coalescing_count = count;
0313     intr_coalescing_ticks = ticks;
0314     spin_unlock_irqrestore(&host->lock, flags);
0315 
0316     dev_dbg(host->dev, "interrupt coalescing, count = 0x%x, ticks = %x\n",
0317         intr_coalescing_count, intr_coalescing_ticks);
0318     dev_dbg(host->dev, "ICC register status: (hcr base: 0x%p) = 0x%x\n",
0319         hcr_base, ioread32(hcr_base + ICC));
0320 }
0321 
0322 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
0323         struct device_attribute *attr, char *buf)
0324 {
0325     return sysfs_emit(buf, "%u  %u\n",
0326             intr_coalescing_count, intr_coalescing_ticks);
0327 }
0328 
0329 static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
0330         struct device_attribute *attr,
0331         const char *buf, size_t count)
0332 {
0333     unsigned int coalescing_count,  coalescing_ticks;
0334 
0335     if (sscanf(buf, "%u%u", &coalescing_count, &coalescing_ticks) != 2) {
0336         dev_err(dev, "fsl-sata: wrong parameter format.\n");
0337         return -EINVAL;
0338     }
0339 
0340     fsl_sata_set_irq_coalescing(dev_get_drvdata(dev),
0341             coalescing_count, coalescing_ticks);
0342 
0343     return strlen(buf);
0344 }
0345 
0346 static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
0347         struct device_attribute *attr, char *buf)
0348 {
0349     unsigned int rx_watermark;
0350     unsigned long flags;
0351     struct ata_host *host = dev_get_drvdata(dev);
0352     struct sata_fsl_host_priv *host_priv = host->private_data;
0353     void __iomem *csr_base = host_priv->csr_base;
0354 
0355     spin_lock_irqsave(&host->lock, flags);
0356     rx_watermark = ioread32(csr_base + TRANSCFG);
0357     rx_watermark &= 0x1f;
0358     spin_unlock_irqrestore(&host->lock, flags);
0359 
0360     return sysfs_emit(buf, "%u\n", rx_watermark);
0361 }
0362 
0363 static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
0364         struct device_attribute *attr,
0365         const char *buf, size_t count)
0366 {
0367     unsigned int rx_watermark;
0368     unsigned long flags;
0369     struct ata_host *host = dev_get_drvdata(dev);
0370     struct sata_fsl_host_priv *host_priv = host->private_data;
0371     void __iomem *csr_base = host_priv->csr_base;
0372     u32 temp;
0373 
0374     if (kstrtouint(buf, 10, &rx_watermark) < 0) {
0375         dev_err(dev, "fsl-sata: wrong parameter format.\n");
0376         return -EINVAL;
0377     }
0378 
0379     spin_lock_irqsave(&host->lock, flags);
0380     temp = ioread32(csr_base + TRANSCFG);
0381     temp &= 0xffffffe0;
0382     iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
0383     spin_unlock_irqrestore(&host->lock, flags);
0384 
0385     return strlen(buf);
0386 }
0387 
0388 static inline unsigned int sata_fsl_tag(struct ata_port *ap,
0389                     unsigned int tag,
0390                     void __iomem *hcr_base)
0391 {
0392     /* We let libATA core do actual (queue) tag allocation */
0393 
0394     if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
0395         ata_port_dbg(ap, "tag %d invalid : out of range\n", tag);
0396         return 0;
0397     }
0398 
0399     if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
0400         ata_port_dbg(ap, "tag %d invalid : in use!!\n", tag);
0401         return 0;
0402     }
0403 
0404     return tag;
0405 }
0406 
0407 static void sata_fsl_setup_cmd_hdr_entry(struct ata_port *ap,
0408                      struct sata_fsl_port_priv *pp,
0409                      unsigned int tag, u32 desc_info,
0410                      u32 data_xfer_len, u8 num_prde,
0411                      u8 fis_len)
0412 {
0413     dma_addr_t cmd_descriptor_address;
0414 
0415     cmd_descriptor_address = pp->cmdentry_paddr +
0416         tag * SATA_FSL_CMD_DESC_SIZE;
0417 
0418     /* NOTE: both data_xfer_len & fis_len are Dword counts */
0419 
0420     pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
0421     pp->cmdslot[tag].prde_fis_len =
0422         cpu_to_le32((num_prde << 16) | (fis_len << 2));
0423     pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
0424     pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
0425 
0426     ata_port_dbg(ap, "cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
0427              le32_to_cpu(pp->cmdslot[tag].cda),
0428              le32_to_cpu(pp->cmdslot[tag].prde_fis_len),
0429              le32_to_cpu(pp->cmdslot[tag].ttl),
0430              le32_to_cpu(pp->cmdslot[tag].desc_info));
0431 }
0432 
0433 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
0434                      u32 *ttl, dma_addr_t cmd_desc_paddr,
0435                      int data_snoop)
0436 {
0437     struct scatterlist *sg;
0438     unsigned int num_prde = 0;
0439     u32 ttl_dwords = 0;
0440 
0441     /*
0442      * NOTE : direct & indirect prdt's are contiguously allocated
0443      */
0444     struct prde *prd = (struct prde *)&((struct command_desc *)
0445                         cmd_desc)->prdt;
0446 
0447     struct prde *prd_ptr_to_indirect_ext = NULL;
0448     unsigned indirect_ext_segment_sz = 0;
0449     dma_addr_t indirect_ext_segment_paddr;
0450     unsigned int si;
0451 
0452     indirect_ext_segment_paddr = cmd_desc_paddr +
0453         SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
0454 
0455     for_each_sg(qc->sg, sg, qc->n_elem, si) {
0456         dma_addr_t sg_addr = sg_dma_address(sg);
0457         u32 sg_len = sg_dma_len(sg);
0458 
0459         /* warn if each s/g element is not dword aligned */
0460         if (unlikely(sg_addr & 0x03))
0461             ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
0462                      (unsigned long long)sg_addr);
0463         if (unlikely(sg_len & 0x03))
0464             ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n",
0465                      sg_len);
0466 
0467         if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
0468             sg_next(sg) != NULL) {
0469             prd_ptr_to_indirect_ext = prd;
0470             prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
0471             indirect_ext_segment_sz = 0;
0472             ++prd;
0473             ++num_prde;
0474         }
0475 
0476         ttl_dwords += sg_len;
0477         prd->dba = cpu_to_le32(sg_addr);
0478         prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
0479 
0480         ++num_prde;
0481         ++prd;
0482         if (prd_ptr_to_indirect_ext)
0483             indirect_ext_segment_sz += sg_len;
0484     }
0485 
0486     if (prd_ptr_to_indirect_ext) {
0487         /* set indirect extension flag along with indirect ext. size */
0488         prd_ptr_to_indirect_ext->ddc_and_ext =
0489             cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
0490                  data_snoop |
0491                  (indirect_ext_segment_sz & ~0x03)));
0492     }
0493 
0494     *ttl = ttl_dwords;
0495     return num_prde;
0496 }
0497 
0498 static enum ata_completion_errors sata_fsl_qc_prep(struct ata_queued_cmd *qc)
0499 {
0500     struct ata_port *ap = qc->ap;
0501     struct sata_fsl_port_priv *pp = ap->private_data;
0502     struct sata_fsl_host_priv *host_priv = ap->host->private_data;
0503     void __iomem *hcr_base = host_priv->hcr_base;
0504     unsigned int tag = sata_fsl_tag(ap, qc->hw_tag, hcr_base);
0505     struct command_desc *cd;
0506     u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
0507     u32 num_prde = 0;
0508     u32 ttl_dwords = 0;
0509     dma_addr_t cd_paddr;
0510 
0511     cd = (struct command_desc *)pp->cmdentry + tag;
0512     cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
0513 
0514     ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
0515 
0516     /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
0517     if (ata_is_atapi(qc->tf.protocol)) {
0518         desc_info |= ATAPI_CMD;
0519         memset(&cd->cdb, 0, sizeof(cd->cdb));
0520         memcpy(&cd->cdb, qc->cdb, qc->dev->cdb_len);
0521     }
0522 
0523     if (qc->flags & ATA_QCFLAG_DMAMAP)
0524         num_prde = sata_fsl_fill_sg(qc, (void *)cd,
0525                         &ttl_dwords, cd_paddr,
0526                         host_priv->data_snoop);
0527 
0528     if (qc->tf.protocol == ATA_PROT_NCQ)
0529         desc_info |= FPDMA_QUEUED_CMD;
0530 
0531     sata_fsl_setup_cmd_hdr_entry(ap, pp, tag, desc_info, ttl_dwords,
0532                      num_prde, 5);
0533 
0534     ata_port_dbg(ap, "SATA FSL : di = 0x%x, ttl = %d, num_prde = %d\n",
0535         desc_info, ttl_dwords, num_prde);
0536 
0537     return AC_ERR_OK;
0538 }
0539 
0540 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
0541 {
0542     struct ata_port *ap = qc->ap;
0543     struct sata_fsl_host_priv *host_priv = ap->host->private_data;
0544     void __iomem *hcr_base = host_priv->hcr_base;
0545     unsigned int tag = sata_fsl_tag(ap, qc->hw_tag, hcr_base);
0546 
0547     ata_port_dbg(ap, "CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
0548         ioread32(CQ + hcr_base),
0549         ioread32(CA + hcr_base),
0550         ioread32(CE + hcr_base), ioread32(CC + hcr_base));
0551 
0552     iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
0553 
0554     /* Simply queue command to the controller/device */
0555     iowrite32(1 << tag, CQ + hcr_base);
0556 
0557     ata_port_dbg(ap, "tag=%d, CQ=0x%x, CA=0x%x\n",
0558         tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
0559 
0560     ata_port_dbg(ap, "CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
0561         ioread32(CE + hcr_base),
0562         ioread32(DE + hcr_base),
0563         ioread32(CC + hcr_base),
0564         ioread32(COMMANDSTAT + host_priv->csr_base));
0565 
0566     return 0;
0567 }
0568 
0569 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
0570 {
0571     struct sata_fsl_port_priv *pp = qc->ap->private_data;
0572     struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
0573     void __iomem *hcr_base = host_priv->hcr_base;
0574     unsigned int tag = sata_fsl_tag(qc->ap, qc->hw_tag, hcr_base);
0575     struct command_desc *cd;
0576 
0577     cd = pp->cmdentry + tag;
0578 
0579     ata_tf_from_fis(cd->sfis, &qc->result_tf);
0580     return true;
0581 }
0582 
0583 static int sata_fsl_scr_write(struct ata_link *link,
0584                   unsigned int sc_reg_in, u32 val)
0585 {
0586     struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
0587     void __iomem *ssr_base = host_priv->ssr_base;
0588     unsigned int sc_reg;
0589 
0590     switch (sc_reg_in) {
0591     case SCR_STATUS:
0592     case SCR_ERROR:
0593     case SCR_CONTROL:
0594     case SCR_ACTIVE:
0595         sc_reg = sc_reg_in;
0596         break;
0597     default:
0598         return -EINVAL;
0599     }
0600 
0601     ata_link_dbg(link, "reg_in = %d\n", sc_reg);
0602 
0603     iowrite32(val, ssr_base + (sc_reg * 4));
0604     return 0;
0605 }
0606 
0607 static int sata_fsl_scr_read(struct ata_link *link,
0608                  unsigned int sc_reg_in, u32 *val)
0609 {
0610     struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
0611     void __iomem *ssr_base = host_priv->ssr_base;
0612     unsigned int sc_reg;
0613 
0614     switch (sc_reg_in) {
0615     case SCR_STATUS:
0616     case SCR_ERROR:
0617     case SCR_CONTROL:
0618     case SCR_ACTIVE:
0619         sc_reg = sc_reg_in;
0620         break;
0621     default:
0622         return -EINVAL;
0623     }
0624 
0625     ata_link_dbg(link, "reg_in = %d\n", sc_reg);
0626 
0627     *val = ioread32(ssr_base + (sc_reg * 4));
0628     return 0;
0629 }
0630 
0631 static void sata_fsl_freeze(struct ata_port *ap)
0632 {
0633     struct sata_fsl_host_priv *host_priv = ap->host->private_data;
0634     void __iomem *hcr_base = host_priv->hcr_base;
0635     u32 temp;
0636 
0637     ata_port_dbg(ap, "CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
0638         ioread32(CQ + hcr_base),
0639         ioread32(CA + hcr_base),
0640         ioread32(CE + hcr_base), ioread32(DE + hcr_base));
0641     ata_port_dbg(ap, "CmdStat = 0x%x\n",
0642         ioread32(host_priv->csr_base + COMMANDSTAT));
0643 
0644     /* disable interrupts on the controller/port */
0645     temp = ioread32(hcr_base + HCONTROL);
0646     iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
0647 
0648     ata_port_dbg(ap, "HControl = 0x%x, HStatus = 0x%x\n",
0649         ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
0650 }
0651 
0652 static void sata_fsl_thaw(struct ata_port *ap)
0653 {
0654     struct sata_fsl_host_priv *host_priv = ap->host->private_data;
0655     void __iomem *hcr_base = host_priv->hcr_base;
0656     u32 temp;
0657 
0658     /* ack. any pending IRQs for this controller/port */
0659     temp = ioread32(hcr_base + HSTATUS);
0660 
0661     ata_port_dbg(ap, "pending IRQs = 0x%x\n", (temp & 0x3F));
0662 
0663     if (temp & 0x3F)
0664         iowrite32((temp & 0x3F), hcr_base + HSTATUS);
0665 
0666     /* enable interrupts on the controller/port */
0667     temp = ioread32(hcr_base + HCONTROL);
0668     iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
0669 
0670     ata_port_dbg(ap, "HControl = 0x%x, HStatus = 0x%x\n",
0671         ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
0672 }
0673 
0674 static void sata_fsl_pmp_attach(struct ata_port *ap)
0675 {
0676     struct sata_fsl_host_priv *host_priv = ap->host->private_data;
0677     void __iomem *hcr_base = host_priv->hcr_base;
0678     u32 temp;
0679 
0680     temp = ioread32(hcr_base + HCONTROL);
0681     iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
0682 }
0683 
0684 static void sata_fsl_pmp_detach(struct ata_port *ap)
0685 {
0686     struct sata_fsl_host_priv *host_priv = ap->host->private_data;
0687     void __iomem *hcr_base = host_priv->hcr_base;
0688     u32 temp;
0689 
0690     temp = ioread32(hcr_base + HCONTROL);
0691     temp &= ~HCONTROL_PMP_ATTACHED;
0692     iowrite32(temp, hcr_base + HCONTROL);
0693 
0694     /* enable interrupts on the controller/port */
0695     temp = ioread32(hcr_base + HCONTROL);
0696     iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
0697 
0698 }
0699 
0700 static int sata_fsl_port_start(struct ata_port *ap)
0701 {
0702     struct device *dev = ap->host->dev;
0703     struct sata_fsl_port_priv *pp;
0704     void *mem;
0705     dma_addr_t mem_dma;
0706     struct sata_fsl_host_priv *host_priv = ap->host->private_data;
0707     void __iomem *hcr_base = host_priv->hcr_base;
0708     u32 temp;
0709 
0710     pp = kzalloc(sizeof(*pp), GFP_KERNEL);
0711     if (!pp)
0712         return -ENOMEM;
0713 
0714     mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
0715                  GFP_KERNEL);
0716     if (!mem) {
0717         kfree(pp);
0718         return -ENOMEM;
0719     }
0720 
0721     pp->cmdslot = mem;
0722     pp->cmdslot_paddr = mem_dma;
0723 
0724     mem += SATA_FSL_CMD_SLOT_SIZE;
0725     mem_dma += SATA_FSL_CMD_SLOT_SIZE;
0726 
0727     pp->cmdentry = mem;
0728     pp->cmdentry_paddr = mem_dma;
0729 
0730     ap->private_data = pp;
0731 
0732     ata_port_dbg(ap, "CHBA = 0x%lx, cmdentry_phys = 0x%lx\n",
0733         (unsigned long)pp->cmdslot_paddr,
0734         (unsigned long)pp->cmdentry_paddr);
0735 
0736     /* Now, update the CHBA register in host controller cmd register set */
0737     iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
0738 
0739     /*
0740      * Now, we can bring the controller on-line & also initiate
0741      * the COMINIT sequence, we simply return here and the boot-probing
0742      * & device discovery process is re-initiated by libATA using a
0743      * Softreset EH (dummy) session. Hence, boot probing and device
0744      * discovey will be part of sata_fsl_softreset() callback.
0745      */
0746 
0747     temp = ioread32(hcr_base + HCONTROL);
0748     iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
0749 
0750     ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
0751     ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
0752     ata_port_dbg(ap, "CHBA  = 0x%x\n", ioread32(hcr_base + CHBA));
0753 
0754     return 0;
0755 }
0756 
0757 static void sata_fsl_port_stop(struct ata_port *ap)
0758 {
0759     struct device *dev = ap->host->dev;
0760     struct sata_fsl_port_priv *pp = ap->private_data;
0761     struct sata_fsl_host_priv *host_priv = ap->host->private_data;
0762     void __iomem *hcr_base = host_priv->hcr_base;
0763     u32 temp;
0764 
0765     /*
0766      * Force host controller to go off-line, aborting current operations
0767      */
0768     temp = ioread32(hcr_base + HCONTROL);
0769     temp &= ~HCONTROL_ONLINE_PHY_RST;
0770     temp |= HCONTROL_FORCE_OFFLINE;
0771     iowrite32(temp, hcr_base + HCONTROL);
0772 
0773     /* Poll for controller to go offline - should happen immediately */
0774     ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
0775 
0776     ap->private_data = NULL;
0777     dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
0778               pp->cmdslot, pp->cmdslot_paddr);
0779 
0780     kfree(pp);
0781 }
0782 
0783 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
0784 {
0785     struct sata_fsl_host_priv *host_priv = ap->host->private_data;
0786     void __iomem *hcr_base = host_priv->hcr_base;
0787     struct ata_taskfile tf;
0788     u32 temp;
0789 
0790     temp = ioread32(hcr_base + SIGNATURE);
0791 
0792     ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
0793     ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
0794 
0795     tf.lbah = (temp >> 24) & 0xff;
0796     tf.lbam = (temp >> 16) & 0xff;
0797     tf.lbal = (temp >> 8) & 0xff;
0798     tf.nsect = temp & 0xff;
0799 
0800     return ata_port_classify(ap, &tf);
0801 }
0802 
0803 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
0804                     unsigned long deadline)
0805 {
0806     struct ata_port *ap = link->ap;
0807     struct sata_fsl_host_priv *host_priv = ap->host->private_data;
0808     void __iomem *hcr_base = host_priv->hcr_base;
0809     u32 temp;
0810     int i = 0;
0811     unsigned long start_jiffies;
0812 
0813 try_offline_again:
0814     /*
0815      * Force host controller to go off-line, aborting current operations
0816      */
0817     temp = ioread32(hcr_base + HCONTROL);
0818     temp &= ~HCONTROL_ONLINE_PHY_RST;
0819     iowrite32(temp, hcr_base + HCONTROL);
0820 
0821     /* Poll for controller to go offline */
0822     temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
0823                  1, 500);
0824 
0825     if (temp & ONLINE) {
0826         ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i);
0827 
0828         /*
0829          * Try to offline controller atleast twice
0830          */
0831         i++;
0832         if (i == 2)
0833             goto err;
0834         else
0835             goto try_offline_again;
0836     }
0837 
0838     ata_port_dbg(ap, "hardreset, controller off-lined\n"
0839              "HStatus = 0x%x HControl = 0x%x\n",
0840              ioread32(hcr_base + HSTATUS),
0841              ioread32(hcr_base + HCONTROL));
0842 
0843     /*
0844      * PHY reset should remain asserted for atleast 1ms
0845      */
0846     ata_msleep(ap, 1);
0847 
0848     sata_set_spd(link);
0849 
0850     /*
0851      * Now, bring the host controller online again, this can take time
0852      * as PHY reset and communication establishment, 1st D2H FIS and
0853      * device signature update is done, on safe side assume 500ms
0854      * NOTE : Host online status may be indicated immediately!!
0855      */
0856 
0857     temp = ioread32(hcr_base + HCONTROL);
0858     temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
0859     temp |= HCONTROL_PMP_ATTACHED;
0860     iowrite32(temp, hcr_base + HCONTROL);
0861 
0862     temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
0863 
0864     if (!(temp & ONLINE)) {
0865         ata_port_err(ap, "Hardreset failed, not on-lined\n");
0866         goto err;
0867     }
0868 
0869     ata_port_dbg(ap, "controller off-lined & on-lined\n"
0870              "HStatus = 0x%x HControl = 0x%x\n",
0871              ioread32(hcr_base + HSTATUS),
0872              ioread32(hcr_base + HCONTROL));
0873 
0874     /*
0875      * First, wait for the PHYRDY change to occur before waiting for
0876      * the signature, and also verify if SStatus indicates device
0877      * presence
0878      */
0879 
0880     temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
0881     if ((!(temp & 0x10)) || ata_link_offline(link)) {
0882         ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n",
0883                   ioread32(hcr_base + HSTATUS));
0884         *class = ATA_DEV_NONE;
0885         return 0;
0886     }
0887 
0888     /*
0889      * Wait for the first D2H from device,i.e,signature update notification
0890      */
0891     start_jiffies = jiffies;
0892     temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
0893             500, jiffies_to_msecs(deadline - start_jiffies));
0894 
0895     if ((temp & 0xFF) != 0x18) {
0896         ata_port_warn(ap, "No Signature Update\n");
0897         *class = ATA_DEV_NONE;
0898         goto do_followup_srst;
0899     } else {
0900         ata_port_info(ap, "Signature Update detected @ %d msecs\n",
0901                   jiffies_to_msecs(jiffies - start_jiffies));
0902         *class = sata_fsl_dev_classify(ap);
0903         return 0;
0904     }
0905 
0906 do_followup_srst:
0907     /*
0908      * request libATA to perform follow-up softreset
0909      */
0910     return -EAGAIN;
0911 
0912 err:
0913     return -EIO;
0914 }
0915 
0916 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
0917                     unsigned long deadline)
0918 {
0919     struct ata_port *ap = link->ap;
0920     struct sata_fsl_port_priv *pp = ap->private_data;
0921     struct sata_fsl_host_priv *host_priv = ap->host->private_data;
0922     void __iomem *hcr_base = host_priv->hcr_base;
0923     int pmp = sata_srst_pmp(link);
0924     u32 temp;
0925     struct ata_taskfile tf;
0926     u8 *cfis;
0927     u32 Serror;
0928 
0929     if (ata_link_offline(link)) {
0930         *class = ATA_DEV_NONE;
0931         return 0;
0932     }
0933 
0934     /*
0935      * Send a device reset (SRST) explicitly on command slot #0
0936      * Check : will the command queue (reg) be cleared during offlining ??
0937      * Also we will be online only if Phy commn. has been established
0938      * and device presence has been detected, therefore if we have
0939      * reached here, we can send a command to the target device
0940      */
0941 
0942     ata_tf_init(link->device, &tf);
0943     cfis = (u8 *) &pp->cmdentry->cfis;
0944 
0945     /* device reset/SRST is a control register update FIS, uses tag0 */
0946     sata_fsl_setup_cmd_hdr_entry(ap, pp, 0,
0947         SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
0948 
0949     tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
0950     ata_tf_to_fis(&tf, pmp, 0, cfis);
0951 
0952     ata_port_dbg(ap, "Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
0953         cfis[0], cfis[1], cfis[2], cfis[3]);
0954 
0955     /*
0956      * Queue SRST command to the controller/device, ensure that no
0957      * other commands are active on the controller/device
0958      */
0959 
0960     ata_port_dbg(ap, "CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
0961         ioread32(CQ + hcr_base),
0962         ioread32(CA + hcr_base), ioread32(CC + hcr_base));
0963 
0964     iowrite32(0xFFFF, CC + hcr_base);
0965     if (pmp != SATA_PMP_CTRL_PORT)
0966         iowrite32(pmp, CQPMP + hcr_base);
0967     iowrite32(1, CQ + hcr_base);
0968 
0969     temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
0970     if (temp & 0x1) {
0971         ata_port_warn(ap, "ATA_SRST issue failed\n");
0972 
0973         ata_port_dbg(ap, "Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
0974             ioread32(CQ + hcr_base),
0975             ioread32(CA + hcr_base), ioread32(CC + hcr_base));
0976 
0977         sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
0978 
0979         ata_port_dbg(ap, "HStatus = 0x%x HControl = 0x%x Serror = 0x%x\n",
0980                  ioread32(hcr_base + HSTATUS),
0981                  ioread32(hcr_base + HCONTROL),
0982                  Serror);
0983         goto err;
0984     }
0985 
0986     ata_msleep(ap, 1);
0987 
0988     /*
0989      * SATA device enters reset state after receiving a Control register
0990      * FIS with SRST bit asserted and it awaits another H2D Control reg.
0991      * FIS with SRST bit cleared, then the device does internal diags &
0992      * initialization, followed by indicating it's initialization status
0993      * using ATA signature D2H register FIS to the host controller.
0994      */
0995 
0996     sata_fsl_setup_cmd_hdr_entry(ap, pp, 0,
0997                      CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
0998                      0, 0, 5);
0999 
1000     tf.ctl &= ~ATA_SRST;    /* 2nd H2D Ctl. register FIS */
1001     ata_tf_to_fis(&tf, pmp, 0, cfis);
1002 
1003     if (pmp != SATA_PMP_CTRL_PORT)
1004         iowrite32(pmp, CQPMP + hcr_base);
1005     iowrite32(1, CQ + hcr_base);
1006     ata_msleep(ap, 150);        /* ?? */
1007 
1008     /*
1009      * The above command would have signalled an interrupt on command
1010      * complete, which needs special handling, by clearing the Nth
1011      * command bit of the CCreg
1012      */
1013     iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
1014 
1015     *class = ATA_DEV_NONE;
1016 
1017     /* Verify if SStatus indicates device presence */
1018     if (ata_link_online(link)) {
1019         /*
1020          * if we are here, device presence has been detected,
1021          * 1st D2H FIS would have been received, but sfis in
1022          * command desc. is not updated, but signature register
1023          * would have been updated
1024          */
1025 
1026         *class = sata_fsl_dev_classify(ap);
1027 
1028         ata_port_dbg(ap, "ccreg = 0x%x\n", ioread32(hcr_base + CC));
1029         ata_port_dbg(ap, "cereg = 0x%x\n", ioread32(hcr_base + CE));
1030     }
1031 
1032     return 0;
1033 
1034 err:
1035     return -EIO;
1036 }
1037 
1038 static void sata_fsl_error_handler(struct ata_port *ap)
1039 {
1040     sata_pmp_error_handler(ap);
1041 }
1042 
1043 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1044 {
1045     if (qc->flags & ATA_QCFLAG_FAILED)
1046         qc->err_mask |= AC_ERR_OTHER;
1047 
1048     if (qc->err_mask) {
1049         /* make DMA engine forget about the failed command */
1050 
1051     }
1052 }
1053 
1054 static void sata_fsl_error_intr(struct ata_port *ap)
1055 {
1056     struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1057     void __iomem *hcr_base = host_priv->hcr_base;
1058     u32 hstatus, dereg=0, cereg = 0, SError = 0;
1059     unsigned int err_mask = 0, action = 0;
1060     int freeze = 0, abort=0;
1061     struct ata_link *link = NULL;
1062     struct ata_queued_cmd *qc = NULL;
1063     struct ata_eh_info *ehi;
1064 
1065     hstatus = ioread32(hcr_base + HSTATUS);
1066     cereg = ioread32(hcr_base + CE);
1067 
1068     /* first, analyze and record host port events */
1069     link = &ap->link;
1070     ehi = &link->eh_info;
1071     ata_ehi_clear_desc(ehi);
1072 
1073     /*
1074      * Handle & Clear SError
1075      */
1076 
1077     sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1078     if (unlikely(SError & 0xFFFF0000))
1079         sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
1080 
1081     ata_port_dbg(ap, "hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1082         hstatus, cereg, ioread32(hcr_base + DE), SError);
1083 
1084     /* handle fatal errors */
1085     if (hstatus & FATAL_ERROR_DECODE) {
1086         ehi->err_mask |= AC_ERR_ATA_BUS;
1087         ehi->action |= ATA_EH_SOFTRESET;
1088 
1089         freeze = 1;
1090     }
1091 
1092     /* Handle SDB FIS receive & notify update */
1093     if (hstatus & INT_ON_SNOTIFY_UPDATE)
1094         sata_async_notification(ap);
1095 
1096     /* Handle PHYRDY change notification */
1097     if (hstatus & INT_ON_PHYRDY_CHG) {
1098         ata_port_dbg(ap, "PHYRDY change indication\n");
1099 
1100         /* Setup a soft-reset EH action */
1101         ata_ehi_hotplugged(ehi);
1102         ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1103         freeze = 1;
1104     }
1105 
1106     /* handle single device errors */
1107     if (cereg) {
1108         /*
1109          * clear the command error, also clears queue to the device
1110          * in error, and we can (re)issue commands to this device.
1111          * When a device is in error all commands queued into the
1112          * host controller and at the device are considered aborted
1113          * and the queue for that device is stopped. Now, after
1114          * clearing the device error, we can issue commands to the
1115          * device to interrogate it to find the source of the error.
1116          */
1117         abort = 1;
1118 
1119         ata_port_dbg(ap, "single device error, CE=0x%x, DE=0x%x\n",
1120             ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1121 
1122         /* find out the offending link and qc */
1123         if (ap->nr_pmp_links) {
1124             unsigned int dev_num;
1125 
1126             dereg = ioread32(hcr_base + DE);
1127             iowrite32(dereg, hcr_base + DE);
1128             iowrite32(cereg, hcr_base + CE);
1129 
1130             dev_num = ffs(dereg) - 1;
1131             if (dev_num < ap->nr_pmp_links && dereg != 0) {
1132                 link = &ap->pmp_link[dev_num];
1133                 ehi = &link->eh_info;
1134                 qc = ata_qc_from_tag(ap, link->active_tag);
1135                 /*
1136                  * We should consider this as non fatal error,
1137                                  * and TF must be updated as done below.
1138                          */
1139 
1140                 err_mask |= AC_ERR_DEV;
1141 
1142             } else {
1143                 err_mask |= AC_ERR_HSM;
1144                 action |= ATA_EH_HARDRESET;
1145                 freeze = 1;
1146             }
1147         } else {
1148             dereg = ioread32(hcr_base + DE);
1149             iowrite32(dereg, hcr_base + DE);
1150             iowrite32(cereg, hcr_base + CE);
1151 
1152             qc = ata_qc_from_tag(ap, link->active_tag);
1153             /*
1154              * We should consider this as non fatal error,
1155                          * and TF must be updated as done below.
1156                     */
1157             err_mask |= AC_ERR_DEV;
1158         }
1159     }
1160 
1161     /* record error info */
1162     if (qc)
1163         qc->err_mask |= err_mask;
1164     else
1165         ehi->err_mask |= err_mask;
1166 
1167     ehi->action |= action;
1168 
1169     /* freeze or abort */
1170     if (freeze)
1171         ata_port_freeze(ap);
1172     else if (abort) {
1173         if (qc)
1174             ata_link_abort(qc->dev->link);
1175         else
1176             ata_port_abort(ap);
1177     }
1178 }
1179 
1180 static void sata_fsl_host_intr(struct ata_port *ap)
1181 {
1182     struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1183     void __iomem *hcr_base = host_priv->hcr_base;
1184     u32 hstatus, done_mask = 0;
1185     struct ata_queued_cmd *qc;
1186     u32 SError;
1187     u32 tag;
1188     u32 status_mask = INT_ON_ERROR;
1189 
1190     hstatus = ioread32(hcr_base + HSTATUS);
1191 
1192     sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1193 
1194     /* Read command completed register */
1195     done_mask = ioread32(hcr_base + CC);
1196 
1197     /* Workaround for data length mismatch errata */
1198     if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
1199         ata_qc_for_each_with_internal(ap, qc, tag) {
1200             if (qc && ata_is_atapi(qc->tf.protocol)) {
1201                 u32 hcontrol;
1202                 /* Set HControl[27] to clear error registers */
1203                 hcontrol = ioread32(hcr_base + HCONTROL);
1204                 iowrite32(hcontrol | CLEAR_ERROR,
1205                         hcr_base + HCONTROL);
1206 
1207                 /* Clear HControl[27] */
1208                 iowrite32(hcontrol & ~CLEAR_ERROR,
1209                         hcr_base + HCONTROL);
1210 
1211                 /* Clear SError[E] bit */
1212                 sata_fsl_scr_write(&ap->link, SCR_ERROR,
1213                         SError);
1214 
1215                 /* Ignore fatal error and device error */
1216                 status_mask &= ~(INT_ON_SINGL_DEVICE_ERR
1217                         | INT_ON_FATAL_ERR);
1218                 break;
1219             }
1220         }
1221     }
1222 
1223     if (unlikely(SError & 0xFFFF0000)) {
1224         ata_port_dbg(ap, "serror @host_intr : 0x%x\n", SError);
1225         sata_fsl_error_intr(ap);
1226     }
1227 
1228     if (unlikely(hstatus & status_mask)) {
1229         ata_port_dbg(ap, "error interrupt!!\n");
1230         sata_fsl_error_intr(ap);
1231         return;
1232     }
1233 
1234     ata_port_dbg(ap, "Status of all queues :\n");
1235     ata_port_dbg(ap, "done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n",
1236         done_mask,
1237         ioread32(hcr_base + CA),
1238         ioread32(hcr_base + CE),
1239         ioread32(hcr_base + CQ),
1240         ap->qc_active);
1241 
1242     if (done_mask & ap->qc_active) {
1243         int i;
1244         /* clear CC bit, this will also complete the interrupt */
1245         iowrite32(done_mask, hcr_base + CC);
1246 
1247         ata_port_dbg(ap, "Status of all queues: done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1248             done_mask, ioread32(hcr_base + CA),
1249             ioread32(hcr_base + CE));
1250 
1251         for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1252             if (done_mask & (1 << i))
1253                 ata_port_dbg(ap, "completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1254                      i, ioread32(hcr_base + CC),
1255                      ioread32(hcr_base + CA));
1256         }
1257         ata_qc_complete_multiple(ap, ata_qc_get_active(ap) ^ done_mask);
1258         return;
1259 
1260     } else if ((ap->qc_active & (1ULL << ATA_TAG_INTERNAL))) {
1261         iowrite32(1, hcr_base + CC);
1262         qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1263 
1264         ata_port_dbg(ap, "completing non-ncq cmd, CC=0x%x\n",
1265              ioread32(hcr_base + CC));
1266 
1267         if (qc) {
1268             ata_qc_complete(qc);
1269         }
1270     } else {
1271         /* Spurious Interrupt!! */
1272         ata_port_dbg(ap, "spurious interrupt!!, CC = 0x%x\n",
1273             ioread32(hcr_base + CC));
1274         iowrite32(done_mask, hcr_base + CC);
1275         return;
1276     }
1277 }
1278 
1279 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1280 {
1281     struct ata_host *host = dev_instance;
1282     struct sata_fsl_host_priv *host_priv = host->private_data;
1283     void __iomem *hcr_base = host_priv->hcr_base;
1284     u32 interrupt_enables;
1285     unsigned handled = 0;
1286     struct ata_port *ap;
1287 
1288     /* ack. any pending IRQs for this controller/port */
1289     interrupt_enables = ioread32(hcr_base + HSTATUS);
1290     interrupt_enables &= 0x3F;
1291 
1292     if (!interrupt_enables)
1293         return IRQ_NONE;
1294 
1295     spin_lock(&host->lock);
1296 
1297     /* Assuming one port per host controller */
1298 
1299     ap = host->ports[0];
1300     if (ap) {
1301         sata_fsl_host_intr(ap);
1302     } else {
1303         dev_warn(host->dev, "interrupt on disabled port 0\n");
1304     }
1305 
1306     iowrite32(interrupt_enables, hcr_base + HSTATUS);
1307     handled = 1;
1308 
1309     spin_unlock(&host->lock);
1310 
1311     return IRQ_RETVAL(handled);
1312 }
1313 
1314 /*
1315  * Multiple ports are represented by multiple SATA controllers with
1316  * one port per controller
1317  */
1318 static int sata_fsl_init_controller(struct ata_host *host)
1319 {
1320     struct sata_fsl_host_priv *host_priv = host->private_data;
1321     void __iomem *hcr_base = host_priv->hcr_base;
1322     u32 temp;
1323 
1324     /*
1325      * NOTE : We cannot bring the controller online before setting
1326      * the CHBA, hence main controller initialization is done as
1327      * part of the port_start() callback
1328      */
1329 
1330     /* sata controller to operate in enterprise mode */
1331     temp = ioread32(hcr_base + HCONTROL);
1332     iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
1333 
1334     /* ack. any pending IRQs for this controller/port */
1335     temp = ioread32(hcr_base + HSTATUS);
1336     if (temp & 0x3F)
1337         iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1338 
1339     /* Keep interrupts disabled on the controller */
1340     temp = ioread32(hcr_base + HCONTROL);
1341     iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1342 
1343     /* Disable interrupt coalescing control(icc), for the moment */
1344     dev_dbg(host->dev, "icc = 0x%x\n", ioread32(hcr_base + ICC));
1345     iowrite32(0x01000000, hcr_base + ICC);
1346 
1347     /* clear error registers, SError is cleared by libATA  */
1348     iowrite32(0x00000FFFF, hcr_base + CE);
1349     iowrite32(0x00000FFFF, hcr_base + DE);
1350 
1351     /*
1352      * reset the number of command complete bits which will cause the
1353      * interrupt to be signaled
1354      */
1355     fsl_sata_set_irq_coalescing(host, intr_coalescing_count,
1356             intr_coalescing_ticks);
1357 
1358     /*
1359      * host controller will be brought on-line, during xx_port_start()
1360      * callback, that should also initiate the OOB, COMINIT sequence
1361      */
1362 
1363     dev_dbg(host->dev, "HStatus = 0x%x HControl = 0x%x\n",
1364         ioread32(hcr_base + HSTATUS), ioread32(hcr_base + HCONTROL));
1365 
1366     return 0;
1367 }
1368 
1369 static void sata_fsl_host_stop(struct ata_host *host)
1370 {
1371         struct sata_fsl_host_priv *host_priv = host->private_data;
1372 
1373         iounmap(host_priv->hcr_base);
1374         kfree(host_priv);
1375 }
1376 
1377 /*
1378  * scsi mid-layer and libata interface structures
1379  */
1380 static struct scsi_host_template sata_fsl_sht = {
1381     ATA_NCQ_SHT_QD("sata_fsl", SATA_FSL_QUEUE_DEPTH),
1382     .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1383     .dma_boundary = ATA_DMA_BOUNDARY,
1384 };
1385 
1386 static struct ata_port_operations sata_fsl_ops = {
1387     .inherits       = &sata_pmp_port_ops,
1388 
1389     .qc_defer = ata_std_qc_defer,
1390     .qc_prep = sata_fsl_qc_prep,
1391     .qc_issue = sata_fsl_qc_issue,
1392     .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1393 
1394     .scr_read = sata_fsl_scr_read,
1395     .scr_write = sata_fsl_scr_write,
1396 
1397     .freeze = sata_fsl_freeze,
1398     .thaw = sata_fsl_thaw,
1399     .softreset = sata_fsl_softreset,
1400     .hardreset = sata_fsl_hardreset,
1401     .pmp_softreset = sata_fsl_softreset,
1402     .error_handler = sata_fsl_error_handler,
1403     .post_internal_cmd = sata_fsl_post_internal_cmd,
1404 
1405     .port_start = sata_fsl_port_start,
1406     .port_stop = sata_fsl_port_stop,
1407 
1408     .host_stop      = sata_fsl_host_stop,
1409 
1410     .pmp_attach = sata_fsl_pmp_attach,
1411     .pmp_detach = sata_fsl_pmp_detach,
1412 };
1413 
1414 static const struct ata_port_info sata_fsl_port_info[] = {
1415     {
1416      .flags = SATA_FSL_HOST_FLAGS,
1417      .pio_mask = ATA_PIO4,
1418      .udma_mask = ATA_UDMA6,
1419      .port_ops = &sata_fsl_ops,
1420      },
1421 };
1422 
1423 static int sata_fsl_probe(struct platform_device *ofdev)
1424 {
1425     int retval = -ENXIO;
1426     void __iomem *hcr_base = NULL;
1427     void __iomem *ssr_base = NULL;
1428     void __iomem *csr_base = NULL;
1429     struct sata_fsl_host_priv *host_priv = NULL;
1430     int irq;
1431     struct ata_host *host = NULL;
1432     u32 temp;
1433 
1434     struct ata_port_info pi = sata_fsl_port_info[0];
1435     const struct ata_port_info *ppi[] = { &pi, NULL };
1436 
1437     dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n");
1438 
1439     hcr_base = of_iomap(ofdev->dev.of_node, 0);
1440     if (!hcr_base)
1441         goto error_exit_with_cleanup;
1442 
1443     ssr_base = hcr_base + 0x100;
1444     csr_base = hcr_base + 0x140;
1445 
1446     if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
1447         temp = ioread32(csr_base + TRANSCFG);
1448         temp = temp & 0xffffffe0;
1449         iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
1450     }
1451 
1452     dev_dbg(&ofdev->dev, "@reset i/o = 0x%x\n",
1453         ioread32(csr_base + TRANSCFG));
1454 
1455     host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1456     if (!host_priv)
1457         goto error_exit_with_cleanup;
1458 
1459     host_priv->hcr_base = hcr_base;
1460     host_priv->ssr_base = ssr_base;
1461     host_priv->csr_base = csr_base;
1462 
1463     irq = platform_get_irq(ofdev, 0);
1464     if (irq < 0) {
1465         retval = irq;
1466         goto error_exit_with_cleanup;
1467     }
1468     host_priv->irq = irq;
1469 
1470     if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
1471         host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
1472     else
1473         host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
1474 
1475     /* allocate host structure */
1476     host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1477     if (!host) {
1478         retval = -ENOMEM;
1479         goto error_exit_with_cleanup;
1480     }
1481 
1482     /* host->iomap is not used currently */
1483     host->private_data = host_priv;
1484 
1485     /* initialize host controller */
1486     sata_fsl_init_controller(host);
1487 
1488     /*
1489      * Now, register with libATA core, this will also initiate the
1490      * device discovery process, invoking our port_start() handler &
1491      * error_handler() to execute a dummy Softreset EH session
1492      */
1493     ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1494               &sata_fsl_sht);
1495 
1496     host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show;
1497     host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store;
1498     sysfs_attr_init(&host_priv->intr_coalescing.attr);
1499     host_priv->intr_coalescing.attr.name = "intr_coalescing";
1500     host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR;
1501     retval = device_create_file(host->dev, &host_priv->intr_coalescing);
1502     if (retval)
1503         goto error_exit_with_cleanup;
1504 
1505     host_priv->rx_watermark.show = fsl_sata_rx_watermark_show;
1506     host_priv->rx_watermark.store = fsl_sata_rx_watermark_store;
1507     sysfs_attr_init(&host_priv->rx_watermark.attr);
1508     host_priv->rx_watermark.attr.name = "rx_watermark";
1509     host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR;
1510     retval = device_create_file(host->dev, &host_priv->rx_watermark);
1511     if (retval) {
1512         device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1513         goto error_exit_with_cleanup;
1514     }
1515 
1516     return 0;
1517 
1518 error_exit_with_cleanup:
1519 
1520     if (host)
1521         ata_host_detach(host);
1522 
1523     if (hcr_base)
1524         iounmap(hcr_base);
1525     kfree(host_priv);
1526 
1527     return retval;
1528 }
1529 
1530 static int sata_fsl_remove(struct platform_device *ofdev)
1531 {
1532     struct ata_host *host = platform_get_drvdata(ofdev);
1533     struct sata_fsl_host_priv *host_priv = host->private_data;
1534 
1535     device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1536     device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
1537 
1538     ata_host_detach(host);
1539 
1540     return 0;
1541 }
1542 
1543 #ifdef CONFIG_PM_SLEEP
1544 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
1545 {
1546     struct ata_host *host = platform_get_drvdata(op);
1547 
1548     ata_host_suspend(host, state);
1549     return 0;
1550 }
1551 
1552 static int sata_fsl_resume(struct platform_device *op)
1553 {
1554     struct ata_host *host = platform_get_drvdata(op);
1555     struct sata_fsl_host_priv *host_priv = host->private_data;
1556     int ret;
1557     void __iomem *hcr_base = host_priv->hcr_base;
1558     struct ata_port *ap = host->ports[0];
1559     struct sata_fsl_port_priv *pp = ap->private_data;
1560 
1561     ret = sata_fsl_init_controller(host);
1562     if (ret) {
1563         dev_err(&op->dev, "Error initializing hardware\n");
1564         return ret;
1565     }
1566 
1567     /* Recovery the CHBA register in host controller cmd register set */
1568     iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1569 
1570     iowrite32((ioread32(hcr_base + HCONTROL)
1571                 | HCONTROL_ONLINE_PHY_RST
1572                 | HCONTROL_SNOOP_ENABLE
1573                 | HCONTROL_PMP_ATTACHED),
1574             hcr_base + HCONTROL);
1575 
1576     ata_host_resume(host);
1577     return 0;
1578 }
1579 #endif
1580 
1581 static const struct of_device_id fsl_sata_match[] = {
1582     { .compatible = "fsl,pq-sata", },
1583     { .compatible = "fsl,pq-sata-v2", },
1584     { /* sentinel */ }
1585 };
1586 
1587 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1588 
1589 static struct platform_driver fsl_sata_driver = {
1590     .driver = {
1591         .name = "fsl-sata",
1592         .of_match_table = fsl_sata_match,
1593     },
1594     .probe      = sata_fsl_probe,
1595     .remove     = sata_fsl_remove,
1596 #ifdef CONFIG_PM_SLEEP
1597     .suspend    = sata_fsl_suspend,
1598     .resume     = sata_fsl_resume,
1599 #endif
1600 };
1601 
1602 module_platform_driver(fsl_sata_driver);
1603 
1604 MODULE_LICENSE("GPL");
1605 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1606 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1607 MODULE_VERSION("1.10");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!