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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  pdc_adma.c - Pacific Digital Corporation ADMA
0004  *
0005  *  Maintained by:  Tejun Heo <tj@kernel.org>
0006  *
0007  *  Copyright 2005 Mark Lord
0008  *
0009  *  libata documentation is available via 'make {ps|pdf}docs',
0010  *  as Documentation/driver-api/libata.rst
0011  *
0012  *  Supports ATA disks in single-packet ADMA mode.
0013  *  Uses PIO for everything else.
0014  *
0015  *  TODO:  Use ADMA transfers for ATAPI devices, when possible.
0016  *  This requires careful attention to a number of quirks of the chip.
0017  */
0018 
0019 #include <linux/kernel.h>
0020 #include <linux/module.h>
0021 #include <linux/gfp.h>
0022 #include <linux/pci.h>
0023 #include <linux/blkdev.h>
0024 #include <linux/delay.h>
0025 #include <linux/interrupt.h>
0026 #include <linux/device.h>
0027 #include <scsi/scsi_host.h>
0028 #include <linux/libata.h>
0029 
0030 #define DRV_NAME    "pdc_adma"
0031 #define DRV_VERSION "1.0"
0032 
0033 /* macro to calculate base address for ATA regs */
0034 #define ADMA_ATA_REGS(base, port_no)    ((base) + ((port_no) * 0x40))
0035 
0036 /* macro to calculate base address for ADMA regs */
0037 #define ADMA_REGS(base, port_no)    ((base) + 0x80 + ((port_no) * 0x20))
0038 
0039 /* macro to obtain addresses from ata_port */
0040 #define ADMA_PORT_REGS(ap) \
0041     ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
0042 
0043 enum {
0044     ADMA_MMIO_BAR       = 4,
0045 
0046     ADMA_PORTS      = 2,
0047     ADMA_CPB_BYTES      = 40,
0048     ADMA_PRD_BYTES      = LIBATA_MAX_PRD * 16,
0049     ADMA_PKT_BYTES      = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
0050 
0051     ADMA_DMA_BOUNDARY   = 0xffffffff,
0052 
0053     /* global register offsets */
0054     ADMA_MODE_LOCK      = 0x00c7,
0055 
0056     /* per-channel register offsets */
0057     ADMA_CONTROL        = 0x0000, /* ADMA control */
0058     ADMA_STATUS     = 0x0002, /* ADMA status */
0059     ADMA_CPB_COUNT      = 0x0004, /* CPB count */
0060     ADMA_CPB_CURRENT    = 0x000c, /* current CPB address */
0061     ADMA_CPB_NEXT       = 0x000c, /* next CPB address */
0062     ADMA_CPB_LOOKUP     = 0x0010, /* CPB lookup table */
0063     ADMA_FIFO_IN        = 0x0014, /* input FIFO threshold */
0064     ADMA_FIFO_OUT       = 0x0016, /* output FIFO threshold */
0065 
0066     /* ADMA_CONTROL register bits */
0067     aNIEN           = (1 << 8), /* irq mask: 1==masked */
0068     aGO         = (1 << 7), /* packet trigger ("Go!") */
0069     aRSTADM         = (1 << 5), /* ADMA logic reset */
0070     aPIOMD4         = 0x0003,   /* PIO mode 4 */
0071 
0072     /* ADMA_STATUS register bits */
0073     aPSD            = (1 << 6),
0074     aUIRQ           = (1 << 4),
0075     aPERR           = (1 << 0),
0076 
0077     /* CPB bits */
0078     cDONE           = (1 << 0),
0079     cATERR          = (1 << 3),
0080 
0081     cVLD            = (1 << 0),
0082     cDAT            = (1 << 2),
0083     cIEN            = (1 << 3),
0084 
0085     /* PRD bits */
0086     pORD            = (1 << 4),
0087     pDIRO           = (1 << 5),
0088     pEND            = (1 << 7),
0089 
0090     /* ATA register flags */
0091     rIGN            = (1 << 5),
0092     rEND            = (1 << 7),
0093 
0094     /* ATA register addresses */
0095     ADMA_REGS_CONTROL   = 0x0e,
0096     ADMA_REGS_SECTOR_COUNT  = 0x12,
0097     ADMA_REGS_LBA_LOW   = 0x13,
0098     ADMA_REGS_LBA_MID   = 0x14,
0099     ADMA_REGS_LBA_HIGH  = 0x15,
0100     ADMA_REGS_DEVICE    = 0x16,
0101     ADMA_REGS_COMMAND   = 0x17,
0102 
0103     /* PCI device IDs */
0104     board_1841_idx      = 0,    /* ADMA 2-port controller */
0105 };
0106 
0107 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
0108 
0109 struct adma_port_priv {
0110     u8          *pkt;
0111     dma_addr_t      pkt_dma;
0112     adma_state_t        state;
0113 };
0114 
0115 static int adma_ata_init_one(struct pci_dev *pdev,
0116                 const struct pci_device_id *ent);
0117 static int adma_port_start(struct ata_port *ap);
0118 static void adma_port_stop(struct ata_port *ap);
0119 static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc);
0120 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
0121 static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
0122 static void adma_freeze(struct ata_port *ap);
0123 static void adma_thaw(struct ata_port *ap);
0124 static int adma_prereset(struct ata_link *link, unsigned long deadline);
0125 
0126 static struct scsi_host_template adma_ata_sht = {
0127     ATA_BASE_SHT(DRV_NAME),
0128     .sg_tablesize       = LIBATA_MAX_PRD,
0129     .dma_boundary       = ADMA_DMA_BOUNDARY,
0130 };
0131 
0132 static struct ata_port_operations adma_ata_ops = {
0133     .inherits       = &ata_sff_port_ops,
0134 
0135     .lost_interrupt     = ATA_OP_NULL,
0136 
0137     .check_atapi_dma    = adma_check_atapi_dma,
0138     .qc_prep        = adma_qc_prep,
0139     .qc_issue       = adma_qc_issue,
0140 
0141     .freeze         = adma_freeze,
0142     .thaw           = adma_thaw,
0143     .prereset       = adma_prereset,
0144 
0145     .port_start     = adma_port_start,
0146     .port_stop      = adma_port_stop,
0147 };
0148 
0149 static struct ata_port_info adma_port_info[] = {
0150     /* board_1841_idx */
0151     {
0152         .flags      = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_POLLING,
0153         .pio_mask   = ATA_PIO4_ONLY,
0154         .udma_mask  = ATA_UDMA4,
0155         .port_ops   = &adma_ata_ops,
0156     },
0157 };
0158 
0159 static const struct pci_device_id adma_ata_pci_tbl[] = {
0160     { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
0161 
0162     { } /* terminate list */
0163 };
0164 
0165 static struct pci_driver adma_ata_pci_driver = {
0166     .name           = DRV_NAME,
0167     .id_table       = adma_ata_pci_tbl,
0168     .probe          = adma_ata_init_one,
0169     .remove         = ata_pci_remove_one,
0170 };
0171 
0172 static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
0173 {
0174     return 1;   /* ATAPI DMA not yet supported */
0175 }
0176 
0177 static void adma_reset_engine(struct ata_port *ap)
0178 {
0179     void __iomem *chan = ADMA_PORT_REGS(ap);
0180 
0181     /* reset ADMA to idle state */
0182     writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
0183     udelay(2);
0184     writew(aPIOMD4, chan + ADMA_CONTROL);
0185     udelay(2);
0186 }
0187 
0188 static void adma_reinit_engine(struct ata_port *ap)
0189 {
0190     struct adma_port_priv *pp = ap->private_data;
0191     void __iomem *chan = ADMA_PORT_REGS(ap);
0192 
0193     /* mask/clear ATA interrupts */
0194     writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
0195     ata_sff_check_status(ap);
0196 
0197     /* reset the ADMA engine */
0198     adma_reset_engine(ap);
0199 
0200     /* set in-FIFO threshold to 0x100 */
0201     writew(0x100, chan + ADMA_FIFO_IN);
0202 
0203     /* set CPB pointer */
0204     writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
0205 
0206     /* set out-FIFO threshold to 0x100 */
0207     writew(0x100, chan + ADMA_FIFO_OUT);
0208 
0209     /* set CPB count */
0210     writew(1, chan + ADMA_CPB_COUNT);
0211 
0212     /* read/discard ADMA status */
0213     readb(chan + ADMA_STATUS);
0214 }
0215 
0216 static inline void adma_enter_reg_mode(struct ata_port *ap)
0217 {
0218     void __iomem *chan = ADMA_PORT_REGS(ap);
0219 
0220     writew(aPIOMD4, chan + ADMA_CONTROL);
0221     readb(chan + ADMA_STATUS);  /* flush */
0222 }
0223 
0224 static void adma_freeze(struct ata_port *ap)
0225 {
0226     void __iomem *chan = ADMA_PORT_REGS(ap);
0227 
0228     /* mask/clear ATA interrupts */
0229     writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
0230     ata_sff_check_status(ap);
0231 
0232     /* reset ADMA to idle state */
0233     writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
0234     udelay(2);
0235     writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
0236     udelay(2);
0237 }
0238 
0239 static void adma_thaw(struct ata_port *ap)
0240 {
0241     adma_reinit_engine(ap);
0242 }
0243 
0244 static int adma_prereset(struct ata_link *link, unsigned long deadline)
0245 {
0246     struct ata_port *ap = link->ap;
0247     struct adma_port_priv *pp = ap->private_data;
0248 
0249     if (pp->state != adma_state_idle) /* healthy paranoia */
0250         pp->state = adma_state_mmio;
0251     adma_reinit_engine(ap);
0252 
0253     return ata_sff_prereset(link, deadline);
0254 }
0255 
0256 static int adma_fill_sg(struct ata_queued_cmd *qc)
0257 {
0258     struct scatterlist *sg;
0259     struct ata_port *ap = qc->ap;
0260     struct adma_port_priv *pp = ap->private_data;
0261     u8  *buf = pp->pkt, *last_buf = NULL;
0262     int i = (2 + buf[3]) * 8;
0263     u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
0264     unsigned int si;
0265 
0266     for_each_sg(qc->sg, sg, qc->n_elem, si) {
0267         u32 addr;
0268         u32 len;
0269 
0270         addr = (u32)sg_dma_address(sg);
0271         *(__le32 *)(buf + i) = cpu_to_le32(addr);
0272         i += 4;
0273 
0274         len = sg_dma_len(sg) >> 3;
0275         *(__le32 *)(buf + i) = cpu_to_le32(len);
0276         i += 4;
0277 
0278         last_buf = &buf[i];
0279         buf[i++] = pFLAGS;
0280         buf[i++] = qc->dev->dma_mode & 0xf;
0281         buf[i++] = 0;   /* pPKLW */
0282         buf[i++] = 0;   /* reserved */
0283 
0284         *(__le32 *)(buf + i) =
0285             (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
0286         i += 4;
0287     }
0288 
0289     if (likely(last_buf))
0290         *last_buf |= pEND;
0291 
0292     return i;
0293 }
0294 
0295 static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc)
0296 {
0297     struct adma_port_priv *pp = qc->ap->private_data;
0298     u8  *buf = pp->pkt;
0299     u32 pkt_dma = (u32)pp->pkt_dma;
0300     int i = 0;
0301 
0302     adma_enter_reg_mode(qc->ap);
0303     if (qc->tf.protocol != ATA_PROT_DMA)
0304         return AC_ERR_OK;
0305 
0306     buf[i++] = 0;   /* Response flags */
0307     buf[i++] = 0;   /* reserved */
0308     buf[i++] = cVLD | cDAT | cIEN;
0309     i++;        /* cLEN, gets filled in below */
0310 
0311     *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma);  /* cNCPB */
0312     i += 4;     /* cNCPB */
0313     i += 4;     /* cPRD, gets filled in below */
0314 
0315     buf[i++] = 0;   /* reserved */
0316     buf[i++] = 0;   /* reserved */
0317     buf[i++] = 0;   /* reserved */
0318     buf[i++] = 0;   /* reserved */
0319 
0320     /* ATA registers; must be a multiple of 4 */
0321     buf[i++] = qc->tf.device;
0322     buf[i++] = ADMA_REGS_DEVICE;
0323     if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
0324         buf[i++] = qc->tf.hob_nsect;
0325         buf[i++] = ADMA_REGS_SECTOR_COUNT;
0326         buf[i++] = qc->tf.hob_lbal;
0327         buf[i++] = ADMA_REGS_LBA_LOW;
0328         buf[i++] = qc->tf.hob_lbam;
0329         buf[i++] = ADMA_REGS_LBA_MID;
0330         buf[i++] = qc->tf.hob_lbah;
0331         buf[i++] = ADMA_REGS_LBA_HIGH;
0332     }
0333     buf[i++] = qc->tf.nsect;
0334     buf[i++] = ADMA_REGS_SECTOR_COUNT;
0335     buf[i++] = qc->tf.lbal;
0336     buf[i++] = ADMA_REGS_LBA_LOW;
0337     buf[i++] = qc->tf.lbam;
0338     buf[i++] = ADMA_REGS_LBA_MID;
0339     buf[i++] = qc->tf.lbah;
0340     buf[i++] = ADMA_REGS_LBA_HIGH;
0341     buf[i++] = 0;
0342     buf[i++] = ADMA_REGS_CONTROL;
0343     buf[i++] = rIGN;
0344     buf[i++] = 0;
0345     buf[i++] = qc->tf.command;
0346     buf[i++] = ADMA_REGS_COMMAND | rEND;
0347 
0348     buf[3] = (i >> 3) - 2;              /* cLEN */
0349     *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i);  /* cPRD */
0350 
0351     i = adma_fill_sg(qc);
0352     wmb();  /* flush PRDs and pkt to memory */
0353     return AC_ERR_OK;
0354 }
0355 
0356 static inline void adma_packet_start(struct ata_queued_cmd *qc)
0357 {
0358     struct ata_port *ap = qc->ap;
0359     void __iomem *chan = ADMA_PORT_REGS(ap);
0360 
0361     /* fire up the ADMA engine */
0362     writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
0363 }
0364 
0365 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
0366 {
0367     struct adma_port_priv *pp = qc->ap->private_data;
0368 
0369     switch (qc->tf.protocol) {
0370     case ATA_PROT_DMA:
0371         pp->state = adma_state_pkt;
0372         adma_packet_start(qc);
0373         return 0;
0374 
0375     case ATAPI_PROT_DMA:
0376         BUG();
0377         break;
0378 
0379     default:
0380         break;
0381     }
0382 
0383     pp->state = adma_state_mmio;
0384     return ata_sff_qc_issue(qc);
0385 }
0386 
0387 static inline unsigned int adma_intr_pkt(struct ata_host *host)
0388 {
0389     unsigned int handled = 0, port_no;
0390 
0391     for (port_no = 0; port_no < host->n_ports; ++port_no) {
0392         struct ata_port *ap = host->ports[port_no];
0393         struct adma_port_priv *pp;
0394         struct ata_queued_cmd *qc;
0395         void __iomem *chan = ADMA_PORT_REGS(ap);
0396         u8 status = readb(chan + ADMA_STATUS);
0397 
0398         if (status == 0)
0399             continue;
0400         handled = 1;
0401         adma_enter_reg_mode(ap);
0402         pp = ap->private_data;
0403         if (!pp || pp->state != adma_state_pkt)
0404             continue;
0405         qc = ata_qc_from_tag(ap, ap->link.active_tag);
0406         if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
0407             if (status & aPERR)
0408                 qc->err_mask |= AC_ERR_HOST_BUS;
0409             else if ((status & (aPSD | aUIRQ)))
0410                 qc->err_mask |= AC_ERR_OTHER;
0411 
0412             if (pp->pkt[0] & cATERR)
0413                 qc->err_mask |= AC_ERR_DEV;
0414             else if (pp->pkt[0] != cDONE)
0415                 qc->err_mask |= AC_ERR_OTHER;
0416 
0417             if (!qc->err_mask)
0418                 ata_qc_complete(qc);
0419             else {
0420                 struct ata_eh_info *ehi = &ap->link.eh_info;
0421                 ata_ehi_clear_desc(ehi);
0422                 ata_ehi_push_desc(ehi,
0423                     "ADMA-status 0x%02X", status);
0424                 ata_ehi_push_desc(ehi,
0425                     "pkt[0] 0x%02X", pp->pkt[0]);
0426 
0427                 if (qc->err_mask == AC_ERR_DEV)
0428                     ata_port_abort(ap);
0429                 else
0430                     ata_port_freeze(ap);
0431             }
0432         }
0433     }
0434     return handled;
0435 }
0436 
0437 static inline unsigned int adma_intr_mmio(struct ata_host *host)
0438 {
0439     unsigned int handled = 0, port_no;
0440 
0441     for (port_no = 0; port_no < host->n_ports; ++port_no) {
0442         struct ata_port *ap = host->ports[port_no];
0443         struct adma_port_priv *pp = ap->private_data;
0444         struct ata_queued_cmd *qc;
0445 
0446         if (!pp || pp->state != adma_state_mmio)
0447             continue;
0448         qc = ata_qc_from_tag(ap, ap->link.active_tag);
0449         if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
0450 
0451             /* check main status, clearing INTRQ */
0452             u8 status = ata_sff_check_status(ap);
0453             if ((status & ATA_BUSY))
0454                 continue;
0455 
0456             /* complete taskfile transaction */
0457             pp->state = adma_state_idle;
0458             qc->err_mask |= ac_err_mask(status);
0459             if (!qc->err_mask)
0460                 ata_qc_complete(qc);
0461             else {
0462                 struct ata_eh_info *ehi = &ap->link.eh_info;
0463                 ata_ehi_clear_desc(ehi);
0464                 ata_ehi_push_desc(ehi, "status 0x%02X", status);
0465 
0466                 if (qc->err_mask == AC_ERR_DEV)
0467                     ata_port_abort(ap);
0468                 else
0469                     ata_port_freeze(ap);
0470             }
0471             handled = 1;
0472         }
0473     }
0474     return handled;
0475 }
0476 
0477 static irqreturn_t adma_intr(int irq, void *dev_instance)
0478 {
0479     struct ata_host *host = dev_instance;
0480     unsigned int handled = 0;
0481 
0482     spin_lock(&host->lock);
0483     handled  = adma_intr_pkt(host) | adma_intr_mmio(host);
0484     spin_unlock(&host->lock);
0485 
0486     return IRQ_RETVAL(handled);
0487 }
0488 
0489 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
0490 {
0491     port->cmd_addr      =
0492     port->data_addr     = base + 0x000;
0493     port->error_addr    =
0494     port->feature_addr  = base + 0x004;
0495     port->nsect_addr    = base + 0x008;
0496     port->lbal_addr     = base + 0x00c;
0497     port->lbam_addr     = base + 0x010;
0498     port->lbah_addr     = base + 0x014;
0499     port->device_addr   = base + 0x018;
0500     port->status_addr   =
0501     port->command_addr  = base + 0x01c;
0502     port->altstatus_addr    =
0503     port->ctl_addr      = base + 0x038;
0504 }
0505 
0506 static int adma_port_start(struct ata_port *ap)
0507 {
0508     struct device *dev = ap->host->dev;
0509     struct adma_port_priv *pp;
0510 
0511     adma_enter_reg_mode(ap);
0512     pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
0513     if (!pp)
0514         return -ENOMEM;
0515     pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
0516                       GFP_KERNEL);
0517     if (!pp->pkt)
0518         return -ENOMEM;
0519     /* paranoia? */
0520     if ((pp->pkt_dma & 7) != 0) {
0521         ata_port_err(ap, "bad alignment for pp->pkt_dma: %08x\n",
0522                  (u32)pp->pkt_dma);
0523         return -ENOMEM;
0524     }
0525     ap->private_data = pp;
0526     adma_reinit_engine(ap);
0527     return 0;
0528 }
0529 
0530 static void adma_port_stop(struct ata_port *ap)
0531 {
0532     adma_reset_engine(ap);
0533 }
0534 
0535 static void adma_host_init(struct ata_host *host, unsigned int chip_id)
0536 {
0537     unsigned int port_no;
0538 
0539     /* enable/lock aGO operation */
0540     writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
0541 
0542     /* reset the ADMA logic */
0543     for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
0544         adma_reset_engine(host->ports[port_no]);
0545 }
0546 
0547 static int adma_ata_init_one(struct pci_dev *pdev,
0548                  const struct pci_device_id *ent)
0549 {
0550     unsigned int board_idx = (unsigned int) ent->driver_data;
0551     const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
0552     struct ata_host *host;
0553     void __iomem *mmio_base;
0554     int rc, port_no;
0555 
0556     ata_print_version_once(&pdev->dev, DRV_VERSION);
0557 
0558     /* alloc host */
0559     host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
0560     if (!host)
0561         return -ENOMEM;
0562 
0563     /* acquire resources and fill host */
0564     rc = pcim_enable_device(pdev);
0565     if (rc)
0566         return rc;
0567 
0568     if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
0569         return -ENODEV;
0570 
0571     rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
0572     if (rc)
0573         return rc;
0574     host->iomap = pcim_iomap_table(pdev);
0575     mmio_base = host->iomap[ADMA_MMIO_BAR];
0576 
0577     rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
0578     if (rc) {
0579         dev_err(&pdev->dev, "32-bit DMA enable failed\n");
0580         return rc;
0581     }
0582 
0583     for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
0584         struct ata_port *ap = host->ports[port_no];
0585         void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
0586         unsigned int offset = port_base - mmio_base;
0587 
0588         adma_ata_setup_port(&ap->ioaddr, port_base);
0589 
0590         ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
0591         ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
0592     }
0593 
0594     /* initialize adapter */
0595     adma_host_init(host, board_idx);
0596 
0597     pci_set_master(pdev);
0598     return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
0599                  &adma_ata_sht);
0600 }
0601 
0602 module_pci_driver(adma_ata_pci_driver);
0603 
0604 MODULE_AUTHOR("Mark Lord");
0605 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
0606 MODULE_LICENSE("GPL");
0607 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
0608 MODULE_VERSION(DRV_VERSION);
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