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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * pata_via.c   - VIA PATA for new ATA layer
0004  *            (C) 2005-2006 Red Hat Inc
0005  *
0006  *  Documentation
0007  *  Most chipset documentation available under NDA only
0008  *
0009  *  VIA version guide
0010  *  VIA VT82C561    -   early design, uses ata_generic currently
0011  *  VIA VT82C576    -   MWDMA, 33Mhz
0012  *  VIA VT82C586    -   MWDMA, 33Mhz
0013  *  VIA VT82C586a   -   Added UDMA to 33Mhz
0014  *  VIA VT82C586b   -   UDMA33
0015  *  VIA VT82C596a   -   Nonfunctional UDMA66
0016  *  VIA VT82C596b   -   Working UDMA66
0017  *  VIA VT82C686    -   Nonfunctional UDMA66
0018  *  VIA VT82C686a   -   Working UDMA66
0019  *  VIA VT82C686b   -   Updated to UDMA100
0020  *  VIA VT8231  -   UDMA100
0021  *  VIA VT8233  -   UDMA100
0022  *  VIA VT8233a -   UDMA133
0023  *  VIA VT8233c -   UDMA100
0024  *  VIA VT8235  -   UDMA133
0025  *  VIA VT8237  -   UDMA133
0026  *  VIA VT8237A -   UDMA133
0027  *  VIA VT8237S -   UDMA133
0028  *  VIA VT8251  -   UDMA133
0029  *
0030  *  Most registers remain compatible across chips. Others start reserved
0031  *  and acquire sensible semantics if set to 1 (eg cable detect). A few
0032  *  exceptions exist, notably around the FIFO settings.
0033  *
0034  *  One additional quirk of the VIA design is that like ALi they use few
0035  *  PCI IDs for a lot of chips.
0036  *
0037  *  Based heavily on:
0038  *
0039  * Version 3.38
0040  *
0041  * VIA IDE driver for Linux. Supported southbridges:
0042  *
0043  *   vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
0044  *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
0045  *   vt8235, vt8237
0046  *
0047  * Copyright (c) 2000-2002 Vojtech Pavlik
0048  *
0049  * Based on the work of:
0050  *  Michel Aubry
0051  *  Jeff Garzik
0052  *  Andre Hedrick
0053 
0054  */
0055 
0056 #include <linux/kernel.h>
0057 #include <linux/module.h>
0058 #include <linux/pci.h>
0059 #include <linux/blkdev.h>
0060 #include <linux/delay.h>
0061 #include <linux/gfp.h>
0062 #include <scsi/scsi_host.h>
0063 #include <linux/libata.h>
0064 #include <linux/dmi.h>
0065 
0066 #define DRV_NAME "pata_via"
0067 #define DRV_VERSION "0.3.4"
0068 
0069 enum {
0070     VIA_BAD_PREQ    = 0x01, /* Crashes if PREQ# till DDACK# set */
0071     VIA_BAD_CLK66   = 0x02, /* 66 MHz clock doesn't work correctly */
0072     VIA_SET_FIFO    = 0x04, /* Needs to have FIFO split set */
0073     VIA_NO_UNMASK   = 0x08, /* Doesn't work with IRQ unmasking on */
0074     VIA_BAD_ID  = 0x10, /* Has wrong vendor ID (0x1107) */
0075     VIA_BAD_AST = 0x20, /* Don't touch Address Setup Timing */
0076     VIA_NO_ENABLES  = 0x40, /* Has no enablebits */
0077     VIA_SATA_PATA   = 0x80, /* SATA/PATA combined configuration */
0078 };
0079 
0080 enum {
0081     VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */
0082 };
0083 
0084 /*
0085  * VIA SouthBridge chips.
0086  */
0087 
0088 static const struct via_isa_bridge {
0089     const char *name;
0090     u16 id;
0091     u8 rev_min;
0092     u8 rev_max;
0093     u8 udma_mask;
0094     u8 flags;
0095 } via_isa_bridges[] = {
0096     { "vx855",  PCI_DEVICE_ID_VIA_VX855,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
0097     { "vx800",  PCI_DEVICE_ID_VIA_VX800,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
0098     { "vt8261", PCI_DEVICE_ID_VIA_8261,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
0099     { "vt8237s",    PCI_DEVICE_ID_VIA_8237S,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
0100     { "vt8251", PCI_DEVICE_ID_VIA_8251,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
0101     { "cx700",  PCI_DEVICE_ID_VIA_CX700,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
0102     { "vt6410", PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },
0103     { "vt6415", PCI_DEVICE_ID_VIA_6415,     0x00, 0xff, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },
0104     { "vt8237a",    PCI_DEVICE_ID_VIA_8237A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
0105     { "vt8237", PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
0106     { "vt8235", PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
0107     { "vt8233a",    PCI_DEVICE_ID_VIA_8233A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
0108     { "vt8233c",    PCI_DEVICE_ID_VIA_8233C_0,  0x00, 0x2f, ATA_UDMA5, },
0109     { "vt8233", PCI_DEVICE_ID_VIA_8233_0,   0x00, 0x2f, ATA_UDMA5, },
0110     { "vt8231", PCI_DEVICE_ID_VIA_8231,     0x00, 0x2f, ATA_UDMA5, },
0111     { "vt82c686b",  PCI_DEVICE_ID_VIA_82C686,   0x40, 0x4f, ATA_UDMA5, },
0112     { "vt82c686a",  PCI_DEVICE_ID_VIA_82C686,   0x10, 0x2f, ATA_UDMA4, },
0113     { "vt82c686",   PCI_DEVICE_ID_VIA_82C686,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
0114     { "vt82c596b",  PCI_DEVICE_ID_VIA_82C596,   0x10, 0x2f, ATA_UDMA4, },
0115     { "vt82c596a",  PCI_DEVICE_ID_VIA_82C596,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
0116     { "vt82c586b",  PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
0117     { "vt82c586b",  PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
0118     { "vt82c586b",  PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
0119     { "vt82c586a",  PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
0120     { "vt82c586",   PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f,      0x00, VIA_SET_FIFO },
0121     { "vt82c576",   PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
0122     { "vt82c576",   PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
0123     { "vtxxxx", PCI_DEVICE_ID_VIA_ANON,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
0124     { NULL }
0125 };
0126 
0127 static const struct dmi_system_id no_atapi_dma_dmi_table[] = {
0128     {
0129         .ident = "AVERATEC 3200",
0130         .matches = {
0131             DMI_MATCH(DMI_BOARD_VENDOR, "AVERATEC"),
0132             DMI_MATCH(DMI_BOARD_NAME, "3200"),
0133         },
0134     },
0135     { }
0136 };
0137 
0138 struct via_port {
0139     u8 cached_device;
0140 };
0141 
0142 /*
0143  *  Cable special cases
0144  */
0145 
0146 static const struct dmi_system_id cable_dmi_table[] = {
0147     {
0148         .ident = "Acer Ferrari 3400",
0149         .matches = {
0150             DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
0151             DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
0152         },
0153     },
0154     { }
0155 };
0156 
0157 static int via_cable_override(struct pci_dev *pdev)
0158 {
0159     /* Systems by DMI */
0160     if (dmi_check_system(cable_dmi_table))
0161         return 1;
0162     /* Arima W730-K8/Targa Visionary 811/... */
0163     if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032)
0164         return 1;
0165     return 0;
0166 }
0167 
0168 
0169 /**
0170  *  via_cable_detect    -   cable detection
0171  *  @ap: ATA port
0172  *
0173  *  Perform cable detection. Actually for the VIA case the BIOS
0174  *  already did this for us. We read the values provided by the
0175  *  BIOS. If you are using an 8235 in a non-PC configuration you
0176  *  may need to update this code.
0177  *
0178  *  Hotplug also impacts on this.
0179  */
0180 
0181 static int via_cable_detect(struct ata_port *ap) {
0182     const struct via_isa_bridge *config = ap->host->private_data;
0183     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0184     u32 ata66;
0185 
0186     if (via_cable_override(pdev))
0187         return ATA_CBL_PATA40_SHORT;
0188 
0189     if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0)
0190         return ATA_CBL_SATA;
0191 
0192     /* Early chips are 40 wire */
0193     if (config->udma_mask < ATA_UDMA4)
0194         return ATA_CBL_PATA40;
0195     /* UDMA 66 chips have only drive side logic */
0196     else if (config->udma_mask < ATA_UDMA5)
0197         return ATA_CBL_PATA_UNK;
0198     /* UDMA 100 or later */
0199     pci_read_config_dword(pdev, 0x50, &ata66);
0200     /* Check both the drive cable reporting bits, we might not have
0201        two drives */
0202     if (ata66 & (0x10100000 >> (16 * ap->port_no)))
0203         return ATA_CBL_PATA80;
0204     /* Check with ACPI so we can spot BIOS reported SATA bridges */
0205     if (ata_acpi_init_gtm(ap) &&
0206         ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap)))
0207         return ATA_CBL_PATA80;
0208     return ATA_CBL_PATA40;
0209 }
0210 
0211 static int via_pre_reset(struct ata_link *link, unsigned long deadline)
0212 {
0213     struct ata_port *ap = link->ap;
0214     const struct via_isa_bridge *config = ap->host->private_data;
0215 
0216     if (!(config->flags & VIA_NO_ENABLES)) {
0217         static const struct pci_bits via_enable_bits[] = {
0218             { 0x40, 1, 0x02, 0x02 },
0219             { 0x40, 1, 0x01, 0x01 }
0220         };
0221         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0222         if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
0223             return -ENOENT;
0224     }
0225 
0226     return ata_sff_prereset(link, deadline);
0227 }
0228 
0229 
0230 /**
0231  *  via_do_set_mode -   set transfer mode data
0232  *  @ap: ATA interface
0233  *  @adev: ATA device
0234  *  @mode: ATA mode being programmed
0235  *  @set_ast: Set to program address setup
0236  *  @udma_type: UDMA mode/format of registers
0237  *
0238  *  Program the VIA registers for DMA and PIO modes. Uses the ata timing
0239  *  support in order to compute modes.
0240  *
0241  *  FIXME: Hotplug will require we serialize multiple mode changes
0242  *  on the two channels.
0243  */
0244 
0245 static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev,
0246                 int mode, int set_ast, int udma_type)
0247 {
0248     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0249     struct ata_device *peer = ata_dev_pair(adev);
0250     struct ata_timing t, p;
0251     const int via_clock = 33333;    /* Bus clock in kHz */
0252     const int T = 1000000000 / via_clock;
0253     int UT = T;
0254     int ut;
0255     int offset = 3 - (2*ap->port_no) - adev->devno;
0256 
0257     switch (udma_type) {
0258     case ATA_UDMA4:
0259         UT = T / 2; break;
0260     case ATA_UDMA5:
0261         UT = T / 3; break;
0262     case ATA_UDMA6:
0263         UT = T / 4; break;
0264     }
0265 
0266     /* Calculate the timing values we require */
0267     ata_timing_compute(adev, mode, &t, T, UT);
0268 
0269     /* We share 8bit timing so we must merge the constraints */
0270     if (peer) {
0271         if (peer->pio_mode) {
0272             ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
0273             ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
0274         }
0275     }
0276 
0277     /* Address setup is programmable but breaks on UDMA133 setups */
0278     if (set_ast) {
0279         u8 setup;   /* 2 bits per drive */
0280         int shift = 2 * offset;
0281 
0282         pci_read_config_byte(pdev, 0x4C, &setup);
0283         setup &= ~(3 << shift);
0284         setup |= (clamp_val(t.setup, 1, 4) - 1) << shift;
0285         pci_write_config_byte(pdev, 0x4C, setup);
0286     }
0287 
0288     /* Load the PIO mode bits */
0289     pci_write_config_byte(pdev, 0x4F - ap->port_no,
0290         ((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1));
0291     pci_write_config_byte(pdev, 0x48 + offset,
0292         ((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1));
0293 
0294     /* Load the UDMA bits according to type */
0295     switch (udma_type) {
0296     case ATA_UDMA2:
0297     default:
0298         ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03;
0299         break;
0300     case ATA_UDMA4:
0301         ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f;
0302         break;
0303     case ATA_UDMA5:
0304         ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
0305         break;
0306     case ATA_UDMA6:
0307         ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
0308         break;
0309     }
0310 
0311     /* Set UDMA unless device is not UDMA capable */
0312     if (udma_type) {
0313         u8 udma_etc;
0314 
0315         pci_read_config_byte(pdev, 0x50 + offset, &udma_etc);
0316 
0317         /* clear transfer mode bit */
0318         udma_etc &= ~0x20;
0319 
0320         if (t.udma) {
0321             /* preserve 80-wire cable detection bit */
0322             udma_etc &= 0x10;
0323             udma_etc |= ut;
0324         }
0325 
0326         pci_write_config_byte(pdev, 0x50 + offset, udma_etc);
0327     }
0328 }
0329 
0330 static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
0331 {
0332     const struct via_isa_bridge *config = ap->host->private_data;
0333     int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
0334 
0335     via_do_set_mode(ap, adev, adev->pio_mode, set_ast, config->udma_mask);
0336 }
0337 
0338 static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0339 {
0340     const struct via_isa_bridge *config = ap->host->private_data;
0341     int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
0342 
0343     via_do_set_mode(ap, adev, adev->dma_mode, set_ast, config->udma_mask);
0344 }
0345 
0346 /**
0347  *  via_mode_filter     -   filter buggy device/mode pairs
0348  *  @dev: ATA device
0349  *  @mask: Mode bitmask
0350  *
0351  *  We need to apply some minimal filtering for old controllers and at least
0352  *  one breed of Transcend SSD. Return the updated mask.
0353  */
0354 
0355 static unsigned int via_mode_filter(struct ata_device *dev, unsigned int mask)
0356 {
0357     struct ata_host *host = dev->link->ap->host;
0358     const struct via_isa_bridge *config = host->private_data;
0359     unsigned char model_num[ATA_ID_PROD_LEN + 1];
0360 
0361     if (config->id == PCI_DEVICE_ID_VIA_82C586_0) {
0362         ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
0363         if (strcmp(model_num, "TS64GSSD25-M") == 0) {
0364             ata_dev_warn(dev,
0365     "disabling UDMA mode due to reported lockups with this device\n");
0366             mask &= ~ ATA_MASK_UDMA;
0367         }
0368     }
0369 
0370     if (dev->class == ATA_DEV_ATAPI &&
0371         dmi_check_system(no_atapi_dma_dmi_table)) {
0372         ata_dev_warn(dev, "controller locks up on ATAPI DMA, forcing PIO\n");
0373         mask &= ATA_MASK_PIO;
0374     }
0375 
0376     return mask;
0377 }
0378 
0379 /**
0380  *  via_tf_load - send taskfile registers to host controller
0381  *  @ap: Port to which output is sent
0382  *  @tf: ATA taskfile register set
0383  *
0384  *  Outputs ATA taskfile to standard ATA host controller.
0385  *
0386  *  Note: This is to fix the internal bug of via chipsets, which
0387  *  will reset the device register after changing the IEN bit on
0388  *  ctl register
0389  */
0390 static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
0391 {
0392     struct ata_ioports *ioaddr = &ap->ioaddr;
0393     struct via_port *vp = ap->private_data;
0394     unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
0395     int newctl = 0;
0396 
0397     if (tf->ctl != ap->last_ctl) {
0398         iowrite8(tf->ctl, ioaddr->ctl_addr);
0399         ap->last_ctl = tf->ctl;
0400         ata_wait_idle(ap);
0401         newctl = 1;
0402     }
0403 
0404     if (tf->flags & ATA_TFLAG_DEVICE) {
0405         iowrite8(tf->device, ioaddr->device_addr);
0406         vp->cached_device = tf->device;
0407     } else if (newctl)
0408         iowrite8(vp->cached_device, ioaddr->device_addr);
0409 
0410     if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
0411         WARN_ON_ONCE(!ioaddr->ctl_addr);
0412         iowrite8(tf->hob_feature, ioaddr->feature_addr);
0413         iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
0414         iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
0415         iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
0416         iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
0417     }
0418 
0419     if (is_addr) {
0420         iowrite8(tf->feature, ioaddr->feature_addr);
0421         iowrite8(tf->nsect, ioaddr->nsect_addr);
0422         iowrite8(tf->lbal, ioaddr->lbal_addr);
0423         iowrite8(tf->lbam, ioaddr->lbam_addr);
0424         iowrite8(tf->lbah, ioaddr->lbah_addr);
0425     }
0426 
0427     ata_wait_idle(ap);
0428 }
0429 
0430 static int via_port_start(struct ata_port *ap)
0431 {
0432     struct via_port *vp;
0433     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0434 
0435     int ret = ata_bmdma_port_start(ap);
0436     if (ret < 0)
0437         return ret;
0438 
0439     vp = devm_kzalloc(&pdev->dev, sizeof(struct via_port), GFP_KERNEL);
0440     if (vp == NULL)
0441         return -ENOMEM;
0442     ap->private_data = vp;
0443     return 0;
0444 }
0445 
0446 static struct scsi_host_template via_sht = {
0447     ATA_BMDMA_SHT(DRV_NAME),
0448 };
0449 
0450 static struct ata_port_operations via_port_ops = {
0451     .inherits   = &ata_bmdma_port_ops,
0452     .cable_detect   = via_cable_detect,
0453     .set_piomode    = via_set_piomode,
0454     .set_dmamode    = via_set_dmamode,
0455     .prereset   = via_pre_reset,
0456     .sff_tf_load    = via_tf_load,
0457     .port_start = via_port_start,
0458     .mode_filter    = via_mode_filter,
0459 };
0460 
0461 static struct ata_port_operations via_port_ops_noirq = {
0462     .inherits   = &via_port_ops,
0463     .sff_data_xfer  = ata_sff_data_xfer32,
0464 };
0465 
0466 /**
0467  *  via_config_fifo     -   set up the FIFO
0468  *  @pdev: PCI device
0469  *  @flags: configuration flags
0470  *
0471  *  Set the FIFO properties for this device if necessary. Used both on
0472  *  set up and on and the resume path
0473  */
0474 
0475 static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
0476 {
0477     u8 enable;
0478 
0479     /* 0x40 low bits indicate enabled channels */
0480     pci_read_config_byte(pdev, 0x40 , &enable);
0481     enable &= 3;
0482 
0483     if (flags & VIA_SET_FIFO) {
0484         static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
0485         u8 fifo;
0486 
0487         pci_read_config_byte(pdev, 0x43, &fifo);
0488 
0489         /* Clear PREQ# until DDACK# for errata */
0490         if (flags & VIA_BAD_PREQ)
0491             fifo &= 0x7F;
0492         else
0493             fifo &= 0x9f;
0494         /* Turn on FIFO for enabled channels */
0495         fifo |= fifo_setting[enable];
0496         pci_write_config_byte(pdev, 0x43, fifo);
0497     }
0498 }
0499 
0500 static void via_fixup(struct pci_dev *pdev, const struct via_isa_bridge *config)
0501 {
0502     u32 timing;
0503 
0504     /* Initialise the FIFO for the enabled channels. */
0505     via_config_fifo(pdev, config->flags);
0506 
0507     if (config->udma_mask == ATA_UDMA4) {
0508         /* The 66 MHz devices require we enable the clock */
0509         pci_read_config_dword(pdev, 0x50, &timing);
0510         timing |= 0x80008;
0511         pci_write_config_dword(pdev, 0x50, timing);
0512     }
0513     if (config->flags & VIA_BAD_CLK66) {
0514         /* Disable the 66MHz clock on problem devices */
0515         pci_read_config_dword(pdev, 0x50, &timing);
0516         timing &= ~0x80008;
0517         pci_write_config_dword(pdev, 0x50, timing);
0518     }
0519 }
0520 
0521 /**
0522  *  via_init_one        -   discovery callback
0523  *  @pdev: PCI device
0524  *  @id: PCI table info
0525  *
0526  *  A VIA IDE interface has been discovered. Figure out what revision
0527  *  and perform configuration work before handing it to the ATA layer
0528  */
0529 
0530 static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
0531 {
0532     /* Early VIA without UDMA support */
0533     static const struct ata_port_info via_mwdma_info = {
0534         .flags = ATA_FLAG_SLAVE_POSS,
0535         .pio_mask = ATA_PIO4,
0536         .mwdma_mask = ATA_MWDMA2,
0537         .port_ops = &via_port_ops
0538     };
0539     /* Ditto with IRQ masking required */
0540     static const struct ata_port_info via_mwdma_info_borked = {
0541         .flags = ATA_FLAG_SLAVE_POSS,
0542         .pio_mask = ATA_PIO4,
0543         .mwdma_mask = ATA_MWDMA2,
0544         .port_ops = &via_port_ops_noirq,
0545     };
0546     /* VIA UDMA 33 devices (and borked 66) */
0547     static const struct ata_port_info via_udma33_info = {
0548         .flags = ATA_FLAG_SLAVE_POSS,
0549         .pio_mask = ATA_PIO4,
0550         .mwdma_mask = ATA_MWDMA2,
0551         .udma_mask = ATA_UDMA2,
0552         .port_ops = &via_port_ops
0553     };
0554     /* VIA UDMA 66 devices */
0555     static const struct ata_port_info via_udma66_info = {
0556         .flags = ATA_FLAG_SLAVE_POSS,
0557         .pio_mask = ATA_PIO4,
0558         .mwdma_mask = ATA_MWDMA2,
0559         .udma_mask = ATA_UDMA4,
0560         .port_ops = &via_port_ops
0561     };
0562     /* VIA UDMA 100 devices */
0563     static const struct ata_port_info via_udma100_info = {
0564         .flags = ATA_FLAG_SLAVE_POSS,
0565         .pio_mask = ATA_PIO4,
0566         .mwdma_mask = ATA_MWDMA2,
0567         .udma_mask = ATA_UDMA5,
0568         .port_ops = &via_port_ops
0569     };
0570     /* UDMA133 with bad AST (All current 133) */
0571     static const struct ata_port_info via_udma133_info = {
0572         .flags = ATA_FLAG_SLAVE_POSS,
0573         .pio_mask = ATA_PIO4,
0574         .mwdma_mask = ATA_MWDMA2,
0575         .udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */
0576         .port_ops = &via_port_ops
0577     };
0578     const struct ata_port_info *ppi[] = { NULL, NULL };
0579     struct pci_dev *isa;
0580     const struct via_isa_bridge *config;
0581     u8 enable;
0582     unsigned long flags = id->driver_data;
0583     int rc;
0584 
0585     ata_print_version_once(&pdev->dev, DRV_VERSION);
0586 
0587     rc = pcim_enable_device(pdev);
0588     if (rc)
0589         return rc;
0590 
0591     if (flags & VIA_IDFLAG_SINGLE)
0592         ppi[1] = &ata_dummy_port_info;
0593 
0594     /* To find out how the IDE will behave and what features we
0595        actually have to look at the bridge not the IDE controller */
0596     for (config = via_isa_bridges; config->id != PCI_DEVICE_ID_VIA_ANON;
0597          config++)
0598         if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
0599             !!(config->flags & VIA_BAD_ID),
0600             config->id, NULL))) {
0601             u8 rev = isa->revision;
0602             pci_dev_put(isa);
0603 
0604             if ((id->device == 0x0415 || id->device == 0x3164) &&
0605                 (config->id != id->device))
0606                 continue;
0607 
0608             if (rev >= config->rev_min && rev <= config->rev_max)
0609                 break;
0610         }
0611 
0612     if (!(config->flags & VIA_NO_ENABLES)) {
0613         /* 0x40 low bits indicate enabled channels */
0614         pci_read_config_byte(pdev, 0x40 , &enable);
0615         enable &= 3;
0616         if (enable == 0)
0617             return -ENODEV;
0618     }
0619 
0620     /* Clock set up */
0621     switch (config->udma_mask) {
0622     case 0x00:
0623         if (config->flags & VIA_NO_UNMASK)
0624             ppi[0] = &via_mwdma_info_borked;
0625         else
0626             ppi[0] = &via_mwdma_info;
0627         break;
0628     case ATA_UDMA2:
0629         ppi[0] = &via_udma33_info;
0630         break;
0631     case ATA_UDMA4:
0632         ppi[0] = &via_udma66_info;
0633         break;
0634     case ATA_UDMA5:
0635         ppi[0] = &via_udma100_info;
0636         break;
0637     case ATA_UDMA6:
0638         ppi[0] = &via_udma133_info;
0639         break;
0640     default:
0641         WARN_ON(1);
0642         return -ENODEV;
0643     }
0644 
0645     via_fixup(pdev, config);
0646 
0647     /* We have established the device type, now fire it up */
0648     return ata_pci_bmdma_init_one(pdev, ppi, &via_sht, (void *)config, 0);
0649 }
0650 
0651 #ifdef CONFIG_PM_SLEEP
0652 /**
0653  *  via_reinit_one      -   reinit after resume
0654  *  @pdev: PCI device
0655  *
0656  *  Called when the VIA PATA device is resumed. We must then
0657  *  reconfigure the fifo and other setup we may have altered. In
0658  *  addition the kernel needs to have the resume methods on PCI
0659  *  quirk supported.
0660  */
0661 
0662 static int via_reinit_one(struct pci_dev *pdev)
0663 {
0664     struct ata_host *host = pci_get_drvdata(pdev);
0665     int rc;
0666 
0667     rc = ata_pci_device_do_resume(pdev);
0668     if (rc)
0669         return rc;
0670 
0671     via_fixup(pdev, host->private_data);
0672 
0673     ata_host_resume(host);
0674     return 0;
0675 }
0676 #endif
0677 
0678 static const struct pci_device_id via[] = {
0679     { PCI_VDEVICE(VIA, 0x0415), },
0680     { PCI_VDEVICE(VIA, 0x0571), },
0681     { PCI_VDEVICE(VIA, 0x0581), },
0682     { PCI_VDEVICE(VIA, 0x1571), },
0683     { PCI_VDEVICE(VIA, 0x3164), },
0684     { PCI_VDEVICE(VIA, 0x5324), },
0685     { PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE },
0686     { PCI_VDEVICE(VIA, 0x9001), VIA_IDFLAG_SINGLE },
0687 
0688     { },
0689 };
0690 
0691 static struct pci_driver via_pci_driver = {
0692     .name       = DRV_NAME,
0693     .id_table   = via,
0694     .probe      = via_init_one,
0695     .remove     = ata_pci_remove_one,
0696 #ifdef CONFIG_PM_SLEEP
0697     .suspend    = ata_pci_device_suspend,
0698     .resume     = via_reinit_one,
0699 #endif
0700 };
0701 
0702 module_pci_driver(via_pci_driver);
0703 
0704 MODULE_AUTHOR("Alan Cox");
0705 MODULE_DESCRIPTION("low-level driver for VIA PATA");
0706 MODULE_LICENSE("GPL");
0707 MODULE_DEVICE_TABLE(pci, via);
0708 MODULE_VERSION(DRV_VERSION);
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