drivers/ata/pata_sl82c105.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * pata_sl82c105.c  - SL82C105 PATA for new ATA layer
0004  *            (C) 2005 Red Hat Inc
0005  *            (C) 2011 Bartlomiej Zolnierkiewicz
0006  *
0007  * Based in part on linux/drivers/ide/pci/sl82c105.c
0008  *      SL82C105/Winbond 553 IDE driver
0009  *
0010  * and in part on the documentation and errata sheet
0011  *
0012  *
0013  * Note: The controller like many controllers has shared timings for
0014  * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
0015  * in the dma_stop function. Thus we actually don't need a set_dmamode
0016  * method as the PIO method is always called and will set the right PIO
0017  * timing parameters.
0018  */
0019
0020 #include <linux/kernel.h>
0021 #include <linux/module.h>
0022 #include <linux/pci.h>
0023 #include <linux/blkdev.h>
0024 #include <linux/delay.h>
0025 #include <scsi/scsi_host.h>
0026 #include <linux/libata.h>
0027
0028 #define DRV_NAME "pata_sl82c105"
0029 #define DRV_VERSION "0.3.3"
0030
0031 enum {
0032     /*
0033      * SL82C105 PCI config register 0x40 bits.
0034      */
0035     CTRL_IDE_IRQB   =   (1 << 30),
0036     CTRL_IDE_IRQA   =   (1 << 28),
0037     CTRL_LEGIRQ     =   (1 << 11),
0038     CTRL_P1F16      =   (1 << 5),
0039     CTRL_P1EN       =   (1 << 4),
0040     CTRL_P0F16      =   (1 << 1),
0041     CTRL_P0EN       =   (1 << 0)
0042 };
0043
0044 /**
0045  *  sl82c105_pre_reset      -   probe begin
0046  *  @link: ATA link
0047  *  @deadline: deadline jiffies for the operation
0048  *
0049  *  Set up cable type and use generic probe init
0050  */
0051
0052 static int sl82c105_pre_reset(struct ata_link *link, unsigned long deadline)
0053 {
0054     static const struct pci_bits sl82c105_enable_bits[] = {
0055         { 0x40, 1, 0x01, 0x01 },
0056         { 0x40, 1, 0x10, 0x10 }
0057     };
0058     struct ata_port *ap = link->ap;
0059     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0060
0061     if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no]))
0062         return -ENOENT;
0063     return ata_sff_prereset(link, deadline);
0064 }
0065
0066
0067 /**
0068  *  sl82c105_configure_piomode  -   set chip PIO timing
0069  *  @ap: ATA interface
0070  *  @adev: ATA device
0071  *  @pio: PIO mode
0072  *
0073  *  Called to do the PIO mode setup. Our timing registers are shared
0074  *  so a configure_dmamode call will undo any work we do here and vice
0075  *  versa
0076  */
0077
0078 static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
0079 {
0080     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0081     static u16 pio_timing[5] = {
0082         0x50D, 0x407, 0x304, 0x242, 0x240
0083     };
0084     u16 dummy;
0085     int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
0086
0087     pci_write_config_word(pdev, timing, pio_timing[pio]);
0088     /* Can we lose this oddity of the old driver */
0089     pci_read_config_word(pdev, timing, &dummy);
0090 }
0091
0092 /**
0093  *  sl82c105_set_piomode    -   set initial PIO mode data
0094  *  @ap: ATA interface
0095  *  @adev: ATA device
0096  *
0097  *  Called to do the PIO mode setup. Our timing registers are shared
0098  *  but we want to set the PIO timing by default.
0099  */
0100
0101 static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev)
0102 {
0103     sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
0104 }
0105
0106 /**
0107  *  sl82c105_configure_dmamode  -   set DMA mode in chip
0108  *  @ap: ATA interface
0109  *  @adev: ATA device
0110  *
0111  *  Load DMA cycle times into the chip ready for a DMA transfer
0112  *  to occur.
0113  */
0114
0115 static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev)
0116 {
0117     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0118     static u16 dma_timing[3] = {
0119         0x707, 0x201, 0x200
0120     };
0121     u16 dummy;
0122     int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
0123     int dma = adev->dma_mode - XFER_MW_DMA_0;
0124
0125     pci_write_config_word(pdev, timing, dma_timing[dma]);
0126     /* Can we lose this oddity of the old driver */
0127     pci_read_config_word(pdev, timing, &dummy);
0128 }
0129
0130 /**
0131  *  sl82c105_reset_engine   -   Reset the DMA engine
0132  *  @ap: ATA interface
0133  *
0134  *  The sl82c105 has some serious problems with the DMA engine
0135  *  when transfers don't run as expected or ATAPI is used. The
0136  *  recommended fix is to reset the engine each use using a chip
0137  *  test register.
0138  */
0139
0140 static void sl82c105_reset_engine(struct ata_port *ap)
0141 {
0142     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0143     u16 val;
0144
0145     pci_read_config_word(pdev, 0x7E, &val);
0146     pci_write_config_word(pdev, 0x7E, val | 4);
0147     pci_write_config_word(pdev, 0x7E, val & ~4);
0148 }
0149
0150 /**
0151  *  sl82c105_bmdma_start        -   DMA engine begin
0152  *  @qc: ATA command
0153  *
0154  *  Reset the DMA engine each use as recommended by the errata
0155  *  document.
0156  *
0157  *  FIXME: if we switch clock at BMDMA start/end we might get better
0158  *  PIO performance on DMA capable devices.
0159  */
0160
0161 static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
0162 {
0163     struct ata_port *ap = qc->ap;
0164
0165     udelay(100);
0166     sl82c105_reset_engine(ap);
0167     udelay(100);
0168
0169     /* Set the clocks for DMA */
0170     sl82c105_configure_dmamode(ap, qc->dev);
0171     /* Activate DMA */
0172     ata_bmdma_start(qc);
0173 }
0174
0175 /**
0176  *  sl82c105_bmdma_stop     -   DMA engine stop
0177  *  @qc: ATA command
0178  *
0179  *  Reset the DMA engine each use as recommended by the errata
0180  *  document.
0181  *
0182  *  This function is also called to turn off DMA when a timeout occurs
0183  *  during DMA operation. In both cases we need to reset the engine,
0184  *  so no actual eng_timeout handler is required.
0185  *
0186  *  We assume bmdma_stop is always called if bmdma_start as called. If
0187  *  not then we may need to wrap qc_issue.
0188  */
0189
0190 static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
0191 {
0192     struct ata_port *ap = qc->ap;
0193
0194     ata_bmdma_stop(qc);
0195     sl82c105_reset_engine(ap);
0196     udelay(100);
0197
0198     /* This will redo the initial setup of the DMA device to matching
0199        PIO timings */
0200     sl82c105_set_piomode(ap, qc->dev);
0201 }
0202
0203 /**
0204  *  sl82c105_qc_defer   -   implement serialization
0205  *  @qc: command
0206  *
0207  *  We must issue one command per host not per channel because
0208  *  of the reset bug.
0209  *
0210  *  Q: is the scsi host lock sufficient ?
0211  */
0212
0213 static int sl82c105_qc_defer(struct ata_queued_cmd *qc)
0214 {
0215     struct ata_host *host = qc->ap->host;
0216     struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
0217     int rc;
0218
0219     /* First apply the usual rules */
0220     rc = ata_std_qc_defer(qc);
0221     if (rc != 0)
0222         return rc;
0223
0224     /* Now apply serialization rules. Only allow a command if the
0225        other channel state machine is idle */
0226     if (alt && alt->qc_active)
0227         return  ATA_DEFER_PORT;
0228     return 0;
0229 }
0230
0231 static bool sl82c105_sff_irq_check(struct ata_port *ap)
0232 {
0233     struct pci_dev *pdev    = to_pci_dev(ap->host->dev);
0234     u32 val, mask       = ap->port_no ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
0235
0236     pci_read_config_dword(pdev, 0x40, &val);
0237
0238     return val & mask;
0239 }
0240
0241 static struct scsi_host_template sl82c105_sht = {
0242     ATA_BMDMA_SHT(DRV_NAME),
0243 };
0244
0245 static struct ata_port_operations sl82c105_port_ops = {
0246     .inherits   = &ata_bmdma_port_ops,
0247     .qc_defer   = sl82c105_qc_defer,
0248     .bmdma_start    = sl82c105_bmdma_start,
0249     .bmdma_stop = sl82c105_bmdma_stop,
0250     .cable_detect   = ata_cable_40wire,
0251     .set_piomode    = sl82c105_set_piomode,
0252     .prereset   = sl82c105_pre_reset,
0253     .sff_irq_check  = sl82c105_sff_irq_check,
0254 };
0255
0256 /**
0257  *  sl82c105_bridge_revision    -   find bridge version
0258  *  @pdev: PCI device for the ATA function
0259  *
0260  *  Locates the PCI bridge associated with the ATA function and
0261  *  providing it is a Winbond 553 reports the revision. If it cannot
0262  *  find a revision or the right device it returns -1
0263  */
0264
0265 static int sl82c105_bridge_revision(struct pci_dev *pdev)
0266 {
0267     struct pci_dev *bridge;
0268
0269     /*
0270      * The bridge should be part of the same device, but function 0.
0271      */
0272     bridge = pci_get_slot(pdev->bus,
0273                    PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
0274     if (!bridge)
0275         return -1;
0276
0277     /*
0278      * Make sure it is a Winbond 553 and is an ISA bridge.
0279      */
0280     if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
0281         bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
0282         bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
0283             pci_dev_put(bridge);
0284         return -1;
0285     }
0286     /*
0287      * We need to find function 0's revision, not function 1
0288      */
0289     pci_dev_put(bridge);
0290     return bridge->revision;
0291 }
0292
0293 static void sl82c105_fixup(struct pci_dev *pdev)
0294 {
0295     u32 val;
0296
0297     pci_read_config_dword(pdev, 0x40, &val);
0298     val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
0299     pci_write_config_dword(pdev, 0x40, val);
0300 }
0301
0302 static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
0303 {
0304     static const struct ata_port_info info_dma = {
0305         .flags = ATA_FLAG_SLAVE_POSS,
0306         .pio_mask = ATA_PIO4,
0307         .mwdma_mask = ATA_MWDMA2,
0308         .port_ops = &sl82c105_port_ops
0309     };
0310     static const struct ata_port_info info_early = {
0311         .flags = ATA_FLAG_SLAVE_POSS,
0312         .pio_mask = ATA_PIO4,
0313         .port_ops = &sl82c105_port_ops
0314     };
0315     /* for now use only the first port */
0316     const struct ata_port_info *ppi[] = { &info_early,
0317                            NULL };
0318     int rev;
0319     int rc;
0320
0321     rc = pcim_enable_device(dev);
0322     if (rc)
0323         return rc;
0324
0325     rev = sl82c105_bridge_revision(dev);
0326
0327     if (rev == -1)
0328         dev_warn(&dev->dev,
0329              "pata_sl82c105: Unable to find bridge, disabling DMA\n");
0330     else if (rev <= 5)
0331         dev_warn(&dev->dev,
0332              "pata_sl82c105: Early bridge revision, no DMA available\n");
0333     else
0334         ppi[0] = &info_dma;
0335
0336     sl82c105_fixup(dev);
0337
0338     return ata_pci_bmdma_init_one(dev, ppi, &sl82c105_sht, NULL, 0);
0339 }
0340
0341 #ifdef CONFIG_PM_SLEEP
0342 static int sl82c105_reinit_one(struct pci_dev *pdev)
0343 {
0344     struct ata_host *host = pci_get_drvdata(pdev);
0345     int rc;
0346
0347     rc = ata_pci_device_do_resume(pdev);
0348     if (rc)
0349         return rc;
0350
0351     sl82c105_fixup(pdev);
0352
0353     ata_host_resume(host);
0354     return 0;
0355 }
0356 #endif
0357
0358 static const struct pci_device_id sl82c105[] = {
0359     { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },
0360
0361     { },
0362 };
0363
0364 static struct pci_driver sl82c105_pci_driver = {
0365     .name       = DRV_NAME,
0366     .id_table   = sl82c105,
0367     .probe      = sl82c105_init_one,
0368     .remove     = ata_pci_remove_one,
0369 #ifdef CONFIG_PM_SLEEP
0370     .suspend    = ata_pci_device_suspend,
0371     .resume     = sl82c105_reinit_one,
0372 #endif
0373 };
0374
0375 module_pci_driver(sl82c105_pci_driver);
0376
0377 MODULE_AUTHOR("Alan Cox");
0378 MODULE_DESCRIPTION("low-level driver for Sl82c105");
0379 MODULE_LICENSE("GPL");
0380 MODULE_DEVICE_TABLE(pci, sl82c105);
0381 MODULE_VERSION(DRV_VERSION);