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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *    pata_sis.c - SiS ATA driver
0004  *
0005  *  (C) 2005 Red Hat
0006  *  (C) 2007,2009 Bartlomiej Zolnierkiewicz
0007  *
0008  *    Based upon linux/drivers/ide/pci/sis5513.c
0009  * Copyright (C) 1999-2000  Andre Hedrick <andre@linux-ide.org>
0010  * Copyright (C) 2002       Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
0011  * Copyright (C) 2003       Vojtech Pavlik <vojtech@suse.cz>
0012  * SiS Taiwan       : for direct support and hardware.
0013  * Daniela Engert   : for initial ATA100 advices and numerous others.
0014  * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt    :
0015  *            for checking code correctness, providing patches.
0016  * Original tests and design on the SiS620 chipset.
0017  * ATA100 tests and design on the SiS735 chipset.
0018  * ATA16/33 support from specs
0019  * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
0020  *
0021  *
0022  *  TODO
0023  *  Check MWDMA on drives that don't support MWDMA speed pio cycles ?
0024  *  More Testing
0025  */
0026 
0027 #include <linux/kernel.h>
0028 #include <linux/module.h>
0029 #include <linux/pci.h>
0030 #include <linux/blkdev.h>
0031 #include <linux/delay.h>
0032 #include <linux/device.h>
0033 #include <scsi/scsi_host.h>
0034 #include <linux/libata.h>
0035 #include <linux/ata.h>
0036 #include "sis.h"
0037 
0038 #define DRV_NAME    "pata_sis"
0039 #define DRV_VERSION "0.5.2"
0040 
0041 struct sis_chipset {
0042     u16 device;             /* PCI host ID */
0043     const struct ata_port_info *info;   /* Info block */
0044     /* Probably add family, cable detect type etc here to clean
0045        up code later */
0046 };
0047 
0048 struct sis_laptop {
0049     u16 device;
0050     u16 subvendor;
0051     u16 subdevice;
0052 };
0053 
0054 static const struct sis_laptop sis_laptop[] = {
0055     /* devid, subvendor, subdev */
0056     { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
0057     { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */
0058     { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
0059     /* end marker */
0060     { 0, }
0061 };
0062 
0063 static int sis_short_ata40(struct pci_dev *dev)
0064 {
0065     const struct sis_laptop *lap = &sis_laptop[0];
0066 
0067     while (lap->device) {
0068         if (lap->device == dev->device &&
0069             lap->subvendor == dev->subsystem_vendor &&
0070             lap->subdevice == dev->subsystem_device)
0071             return 1;
0072         lap++;
0073     }
0074 
0075     return 0;
0076 }
0077 
0078 /**
0079  *  sis_old_port_base - return PCI configuration base for dev
0080  *  @adev: device
0081  *
0082  *  Returns the base of the PCI configuration registers for this port
0083  *  number.
0084  */
0085 
0086 static int sis_old_port_base(struct ata_device *adev)
0087 {
0088     return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno);
0089 }
0090 
0091 /**
0092  *  sis_port_base - return PCI configuration base for dev
0093  *  @adev: device
0094  *
0095  *  Returns the base of the PCI configuration registers for this port
0096  *  number.
0097  */
0098 
0099 static int sis_port_base(struct ata_device *adev)
0100 {
0101     struct ata_port *ap = adev->link->ap;
0102     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0103     int port = 0x40;
0104     u32 reg54;
0105 
0106     /* If bit 30 is set then the registers are mapped at 0x70 not 0x40 */
0107     pci_read_config_dword(pdev, 0x54, &reg54);
0108     if (reg54 & 0x40000000)
0109         port = 0x70;
0110 
0111     return port + (8 * ap->port_no) + (4 * adev->devno);
0112 }
0113 
0114 /**
0115  *  sis_133_cable_detect - check for 40/80 pin
0116  *  @ap: Port
0117  *
0118  *  Perform cable detection for the later UDMA133 capable
0119  *  SiS chipset.
0120  */
0121 
0122 static int sis_133_cable_detect(struct ata_port *ap)
0123 {
0124     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0125     u16 tmp;
0126 
0127     /* The top bit of this register is the cable detect bit */
0128     pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
0129     if ((tmp & 0x8000) && !sis_short_ata40(pdev))
0130         return ATA_CBL_PATA40;
0131     return ATA_CBL_PATA80;
0132 }
0133 
0134 /**
0135  *  sis_66_cable_detect - check for 40/80 pin
0136  *  @ap: Port
0137  *
0138  *  Perform cable detection on the UDMA66, UDMA100 and early UDMA133
0139  *  SiS IDE controllers.
0140  */
0141 
0142 static int sis_66_cable_detect(struct ata_port *ap)
0143 {
0144     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0145     u8 tmp;
0146 
0147     /* Older chips keep cable detect in bits 4/5 of reg 0x48 */
0148     pci_read_config_byte(pdev, 0x48, &tmp);
0149     tmp >>= ap->port_no;
0150     if ((tmp & 0x10) && !sis_short_ata40(pdev))
0151         return ATA_CBL_PATA40;
0152     return ATA_CBL_PATA80;
0153 }
0154 
0155 
0156 /**
0157  *  sis_pre_reset - probe begin
0158  *  @link: ATA link
0159  *  @deadline: deadline jiffies for the operation
0160  *
0161  *  Set up cable type and use generic probe init
0162  */
0163 
0164 static int sis_pre_reset(struct ata_link *link, unsigned long deadline)
0165 {
0166     static const struct pci_bits sis_enable_bits[] = {
0167         { 0x4aU, 1U, 0x02UL, 0x02UL },  /* port 0 */
0168         { 0x4aU, 1U, 0x04UL, 0x04UL },  /* port 1 */
0169     };
0170 
0171     struct ata_port *ap = link->ap;
0172     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0173 
0174     if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
0175         return -ENOENT;
0176 
0177     /* Clear the FIFO settings. We can't enable the FIFO until
0178        we know we are poking at a disk */
0179     pci_write_config_byte(pdev, 0x4B, 0);
0180     return ata_sff_prereset(link, deadline);
0181 }
0182 
0183 
0184 /**
0185  *  sis_set_fifo - Set RWP fifo bits for this device
0186  *  @ap: Port
0187  *  @adev: Device
0188  *
0189  *  SIS chipsets implement prefetch/postwrite bits for each device
0190  *  on both channels. This functionality is not ATAPI compatible and
0191  *  must be configured according to the class of device present
0192  */
0193 
0194 static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
0195 {
0196     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0197     u8 fifoctrl;
0198     u8 mask = 0x11;
0199 
0200     mask <<= (2 * ap->port_no);
0201     mask <<= adev->devno;
0202 
0203     /* This holds various bits including the FIFO control */
0204     pci_read_config_byte(pdev, 0x4B, &fifoctrl);
0205     fifoctrl &= ~mask;
0206 
0207     /* Enable for ATA (disk) only */
0208     if (adev->class == ATA_DEV_ATA)
0209         fifoctrl |= mask;
0210     pci_write_config_byte(pdev, 0x4B, fifoctrl);
0211 }
0212 
0213 /**
0214  *  sis_old_set_piomode - Initialize host controller PATA PIO timings
0215  *  @ap: Port whose timings we are configuring
0216  *  @adev: Device we are configuring for.
0217  *
0218  *  Set PIO mode for device, in host controller PCI config space. This
0219  *  function handles PIO set up for all chips that are pre ATA100 and
0220  *  also early ATA100 devices.
0221  *
0222  *  LOCKING:
0223  *  None (inherited from caller).
0224  */
0225 
0226 static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
0227 {
0228     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0229     int port = sis_old_port_base(adev);
0230     u8 t1, t2;
0231     int speed = adev->pio_mode - XFER_PIO_0;
0232 
0233     static const u8 active[]   = { 0x00, 0x07, 0x04, 0x03, 0x01 };
0234     static const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
0235 
0236     sis_set_fifo(ap, adev);
0237 
0238     pci_read_config_byte(pdev, port, &t1);
0239     pci_read_config_byte(pdev, port + 1, &t2);
0240 
0241     t1 &= ~0x0F;    /* Clear active/recovery timings */
0242     t2 &= ~0x07;
0243 
0244     t1 |= active[speed];
0245     t2 |= recovery[speed];
0246 
0247     pci_write_config_byte(pdev, port, t1);
0248     pci_write_config_byte(pdev, port + 1, t2);
0249 }
0250 
0251 /**
0252  *  sis_100_set_piomode - Initialize host controller PATA PIO timings
0253  *  @ap: Port whose timings we are configuring
0254  *  @adev: Device we are configuring for.
0255  *
0256  *  Set PIO mode for device, in host controller PCI config space. This
0257  *  function handles PIO set up for ATA100 devices and early ATA133.
0258  *
0259  *  LOCKING:
0260  *  None (inherited from caller).
0261  */
0262 
0263 static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
0264 {
0265     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0266     int port = sis_old_port_base(adev);
0267     int speed = adev->pio_mode - XFER_PIO_0;
0268 
0269     static const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
0270 
0271     sis_set_fifo(ap, adev);
0272 
0273     pci_write_config_byte(pdev, port, actrec[speed]);
0274 }
0275 
0276 /**
0277  *  sis_133_set_piomode - Initialize host controller PATA PIO timings
0278  *  @ap: Port whose timings we are configuring
0279  *  @adev: Device we are configuring for.
0280  *
0281  *  Set PIO mode for device, in host controller PCI config space. This
0282  *  function handles PIO set up for the later ATA133 devices.
0283  *
0284  *  LOCKING:
0285  *  None (inherited from caller).
0286  */
0287 
0288 static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
0289 {
0290     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0291     int port;
0292     u32 t1;
0293     int speed = adev->pio_mode - XFER_PIO_0;
0294 
0295     static const u32 timing133[] = {
0296         0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
0297         0x0C266000,
0298         0x04263000,
0299         0x0C0A3000,
0300         0x05093000
0301     };
0302     static const u32 timing100[] = {
0303         0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
0304         0x091C4000,
0305         0x031C2000,
0306         0x09072000,
0307         0x04062000
0308     };
0309 
0310     sis_set_fifo(ap, adev);
0311 
0312     port = sis_port_base(adev);
0313     pci_read_config_dword(pdev, port, &t1);
0314     t1 &= 0xC0C00FFF;   /* Mask out timing */
0315 
0316     if (t1 & 0x08)      /* 100 or 133 ? */
0317         t1 |= timing133[speed];
0318     else
0319         t1 |= timing100[speed];
0320     pci_write_config_byte(pdev, port, t1);
0321 }
0322 
0323 /**
0324  *  sis_old_set_dmamode - Initialize host controller PATA DMA timings
0325  *  @ap: Port whose timings we are configuring
0326  *  @adev: Device to program
0327  *
0328  *  Set UDMA/MWDMA mode for device, in host controller PCI config space.
0329  *  Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
0330  *  the old ide/pci driver.
0331  *
0332  *  LOCKING:
0333  *  None (inherited from caller).
0334  */
0335 
0336 static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
0337 {
0338     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0339     int speed = adev->dma_mode - XFER_MW_DMA_0;
0340     int drive_pci = sis_old_port_base(adev);
0341     u16 timing;
0342 
0343     static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
0344     static const u16 udma_bits[]  = { 0xE000, 0xC000, 0xA000 };
0345 
0346     pci_read_config_word(pdev, drive_pci, &timing);
0347 
0348     if (adev->dma_mode < XFER_UDMA_0) {
0349         /* bits 3-0 hold recovery timing bits 8-10 active timing and
0350            the higher bits are dependent on the device */
0351         timing &= ~0x870F;
0352         timing |= mwdma_bits[speed];
0353     } else {
0354         /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
0355         speed = adev->dma_mode - XFER_UDMA_0;
0356         timing &= ~0x6000;
0357         timing |= udma_bits[speed];
0358     }
0359     pci_write_config_word(pdev, drive_pci, timing);
0360 }
0361 
0362 /**
0363  *  sis_66_set_dmamode - Initialize host controller PATA DMA timings
0364  *  @ap: Port whose timings we are configuring
0365  *  @adev: Device to program
0366  *
0367  *  Set UDMA/MWDMA mode for device, in host controller PCI config space.
0368  *  Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
0369  *  the old ide/pci driver.
0370  *
0371  *  LOCKING:
0372  *  None (inherited from caller).
0373  */
0374 
0375 static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
0376 {
0377     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0378     int speed = adev->dma_mode - XFER_MW_DMA_0;
0379     int drive_pci = sis_old_port_base(adev);
0380     u16 timing;
0381 
0382     /* MWDMA 0-2 and UDMA 0-5 */
0383     static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
0384     static const u16 udma_bits[]  = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 };
0385 
0386     pci_read_config_word(pdev, drive_pci, &timing);
0387 
0388     if (adev->dma_mode < XFER_UDMA_0) {
0389         /* bits 3-0 hold recovery timing bits 8-10 active timing and
0390            the higher bits are dependent on the device, bit 15 udma */
0391         timing &= ~0x870F;
0392         timing |= mwdma_bits[speed];
0393     } else {
0394         /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
0395         speed = adev->dma_mode - XFER_UDMA_0;
0396         timing &= ~0xF000;
0397         timing |= udma_bits[speed];
0398     }
0399     pci_write_config_word(pdev, drive_pci, timing);
0400 }
0401 
0402 /**
0403  *  sis_100_set_dmamode - Initialize host controller PATA DMA timings
0404  *  @ap: Port whose timings we are configuring
0405  *  @adev: Device to program
0406  *
0407  *  Set UDMA/MWDMA mode for device, in host controller PCI config space.
0408  *  Handles UDMA66 and early UDMA100 devices.
0409  *
0410  *  LOCKING:
0411  *  None (inherited from caller).
0412  */
0413 
0414 static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
0415 {
0416     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0417     int speed = adev->dma_mode - XFER_MW_DMA_0;
0418     int drive_pci = sis_old_port_base(adev);
0419     u8 timing;
0420 
0421     static const u8 udma_bits[]  = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81};
0422 
0423     pci_read_config_byte(pdev, drive_pci + 1, &timing);
0424 
0425     if (adev->dma_mode < XFER_UDMA_0) {
0426         /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
0427     } else {
0428         /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
0429         speed = adev->dma_mode - XFER_UDMA_0;
0430         timing &= ~0x8F;
0431         timing |= udma_bits[speed];
0432     }
0433     pci_write_config_byte(pdev, drive_pci + 1, timing);
0434 }
0435 
0436 /**
0437  *  sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
0438  *  @ap: Port whose timings we are configuring
0439  *  @adev: Device to program
0440  *
0441  *  Set UDMA/MWDMA mode for device, in host controller PCI config space.
0442  *  Handles early SiS 961 bridges.
0443  *
0444  *  LOCKING:
0445  *  None (inherited from caller).
0446  */
0447 
0448 static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
0449 {
0450     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0451     int speed = adev->dma_mode - XFER_MW_DMA_0;
0452     int drive_pci = sis_old_port_base(adev);
0453     u8 timing;
0454     /* Low 4 bits are timing */
0455     static const u8 udma_bits[]  = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81};
0456 
0457     pci_read_config_byte(pdev, drive_pci + 1, &timing);
0458 
0459     if (adev->dma_mode < XFER_UDMA_0) {
0460         /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
0461     } else {
0462         /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
0463         speed = adev->dma_mode - XFER_UDMA_0;
0464         timing &= ~0x8F;
0465         timing |= udma_bits[speed];
0466     }
0467     pci_write_config_byte(pdev, drive_pci + 1, timing);
0468 }
0469 
0470 /**
0471  *  sis_133_set_dmamode - Initialize host controller PATA DMA timings
0472  *  @ap: Port whose timings we are configuring
0473  *  @adev: Device to program
0474  *
0475  *  Set UDMA/MWDMA mode for device, in host controller PCI config space.
0476  *
0477  *  LOCKING:
0478  *  None (inherited from caller).
0479  */
0480 
0481 static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
0482 {
0483     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0484     int port;
0485     u32 t1;
0486 
0487     port = sis_port_base(adev);
0488     pci_read_config_dword(pdev, port, &t1);
0489 
0490     if (adev->dma_mode < XFER_UDMA_0) {
0491         /* Recovery << 24 | Act << 16 | Ini << 12, like PIO modes */
0492         static const u32 timing_u100[] = { 0x19154000, 0x06072000, 0x04062000 };
0493         static const u32 timing_u133[] = { 0x221C6000, 0x0C0A3000, 0x05093000 };
0494         int speed = adev->dma_mode - XFER_MW_DMA_0;
0495 
0496         t1 &= 0xC0C00FFF;
0497         /* disable UDMA */
0498         t1 &= ~0x00000004;
0499         if (t1 & 0x08)
0500             t1 |= timing_u133[speed];
0501         else
0502             t1 |= timing_u100[speed];
0503     } else {
0504         /* bits 4- cycle time 8 - cvs time */
0505         static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
0506         static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
0507         int speed = adev->dma_mode - XFER_UDMA_0;
0508 
0509         t1 &= ~0x00000FF0;
0510         /* enable UDMA */
0511         t1 |= 0x00000004;
0512         if (t1 & 0x08)
0513             t1 |= timing_u133[speed];
0514         else
0515             t1 |= timing_u100[speed];
0516     }
0517     pci_write_config_dword(pdev, port, t1);
0518 }
0519 
0520 /**
0521  *  sis_133_mode_filter - mode selection filter
0522  *  @adev: ATA device
0523  *  @mask: received mask to manipulate and pass back
0524  *
0525  *  Block UDMA6 on devices that do not support it.
0526  */
0527 
0528 static unsigned int sis_133_mode_filter(struct ata_device *adev, unsigned int mask)
0529 {
0530     struct ata_port *ap = adev->link->ap;
0531     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0532     int port = sis_port_base(adev);
0533     u32 t1;
0534 
0535     pci_read_config_dword(pdev, port, &t1);
0536     /* if ATA133 is disabled, mask it out */
0537     if (!(t1 & 0x08))
0538         mask &= ~(0xC0 << ATA_SHIFT_UDMA);
0539     return mask;
0540 }
0541 
0542 static struct scsi_host_template sis_sht = {
0543     ATA_BMDMA_SHT(DRV_NAME),
0544 };
0545 
0546 static struct ata_port_operations sis_133_for_sata_ops = {
0547     .inherits       = &ata_bmdma_port_ops,
0548     .set_piomode        = sis_133_set_piomode,
0549     .set_dmamode        = sis_133_set_dmamode,
0550     .cable_detect       = sis_133_cable_detect,
0551 };
0552 
0553 static struct ata_port_operations sis_base_ops = {
0554     .inherits       = &ata_bmdma_port_ops,
0555     .prereset       = sis_pre_reset,
0556 };
0557 
0558 static struct ata_port_operations sis_133_ops = {
0559     .inherits       = &sis_base_ops,
0560     .set_piomode        = sis_133_set_piomode,
0561     .set_dmamode        = sis_133_set_dmamode,
0562     .cable_detect       = sis_133_cable_detect,
0563     .mode_filter        = sis_133_mode_filter,
0564 };
0565 
0566 static struct ata_port_operations sis_133_early_ops = {
0567     .inherits       = &sis_base_ops,
0568     .set_piomode        = sis_100_set_piomode,
0569     .set_dmamode        = sis_133_early_set_dmamode,
0570     .cable_detect       = sis_66_cable_detect,
0571 };
0572 
0573 static struct ata_port_operations sis_100_ops = {
0574     .inherits       = &sis_base_ops,
0575     .set_piomode        = sis_100_set_piomode,
0576     .set_dmamode        = sis_100_set_dmamode,
0577     .cable_detect       = sis_66_cable_detect,
0578 };
0579 
0580 static struct ata_port_operations sis_66_ops = {
0581     .inherits       = &sis_base_ops,
0582     .set_piomode        = sis_old_set_piomode,
0583     .set_dmamode        = sis_66_set_dmamode,
0584     .cable_detect       = sis_66_cable_detect,
0585 };
0586 
0587 static struct ata_port_operations sis_old_ops = {
0588     .inherits       = &sis_base_ops,
0589     .set_piomode        = sis_old_set_piomode,
0590     .set_dmamode        = sis_old_set_dmamode,
0591     .cable_detect       = ata_cable_40wire,
0592 };
0593 
0594 static const struct ata_port_info sis_info = {
0595     .flags      = ATA_FLAG_SLAVE_POSS,
0596     .pio_mask   = ATA_PIO4,
0597     .mwdma_mask = ATA_MWDMA2,
0598     /* No UDMA */
0599     .port_ops   = &sis_old_ops,
0600 };
0601 static const struct ata_port_info sis_info33 = {
0602     .flags      = ATA_FLAG_SLAVE_POSS,
0603     .pio_mask   = ATA_PIO4,
0604     .mwdma_mask = ATA_MWDMA2,
0605     .udma_mask  = ATA_UDMA2,
0606     .port_ops   = &sis_old_ops,
0607 };
0608 static const struct ata_port_info sis_info66 = {
0609     .flags      = ATA_FLAG_SLAVE_POSS,
0610     .pio_mask   = ATA_PIO4,
0611     /* No MWDMA */
0612     .udma_mask  = ATA_UDMA4,
0613     .port_ops   = &sis_66_ops,
0614 };
0615 static const struct ata_port_info sis_info100 = {
0616     .flags      = ATA_FLAG_SLAVE_POSS,
0617     .pio_mask   = ATA_PIO4,
0618     /* No MWDMA */
0619     .udma_mask  = ATA_UDMA5,
0620     .port_ops   = &sis_100_ops,
0621 };
0622 static const struct ata_port_info sis_info100_early = {
0623     .flags      = ATA_FLAG_SLAVE_POSS,
0624     .pio_mask   = ATA_PIO4,
0625     /* No MWDMA */
0626     .udma_mask  = ATA_UDMA5,
0627     .port_ops   = &sis_66_ops,
0628 };
0629 static const struct ata_port_info sis_info133 = {
0630     .flags      = ATA_FLAG_SLAVE_POSS,
0631     .pio_mask   = ATA_PIO4,
0632     .mwdma_mask = ATA_MWDMA2,
0633     .udma_mask  = ATA_UDMA6,
0634     .port_ops   = &sis_133_ops,
0635 };
0636 const struct ata_port_info sis_info133_for_sata = {
0637     .flags      = ATA_FLAG_SLAVE_POSS,
0638     .pio_mask   = ATA_PIO4,
0639     /* No MWDMA */
0640     .udma_mask  = ATA_UDMA6,
0641     .port_ops   = &sis_133_for_sata_ops,
0642 };
0643 static const struct ata_port_info sis_info133_early = {
0644     .flags      = ATA_FLAG_SLAVE_POSS,
0645     .pio_mask   = ATA_PIO4,
0646     /* No MWDMA */
0647     .udma_mask  = ATA_UDMA6,
0648     .port_ops   = &sis_133_early_ops,
0649 };
0650 
0651 /* Privately shared with the SiS180 SATA driver, not for use elsewhere */
0652 EXPORT_SYMBOL_GPL(sis_info133_for_sata);
0653 
0654 static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
0655 {
0656     u16 regw;
0657     u8 reg;
0658 
0659     if (sis->info == &sis_info133) {
0660         pci_read_config_word(pdev, 0x50, &regw);
0661         if (regw & 0x08)
0662             pci_write_config_word(pdev, 0x50, regw & ~0x08);
0663         pci_read_config_word(pdev, 0x52, &regw);
0664         if (regw & 0x08)
0665             pci_write_config_word(pdev, 0x52, regw & ~0x08);
0666         return;
0667     }
0668 
0669     if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
0670         /* Fix up latency */
0671         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
0672         /* Set compatibility bit */
0673         pci_read_config_byte(pdev, 0x49, &reg);
0674         if (!(reg & 0x01))
0675             pci_write_config_byte(pdev, 0x49, reg | 0x01);
0676         return;
0677     }
0678 
0679     if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
0680         /* Fix up latency */
0681         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
0682         /* Set compatibility bit */
0683         pci_read_config_byte(pdev, 0x52, &reg);
0684         if (!(reg & 0x04))
0685             pci_write_config_byte(pdev, 0x52, reg | 0x04);
0686         return;
0687     }
0688 
0689     if (sis->info == &sis_info33) {
0690         pci_read_config_byte(pdev, PCI_CLASS_PROG, &reg);
0691         if (( reg & 0x0F ) != 0x00)
0692             pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
0693         /* Fall through to ATA16 fixup below */
0694     }
0695 
0696     if (sis->info == &sis_info || sis->info == &sis_info33) {
0697         /* force per drive recovery and active timings
0698            needed on ATA_33 and below chips */
0699         pci_read_config_byte(pdev, 0x52, &reg);
0700         if (!(reg & 0x08))
0701             pci_write_config_byte(pdev, 0x52, reg|0x08);
0702         return;
0703     }
0704 
0705     BUG();
0706 }
0707 
0708 /**
0709  *  sis_init_one - Register SiS ATA PCI device with kernel services
0710  *  @pdev: PCI device to register
0711  *  @ent: Entry in sis_pci_tbl matching with @pdev
0712  *
0713  *  Called from kernel PCI layer. We probe for combined mode (sigh),
0714  *  and then hand over control to libata, for it to do the rest.
0715  *
0716  *  LOCKING:
0717  *  Inherited from PCI layer (may sleep).
0718  *
0719  *  RETURNS:
0720  *  Zero on success, or -ERRNO value.
0721  */
0722 
0723 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
0724 {
0725     const struct ata_port_info *ppi[] = { NULL, NULL };
0726     struct pci_dev *host = NULL;
0727     struct sis_chipset *chipset = NULL;
0728     struct sis_chipset *sets;
0729     int rc;
0730 
0731     static struct sis_chipset sis_chipsets[] = {
0732 
0733         { 0x0968, &sis_info133 },
0734         { 0x0966, &sis_info133 },
0735         { 0x0965, &sis_info133 },
0736         { 0x0745, &sis_info100 },
0737         { 0x0735, &sis_info100 },
0738         { 0x0733, &sis_info100 },
0739         { 0x0635, &sis_info100 },
0740         { 0x0633, &sis_info100 },
0741 
0742         { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
0743         { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
0744 
0745         { 0x0640, &sis_info66 },
0746         { 0x0630, &sis_info66 },
0747         { 0x0620, &sis_info66 },
0748         { 0x0540, &sis_info66 },
0749         { 0x0530, &sis_info66 },
0750 
0751         { 0x5600, &sis_info33 },
0752         { 0x5598, &sis_info33 },
0753         { 0x5597, &sis_info33 },
0754         { 0x5591, &sis_info33 },
0755         { 0x5582, &sis_info33 },
0756         { 0x5581, &sis_info33 },
0757 
0758         { 0x5596, &sis_info },
0759         { 0x5571, &sis_info },
0760         { 0x5517, &sis_info },
0761         { 0x5511, &sis_info },
0762 
0763         {0}
0764     };
0765     static struct sis_chipset sis133_early = {
0766         0x0, &sis_info133_early
0767     };
0768     static struct sis_chipset sis133 = {
0769         0x0, &sis_info133
0770     };
0771     static struct sis_chipset sis100_early = {
0772         0x0, &sis_info100_early
0773     };
0774     static struct sis_chipset sis100 = {
0775         0x0, &sis_info100
0776     };
0777 
0778     ata_print_version_once(&pdev->dev, DRV_VERSION);
0779 
0780     rc = pcim_enable_device(pdev);
0781     if (rc)
0782         return rc;
0783 
0784     /* We have to find the bridge first */
0785     for (sets = &sis_chipsets[0]; sets->device; sets++) {
0786         host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL);
0787         if (host != NULL) {
0788             chipset = sets;         /* Match found */
0789             if (sets->device == 0x630) {    /* SIS630 */
0790                 if (host->revision >= 0x30) /* 630 ET */
0791                     chipset = &sis100_early;
0792             }
0793             break;
0794         }
0795     }
0796 
0797     /* Look for concealed bridges */
0798     if (chipset == NULL) {
0799         /* Second check */
0800         u32 idemisc;
0801         u16 trueid;
0802 
0803         /* Disable ID masking and register remapping then
0804            see what the real ID is */
0805 
0806         pci_read_config_dword(pdev, 0x54, &idemisc);
0807         pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
0808         pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
0809         pci_write_config_dword(pdev, 0x54, idemisc);
0810 
0811         switch(trueid) {
0812         case 0x5518:    /* SIS 962/963 */
0813             dev_info(&pdev->dev,
0814                  "SiS 962/963 MuTIOL IDE UDMA133 controller\n");
0815             chipset = &sis133;
0816             if ((idemisc & 0x40000000) == 0) {
0817                 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
0818                 dev_info(&pdev->dev,
0819                      "Switching to 5513 register mapping\n");
0820             }
0821             break;
0822         case 0x0180:    /* SIS 965/965L */
0823             chipset = &sis133;
0824             break;
0825         case 0x1180:    /* SIS 966/966L */
0826             chipset = &sis133;
0827             break;
0828         }
0829     }
0830 
0831     /* Further check */
0832     if (chipset == NULL) {
0833         struct pci_dev *lpc_bridge;
0834         u16 trueid;
0835         u8 prefctl;
0836         u8 idecfg;
0837 
0838         /* Try the second unmasking technique */
0839         pci_read_config_byte(pdev, 0x4a, &idecfg);
0840         pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
0841         pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
0842         pci_write_config_byte(pdev, 0x4a, idecfg);
0843 
0844         switch(trueid) {
0845         case 0x5517:
0846             lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
0847             if (lpc_bridge == NULL)
0848                 break;
0849             pci_read_config_byte(pdev, 0x49, &prefctl);
0850             pci_dev_put(lpc_bridge);
0851 
0852             if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
0853                 chipset = &sis133_early;
0854                 break;
0855             }
0856             chipset = &sis100;
0857             break;
0858         }
0859     }
0860     pci_dev_put(host);
0861 
0862     /* No chipset info, no support */
0863     if (chipset == NULL)
0864         return -ENODEV;
0865 
0866     ppi[0] = chipset->info;
0867 
0868     sis_fixup(pdev, chipset);
0869 
0870     return ata_pci_bmdma_init_one(pdev, ppi, &sis_sht, chipset, 0);
0871 }
0872 
0873 #ifdef CONFIG_PM_SLEEP
0874 static int sis_reinit_one(struct pci_dev *pdev)
0875 {
0876     struct ata_host *host = pci_get_drvdata(pdev);
0877     int rc;
0878 
0879     rc = ata_pci_device_do_resume(pdev);
0880     if (rc)
0881         return rc;
0882 
0883     sis_fixup(pdev, host->private_data);
0884 
0885     ata_host_resume(host);
0886     return 0;
0887 }
0888 #endif
0889 
0890 static const struct pci_device_id sis_pci_tbl[] = {
0891     { PCI_VDEVICE(SI, 0x5513), },   /* SiS 5513 */
0892     { PCI_VDEVICE(SI, 0x5518), },   /* SiS 5518 */
0893     { PCI_VDEVICE(SI, 0x1180), },   /* SiS 1180 */
0894 
0895     { }
0896 };
0897 
0898 static struct pci_driver sis_pci_driver = {
0899     .name           = DRV_NAME,
0900     .id_table       = sis_pci_tbl,
0901     .probe          = sis_init_one,
0902     .remove         = ata_pci_remove_one,
0903 #ifdef CONFIG_PM_SLEEP
0904     .suspend        = ata_pci_device_suspend,
0905     .resume         = sis_reinit_one,
0906 #endif
0907 };
0908 
0909 module_pci_driver(sis_pci_driver);
0910 
0911 MODULE_AUTHOR("Alan Cox");
0912 MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
0913 MODULE_LICENSE("GPL");
0914 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
0915 MODULE_VERSION(DRV_VERSION);
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