drivers/ata/pata_sil680.c

0001 /*
0002  * pata_sil680.c    - SIL680 PATA for new ATA layer
0003  *            (C) 2005 Red Hat Inc
0004  *
0005  * based upon
0006  *
0007  * linux/drivers/ide/pci/siimage.c      Version 1.07    Nov 30, 2003
0008  *
0009  * Copyright (C) 2001-2002  Andre Hedrick <andre@linux-ide.org>
0010  * Copyright (C) 2003       Red Hat <alan@redhat.com>
0011  *
0012  *  May be copied or modified under the terms of the GNU General Public License
0013  *
0014  *  Documentation publicly available.
0015  *
0016  *  If you have strange problems with nVidia chipset systems please
0017  *  see the SI support documentation and update your system BIOS
0018  *  if necessary
0019  *
0020  * TODO
0021  *  If we know all our devices are LBA28 (or LBA28 sized)  we could use
0022  *  the command fifo mode.
0023  */
0024
0025 #include <linux/kernel.h>
0026 #include <linux/module.h>
0027 #include <linux/pci.h>
0028 #include <linux/blkdev.h>
0029 #include <linux/delay.h>
0030 #include <scsi/scsi_host.h>
0031 #include <linux/libata.h>
0032
0033 #define DRV_NAME "pata_sil680"
0034 #define DRV_VERSION "0.4.9"
0035
0036 #define SIL680_MMIO_BAR     5
0037
0038 /**
0039  *  sil680_selreg       -   return register base
0040  *  @ap: ATA interface
0041  *  @r: config offset
0042  *
0043  *  Turn a config register offset into the right address in PCI space
0044  *  to access the control register in question.
0045  *
0046  *  Thankfully this is a configuration operation so isn't performance
0047  *  criticial.
0048  */
0049
0050 static int sil680_selreg(struct ata_port *ap, int r)
0051 {
0052     return 0xA0 + (ap->port_no << 4) + r;
0053 }
0054
0055 /**
0056  *  sil680_seldev       -   return register base
0057  *  @ap: ATA interface
0058  *  @adev: ATA device
0059  *  @r: config offset
0060  *
0061  *  Turn a config register offset into the right address in PCI space
0062  *  to access the control register in question including accounting for
0063  *  the unit shift.
0064  */
0065
0066 static int sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
0067 {
0068     return 0xA0 + (ap->port_no << 4) + r + (adev->devno << 1);
0069 }
0070
0071
0072 /**
0073  *  sil680_cable_detect -   cable detection
0074  *  @ap: ATA port
0075  *
0076  *  Perform cable detection. The SIL680 stores this in PCI config
0077  *  space for us.
0078  */
0079
0080 static int sil680_cable_detect(struct ata_port *ap)
0081 {
0082     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0083     int addr = sil680_selreg(ap, 0);
0084     u8 ata66;
0085
0086     pci_read_config_byte(pdev, addr, &ata66);
0087     if (ata66 & 1)
0088         return ATA_CBL_PATA80;
0089     else
0090         return ATA_CBL_PATA40;
0091 }
0092
0093 /**
0094  *  sil680_set_piomode  -   set PIO mode data
0095  *  @ap: ATA interface
0096  *  @adev: ATA device
0097  *
0098  *  Program the SIL680 registers for PIO mode. Note that the task speed
0099  *  registers are shared between the devices so we must pick the lowest
0100  *  mode for command work.
0101  */
0102
0103 static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
0104 {
0105     static const u16 speed_p[5] = {
0106         0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1
0107     };
0108     static const u16 speed_t[5] = {
0109         0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1
0110     };
0111
0112     int tfaddr = sil680_selreg(ap, 0x02);
0113     int addr = sil680_seldev(ap, adev, 0x04);
0114     int addr_mask = 0x80 + 4 * ap->port_no;
0115     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0116     int pio = adev->pio_mode - XFER_PIO_0;
0117     int lowest_pio = pio;
0118     int port_shift = 4 * adev->devno;
0119     u16 reg;
0120     u8 mode;
0121
0122     struct ata_device *pair = ata_dev_pair(adev);
0123
0124     if (pair != NULL && adev->pio_mode > pair->pio_mode)
0125         lowest_pio = pair->pio_mode - XFER_PIO_0;
0126
0127     pci_write_config_word(pdev, addr, speed_p[pio]);
0128     pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
0129
0130     pci_read_config_word(pdev, tfaddr-2, &reg);
0131     pci_read_config_byte(pdev, addr_mask, &mode);
0132
0133     reg &= ~0x0200;         /* Clear IORDY */
0134     mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */
0135
0136     if (ata_pio_need_iordy(adev)) {
0137         reg |= 0x0200;      /* Enable IORDY */
0138         mode |= 1 << port_shift;
0139     }
0140     pci_write_config_word(pdev, tfaddr-2, reg);
0141     pci_write_config_byte(pdev, addr_mask, mode);
0142 }
0143
0144 /**
0145  *  sil680_set_dmamode  -   set DMA mode data
0146  *  @ap: ATA interface
0147  *  @adev: ATA device
0148  *
0149  *  Program the MWDMA/UDMA modes for the sil680 chipset.
0150  *
0151  *  The MWDMA mode values are pulled from a lookup table
0152  *  while the chipset uses mode number for UDMA.
0153  */
0154
0155 static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0156 {
0157     static const u8 ultra_table[2][7] = {
0158         { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF },   /* 100MHz */
0159         { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 },   /* 133Mhz */
0160     };
0161     static const u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
0162
0163     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0164     int ma = sil680_seldev(ap, adev, 0x08);
0165     int ua = sil680_seldev(ap, adev, 0x0C);
0166     int addr_mask = 0x80 + 4 * ap->port_no;
0167     int port_shift = adev->devno * 4;
0168     u8 scsc, mode;
0169     u16 multi, ultra;
0170
0171     pci_read_config_byte(pdev, 0x8A, &scsc);
0172     pci_read_config_byte(pdev, addr_mask, &mode);
0173     pci_read_config_word(pdev, ma, &multi);
0174     pci_read_config_word(pdev, ua, &ultra);
0175
0176     /* Mask timing bits */
0177     ultra &= ~0x3F;
0178     mode &= ~(0x03 << port_shift);
0179
0180     /* Extract scsc */
0181     scsc = (scsc & 0x30) ? 1 : 0;
0182
0183     if (adev->dma_mode >= XFER_UDMA_0) {
0184         multi = 0x10C1;
0185         ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
0186         mode |= (0x03 << port_shift);
0187     } else {
0188         multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
0189         mode |= (0x02 << port_shift);
0190     }
0191     pci_write_config_byte(pdev, addr_mask, mode);
0192     pci_write_config_word(pdev, ma, multi);
0193     pci_write_config_word(pdev, ua, ultra);
0194 }
0195
0196 /**
0197  *  sil680_sff_exec_command - issue ATA command to host controller
0198  *  @ap: port to which command is being issued
0199  *  @tf: ATA taskfile register set
0200  *
0201  *  Issues ATA command, with proper synchronization with interrupt
0202  *  handler / other threads. Use our MMIO space for PCI posting to avoid
0203  *  a hideously slow cycle all the way to the device.
0204  *
0205  *  LOCKING:
0206  *  spin_lock_irqsave(host lock)
0207  */
0208 static void sil680_sff_exec_command(struct ata_port *ap,
0209                     const struct ata_taskfile *tf)
0210 {
0211     iowrite8(tf->command, ap->ioaddr.command_addr);
0212     ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
0213 }
0214
0215 static bool sil680_sff_irq_check(struct ata_port *ap)
0216 {
0217     struct pci_dev *pdev    = to_pci_dev(ap->host->dev);
0218     int addr        = sil680_selreg(ap, 1);
0219     u8 val;
0220
0221     pci_read_config_byte(pdev, addr, &val);
0222
0223     return val & 0x08;
0224 }
0225
0226 static struct scsi_host_template sil680_sht = {
0227     ATA_BMDMA_SHT(DRV_NAME),
0228 };
0229
0230
0231 static struct ata_port_operations sil680_port_ops = {
0232     .inherits       = &ata_bmdma32_port_ops,
0233     .sff_exec_command   = sil680_sff_exec_command,
0234     .sff_irq_check      = sil680_sff_irq_check,
0235     .cable_detect       = sil680_cable_detect,
0236     .set_piomode        = sil680_set_piomode,
0237     .set_dmamode        = sil680_set_dmamode,
0238 };
0239
0240 /**
0241  *  sil680_init_chip        -   chip setup
0242  *  @pdev: PCI device
0243  *  @try_mmio: Indicates to caller whether MMIO should be attempted
0244  *
0245  *  Perform all the chip setup which must be done both when the device
0246  *  is powered up on boot and when we resume in case we resumed from RAM.
0247  *  Returns the final clock settings.
0248  */
0249
0250 static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio)
0251 {
0252     u8 tmpbyte  = 0;
0253
0254     /* FIXME: double check */
0255     pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
0256                   pdev->revision ? 1 : 255);
0257
0258     pci_write_config_byte(pdev, 0x80, 0x00);
0259     pci_write_config_byte(pdev, 0x84, 0x00);
0260
0261     pci_read_config_byte(pdev, 0x8A, &tmpbyte);
0262
0263     dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
0264         tmpbyte & 1, tmpbyte & 0x30);
0265
0266     *try_mmio = 0;
0267 #ifdef CONFIG_PPC
0268     if (machine_is(cell))
0269         *try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5);
0270 #endif
0271
0272     switch (tmpbyte & 0x30) {
0273     case 0x00:
0274         /* 133 clock attempt to force it on */
0275         pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
0276         break;
0277     case 0x30:
0278         /* if clocking is disabled */
0279         /* 133 clock attempt to force it on */
0280         pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
0281         break;
0282     case 0x10:
0283         /* 133 already */
0284         break;
0285     case 0x20:
0286         /* BIOS set PCI x2 clocking */
0287         break;
0288     }
0289
0290     pci_read_config_byte(pdev,   0x8A, &tmpbyte);
0291     dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
0292         tmpbyte & 1, tmpbyte & 0x30);
0293
0294     pci_write_config_byte(pdev,  0xA1, 0x72);
0295     pci_write_config_word(pdev,  0xA2, 0x328A);
0296     pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
0297     pci_write_config_dword(pdev, 0xA8, 0x43924392);
0298     pci_write_config_dword(pdev, 0xAC, 0x40094009);
0299     pci_write_config_byte(pdev,  0xB1, 0x72);
0300     pci_write_config_word(pdev,  0xB2, 0x328A);
0301     pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
0302     pci_write_config_dword(pdev, 0xB8, 0x43924392);
0303     pci_write_config_dword(pdev, 0xBC, 0x40094009);
0304
0305     switch (tmpbyte & 0x30) {
0306     case 0x00:
0307         dev_info(&pdev->dev, "sil680: 100MHz clock.\n");
0308         break;
0309     case 0x10:
0310         dev_info(&pdev->dev, "sil680: 133MHz clock.\n");
0311         break;
0312     case 0x20:
0313         dev_info(&pdev->dev, "sil680: Using PCI clock.\n");
0314         break;
0315     /* This last case is _NOT_ ok */
0316     case 0x30:
0317         dev_err(&pdev->dev, "sil680: Clock disabled ?\n");
0318     }
0319     return tmpbyte & 0x30;
0320 }
0321
0322 static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
0323 {
0324     static const struct ata_port_info info = {
0325         .flags = ATA_FLAG_SLAVE_POSS,
0326         .pio_mask = ATA_PIO4,
0327         .mwdma_mask = ATA_MWDMA2,
0328         .udma_mask = ATA_UDMA6,
0329         .port_ops = &sil680_port_ops
0330     };
0331     static const struct ata_port_info info_slow = {
0332         .flags = ATA_FLAG_SLAVE_POSS,
0333         .pio_mask = ATA_PIO4,
0334         .mwdma_mask = ATA_MWDMA2,
0335         .udma_mask = ATA_UDMA5,
0336         .port_ops = &sil680_port_ops
0337     };
0338     const struct ata_port_info *ppi[] = { &info, NULL };
0339     struct ata_host *host;
0340     void __iomem *mmio_base;
0341     int rc, try_mmio;
0342
0343     ata_print_version_once(&pdev->dev, DRV_VERSION);
0344
0345     rc = pcim_enable_device(pdev);
0346     if (rc)
0347         return rc;
0348
0349     switch (sil680_init_chip(pdev, &try_mmio)) {
0350         case 0:
0351             ppi[0] = &info_slow;
0352             break;
0353         case 0x30:
0354             return -ENODEV;
0355     }
0356
0357     if (!try_mmio)
0358         goto use_ioports;
0359
0360     /* Try to acquire MMIO resources and fallback to PIO if
0361      * that fails
0362      */
0363     rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);
0364     if (rc)
0365         goto use_ioports;
0366
0367     /* Allocate host and set it up */
0368     host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
0369     if (!host)
0370         return -ENOMEM;
0371     host->iomap = pcim_iomap_table(pdev);
0372
0373     /* Setup DMA masks */
0374     rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
0375     if (rc)
0376         return rc;
0377     pci_set_master(pdev);
0378
0379     /* Get MMIO base and initialize port addresses */
0380     mmio_base = host->iomap[SIL680_MMIO_BAR];
0381     host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;
0382     host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;
0383     host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;
0384     host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;
0385     ata_sff_std_ports(&host->ports[0]->ioaddr);
0386     host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;
0387     host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;
0388     host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;
0389     host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;
0390     ata_sff_std_ports(&host->ports[1]->ioaddr);
0391
0392     /* Register & activate */
0393     return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
0394                  IRQF_SHARED, &sil680_sht);
0395
0396 use_ioports:
0397     return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0);
0398 }
0399
0400 #ifdef CONFIG_PM_SLEEP
0401 static int sil680_reinit_one(struct pci_dev *pdev)
0402 {
0403     struct ata_host *host = pci_get_drvdata(pdev);
0404     int try_mmio, rc;
0405
0406     rc = ata_pci_device_do_resume(pdev);
0407     if (rc)
0408         return rc;
0409     sil680_init_chip(pdev, &try_mmio);
0410     ata_host_resume(host);
0411     return 0;
0412 }
0413 #endif
0414
0415 static const struct pci_device_id sil680[] = {
0416     { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },
0417
0418     { },
0419 };
0420
0421 static struct pci_driver sil680_pci_driver = {
0422     .name       = DRV_NAME,
0423     .id_table   = sil680,
0424     .probe      = sil680_init_one,
0425     .remove     = ata_pci_remove_one,
0426 #ifdef CONFIG_PM_SLEEP
0427     .suspend    = ata_pci_device_suspend,
0428     .resume     = sil680_reinit_one,
0429 #endif
0430 };
0431
0432 module_pci_driver(sil680_pci_driver);
0433
0434 MODULE_AUTHOR("Alan Cox");
0435 MODULE_DESCRIPTION("low-level driver for SI680 PATA");
0436 MODULE_LICENSE("GPL");
0437 MODULE_DEVICE_TABLE(pci, sil680);
0438 MODULE_VERSION(DRV_VERSION);