drivers/ata/pata_serverworks.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * pata_serverworks.c   - Serverworks PATA for new ATA layer
0004  *            (C) 2005 Red Hat Inc
0005  *            (C) 2010 Bartlomiej Zolnierkiewicz
0006  *
0007  * based upon
0008  *
0009  * serverworks.c
0010  *
0011  * Copyright (C) 1998-2000 Michel Aubry
0012  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
0013  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
0014  * Portions copyright (c) 2001 Sun Microsystems
0015  *
0016  *
0017  * RCC/ServerWorks IDE driver for Linux
0018  *
0019  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
0020  *         supports UDMA mode 2 (33 MB/s)
0021  *
0022  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
0023  *         all revisions support UDMA mode 4 (66 MB/s)
0024  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
0025  *
0026  *         *** The CSB5 does not provide ANY register ***
0027  *         *** to detect 80-conductor cable presence. ***
0028  *
0029  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
0030  *
0031  * Documentation:
0032  *  Available under NDA only. Errata info very hard to get.
0033  */
0034
0035 #include <linux/kernel.h>
0036 #include <linux/module.h>
0037 #include <linux/pci.h>
0038 #include <linux/blkdev.h>
0039 #include <linux/delay.h>
0040 #include <scsi/scsi_host.h>
0041 #include <linux/libata.h>
0042
0043 #define DRV_NAME "pata_serverworks"
0044 #define DRV_VERSION "0.4.3"
0045
0046 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
0047 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
0048
0049 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
0050  * can overrun their FIFOs when used with the CSB5 */
0051
0052 static const char *csb_bad_ata100[] = {
0053     "ST320011A",
0054     "ST340016A",
0055     "ST360021A",
0056     "ST380021A",
0057     NULL
0058 };
0059
0060 /**
0061  *  oem_cable   -   Dell/Sun serverworks cable detection
0062  *  @ap: ATA port to do cable detect
0063  *
0064  *  Dell PowerEdge and Sun Cobalt 'Alpine' hide the 40/80 pin select
0065  *  for their interfaces in the top two bits of the subsystem ID.
0066  */
0067
0068 static int oem_cable(struct ata_port *ap)
0069 {
0070     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0071
0072     if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
0073         return ATA_CBL_PATA80;
0074     return ATA_CBL_PATA40;
0075 }
0076
0077 struct sv_cable_table {
0078     int device;
0079     int subvendor;
0080     int (*cable_detect)(struct ata_port *ap);
0081 };
0082
0083 static struct sv_cable_table cable_detect[] = {
0084     { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE,   PCI_VENDOR_ID_DELL, oem_cable },
0085     { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE,   PCI_VENDOR_ID_DELL, oem_cable },
0086     { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE,   PCI_VENDOR_ID_SUN,  oem_cable },
0087     { PCI_DEVICE_ID_SERVERWORKS_OSB4IDE,   PCI_ANY_ID, ata_cable_40wire  },
0088     { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE,   PCI_ANY_ID, ata_cable_unknown },
0089     { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE,   PCI_ANY_ID, ata_cable_unknown },
0090     { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2,  PCI_ANY_ID, ata_cable_unknown },
0091     { PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, ata_cable_unknown },
0092     { }
0093 };
0094
0095 /**
0096  *  serverworks_cable_detect    -   cable detection
0097  *  @ap: ATA port
0098  *
0099  *  Perform cable detection according to the device and subvendor
0100  *  identifications
0101  */
0102
0103 static int serverworks_cable_detect(struct ata_port *ap)
0104 {
0105     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0106     struct sv_cable_table *cb = cable_detect;
0107
0108     while(cb->device) {
0109         if (cb->device == pdev->device &&
0110             (cb->subvendor == pdev->subsystem_vendor ||
0111               cb->subvendor == PCI_ANY_ID)) {
0112             return cb->cable_detect(ap);
0113         }
0114         cb++;
0115     }
0116
0117     BUG();
0118     return -1;  /* kill compiler warning */
0119 }
0120
0121 /**
0122  *  serverworks_is_csb  -   Check for CSB or OSB
0123  *  @pdev: PCI device to check
0124  *
0125  *  Returns true if the device being checked is known to be a CSB
0126  *  series device.
0127  */
0128
0129 static u8 serverworks_is_csb(struct pci_dev *pdev)
0130 {
0131     switch (pdev->device) {
0132         case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
0133         case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
0134         case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
0135         case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
0136             return 1;
0137         default:
0138             break;
0139     }
0140     return 0;
0141 }
0142
0143 /**
0144  *  serverworks_osb4_filter -   mode selection filter
0145  *  @adev: ATA device
0146  *  @mask: Mask of proposed modes
0147  *
0148  *  Filter the offered modes for the device to apply controller
0149  *  specific rules. OSB4 requires no UDMA for disks due to a FIFO
0150  *  bug we hit.
0151  */
0152
0153 static unsigned int serverworks_osb4_filter(struct ata_device *adev, unsigned int mask)
0154 {
0155     if (adev->class == ATA_DEV_ATA)
0156         mask &= ~ATA_MASK_UDMA;
0157     return mask;
0158 }
0159
0160
0161 /**
0162  *  serverworks_csb_filter  -   mode selection filter
0163  *  @adev: ATA device
0164  *  @mask: Mask of proposed modes
0165  *
0166  *  Check the blacklist and disable UDMA5 if matched
0167  */
0168
0169 static unsigned int serverworks_csb_filter(struct ata_device *adev, unsigned int mask)
0170 {
0171     const char *p;
0172     char model_num[ATA_ID_PROD_LEN + 1];
0173     int i;
0174
0175     /* Disk, UDMA */
0176     if (adev->class != ATA_DEV_ATA)
0177         return mask;
0178
0179     /* Actually do need to check */
0180     ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
0181
0182     for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
0183         if (!strcmp(p, model_num))
0184             mask &= ~(0xE0 << ATA_SHIFT_UDMA);
0185     }
0186     return mask;
0187 }
0188
0189 /**
0190  *  serverworks_set_piomode -   set initial PIO mode data
0191  *  @ap: ATA interface
0192  *  @adev: ATA device
0193  *
0194  *  Program the OSB4/CSB5 timing registers for PIO. The PIO register
0195  *  load is done as a simple lookup.
0196  */
0197 static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev)
0198 {
0199     static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
0200     int offset = 1 + 2 * ap->port_no - adev->devno;
0201     int devbits = (2 * ap->port_no + adev->devno) * 4;
0202     u16 csb5_pio;
0203     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0204     int pio = adev->pio_mode - XFER_PIO_0;
0205
0206     pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);
0207
0208     /* The OSB4 just requires the timing but the CSB series want the
0209        mode number as well */
0210     if (serverworks_is_csb(pdev)) {
0211         pci_read_config_word(pdev, 0x4A, &csb5_pio);
0212         csb5_pio &= ~(0x0F << devbits);
0213         pci_write_config_word(pdev, 0x4A, csb5_pio | (pio << devbits));
0214     }
0215 }
0216
0217 /**
0218  *  serverworks_set_dmamode -   set initial DMA mode data
0219  *  @ap: ATA interface
0220  *  @adev: ATA device
0221  *
0222  *  Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
0223  *  chipset. The MWDMA mode values are pulled from a lookup table
0224  *  while the chipset uses mode number for UDMA.
0225  */
0226
0227 static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0228 {
0229     static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
0230     int offset = 1 + 2 * ap->port_no - adev->devno;
0231     int devbits = 2 * ap->port_no + adev->devno;
0232     u8 ultra;
0233     u8 ultra_cfg;
0234     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0235
0236     pci_read_config_byte(pdev, 0x54, &ultra_cfg);
0237     pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
0238     ultra &= ~(0x0F << (adev->devno * 4));
0239
0240     if (adev->dma_mode >= XFER_UDMA_0) {
0241         pci_write_config_byte(pdev, 0x44 + offset,  0x20);
0242
0243         ultra |= (adev->dma_mode - XFER_UDMA_0)
0244                     << (adev->devno * 4);
0245         ultra_cfg |=  (1 << devbits);
0246     } else {
0247         pci_write_config_byte(pdev, 0x44 + offset,
0248             dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
0249         ultra_cfg &= ~(1 << devbits);
0250     }
0251     pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
0252     pci_write_config_byte(pdev, 0x54, ultra_cfg);
0253 }
0254
0255 static struct scsi_host_template serverworks_osb4_sht = {
0256     ATA_BASE_SHT(DRV_NAME),
0257     .sg_tablesize   = LIBATA_DUMB_MAX_PRD,
0258     .dma_boundary   = ATA_DMA_BOUNDARY,
0259 };
0260
0261 static struct scsi_host_template serverworks_csb_sht = {
0262     ATA_BMDMA_SHT(DRV_NAME),
0263 };
0264
0265 static struct ata_port_operations serverworks_osb4_port_ops = {
0266     .inherits   = &ata_bmdma_port_ops,
0267     .qc_prep    = ata_bmdma_dumb_qc_prep,
0268     .cable_detect   = serverworks_cable_detect,
0269     .mode_filter    = serverworks_osb4_filter,
0270     .set_piomode    = serverworks_set_piomode,
0271     .set_dmamode    = serverworks_set_dmamode,
0272 };
0273
0274 static struct ata_port_operations serverworks_csb_port_ops = {
0275     .inherits   = &serverworks_osb4_port_ops,
0276     .qc_prep    = ata_bmdma_qc_prep,
0277     .mode_filter    = serverworks_csb_filter,
0278 };
0279
0280 static int serverworks_fixup_osb4(struct pci_dev *pdev)
0281 {
0282     u32 reg;
0283     struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
0284           PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
0285     if (isa_dev) {
0286         pci_read_config_dword(isa_dev, 0x64, &reg);
0287         reg &= ~0x00002000; /* disable 600ns interrupt mask */
0288         if (!(reg & 0x00004000))
0289             dev_info(&pdev->dev, "UDMA not BIOS enabled.\n");
0290         reg |=  0x00004000; /* enable UDMA/33 support */
0291         pci_write_config_dword(isa_dev, 0x64, reg);
0292         pci_dev_put(isa_dev);
0293         return 0;
0294     }
0295     dev_warn(&pdev->dev, "Unable to find bridge.\n");
0296     return -ENODEV;
0297 }
0298
0299 static int serverworks_fixup_csb(struct pci_dev *pdev)
0300 {
0301     u8 btr;
0302
0303     /* Third Channel Test */
0304     if (!(PCI_FUNC(pdev->devfn) & 1)) {
0305         struct pci_dev * findev = NULL;
0306         u32 reg4c = 0;
0307         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
0308             PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
0309         if (findev) {
0310             pci_read_config_dword(findev, 0x4C, &reg4c);
0311             reg4c &= ~0x000007FF;
0312             reg4c |=  0x00000040;
0313             reg4c |=  0x00000020;
0314             pci_write_config_dword(findev, 0x4C, reg4c);
0315             pci_dev_put(findev);
0316         }
0317     } else {
0318         struct pci_dev * findev = NULL;
0319         u8 reg41 = 0;
0320
0321         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
0322                 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
0323         if (findev) {
0324             pci_read_config_byte(findev, 0x41, &reg41);
0325             reg41 &= ~0x40;
0326             pci_write_config_byte(findev, 0x41, reg41);
0327             pci_dev_put(findev);
0328         }
0329     }
0330     /* setup the UDMA Control register
0331      *
0332      * 1. clear bit 6 to enable DMA
0333      * 2. enable DMA modes with bits 0-1
0334      *  00 : legacy
0335      *  01 : udma2
0336      *  10 : udma2/udma4
0337      *  11 : udma2/udma4/udma5
0338      */
0339     pci_read_config_byte(pdev, 0x5A, &btr);
0340     btr &= ~0x40;
0341     if (!(PCI_FUNC(pdev->devfn) & 1))
0342         btr |= 0x2;
0343     else
0344         btr |= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
0345     pci_write_config_byte(pdev, 0x5A, btr);
0346
0347     return btr;
0348 }
0349
0350 static void serverworks_fixup_ht1000(struct pci_dev *pdev)
0351 {
0352     u8 btr;
0353     /* Setup HT1000 SouthBridge Controller - Single Channel Only */
0354     pci_read_config_byte(pdev, 0x5A, &btr);
0355     btr &= ~0x40;
0356     btr |= 0x3;
0357     pci_write_config_byte(pdev, 0x5A, btr);
0358 }
0359
0360 static int serverworks_fixup(struct pci_dev *pdev)
0361 {
0362     int rc = 0;
0363
0364     /* Force master latency timer to 64 PCI clocks */
0365     pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
0366
0367     switch (pdev->device) {
0368     case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
0369         rc = serverworks_fixup_osb4(pdev);
0370         break;
0371     case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
0372         ata_pci_bmdma_clear_simplex(pdev);
0373         fallthrough;
0374     case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
0375     case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
0376         rc = serverworks_fixup_csb(pdev);
0377         break;
0378     case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
0379         serverworks_fixup_ht1000(pdev);
0380         break;
0381     }
0382
0383     return rc;
0384 }
0385
0386 static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
0387 {
0388     static const struct ata_port_info info[4] = {
0389         { /* OSB4 */
0390             .flags = ATA_FLAG_SLAVE_POSS,
0391             .pio_mask = ATA_PIO4,
0392             .mwdma_mask = ATA_MWDMA2,
0393             .udma_mask = ATA_UDMA2,
0394             .port_ops = &serverworks_osb4_port_ops
0395         }, { /* OSB4 no UDMA */
0396             .flags = ATA_FLAG_SLAVE_POSS,
0397             .pio_mask = ATA_PIO4,
0398             .mwdma_mask = ATA_MWDMA2,
0399             /* No UDMA */
0400             .port_ops = &serverworks_osb4_port_ops
0401         }, { /* CSB5 */
0402             .flags = ATA_FLAG_SLAVE_POSS,
0403             .pio_mask = ATA_PIO4,
0404             .mwdma_mask = ATA_MWDMA2,
0405             .udma_mask = ATA_UDMA4,
0406             .port_ops = &serverworks_csb_port_ops
0407         }, { /* CSB5 - later revisions*/
0408             .flags = ATA_FLAG_SLAVE_POSS,
0409             .pio_mask = ATA_PIO4,
0410             .mwdma_mask = ATA_MWDMA2,
0411             .udma_mask = ATA_UDMA5,
0412             .port_ops = &serverworks_csb_port_ops
0413         }
0414     };
0415     const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
0416     struct scsi_host_template *sht = &serverworks_csb_sht;
0417     int rc;
0418
0419     rc = pcim_enable_device(pdev);
0420     if (rc)
0421         return rc;
0422
0423     rc = serverworks_fixup(pdev);
0424
0425     /* OSB4 : South Bridge and IDE */
0426     if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
0427         /* Select non UDMA capable OSB4 if we can't do fixups */
0428         if (rc < 0)
0429             ppi[0] = &info[1];
0430         sht = &serverworks_osb4_sht;
0431     }
0432     /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
0433     else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
0434          (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
0435          (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
0436
0437          /* If the returned btr is the newer revision then
0438             select the right info block */
0439          if (rc == 3)
0440             ppi[0] = &info[3];
0441
0442         /* Is this the 3rd channel CSB6 IDE ? */
0443         if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
0444             ppi[1] = &ata_dummy_port_info;
0445     }
0446
0447     return ata_pci_bmdma_init_one(pdev, ppi, sht, NULL, 0);
0448 }
0449
0450 #ifdef CONFIG_PM_SLEEP
0451 static int serverworks_reinit_one(struct pci_dev *pdev)
0452 {
0453     struct ata_host *host = pci_get_drvdata(pdev);
0454     int rc;
0455
0456     rc = ata_pci_device_do_resume(pdev);
0457     if (rc)
0458         return rc;
0459
0460     (void)serverworks_fixup(pdev);
0461
0462     ata_host_resume(host);
0463     return 0;
0464 }
0465 #endif
0466
0467 static const struct pci_device_id serverworks[] = {
0468     { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
0469     { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
0470     { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
0471     { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
0472     { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},
0473
0474     { },
0475 };
0476
0477 static struct pci_driver serverworks_pci_driver = {
0478     .name       = DRV_NAME,
0479     .id_table   = serverworks,
0480     .probe      = serverworks_init_one,
0481     .remove     = ata_pci_remove_one,
0482 #ifdef CONFIG_PM_SLEEP
0483     .suspend    = ata_pci_device_suspend,
0484     .resume     = serverworks_reinit_one,
0485 #endif
0486 };
0487
0488 module_pci_driver(serverworks_pci_driver);
0489
0490 MODULE_AUTHOR("Alan Cox");
0491 MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
0492 MODULE_LICENSE("GPL");
0493 MODULE_DEVICE_TABLE(pci, serverworks);
0494 MODULE_VERSION(DRV_VERSION);